CN203950254U - A kind of mainboard of Grantley platform - Google Patents
A kind of mainboard of Grantley platform Download PDFInfo
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- CN203950254U CN203950254U CN201420331147.4U CN201420331147U CN203950254U CN 203950254 U CN203950254 U CN 203950254U CN 201420331147 U CN201420331147 U CN 201420331147U CN 203950254 U CN203950254 U CN 203950254U
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Abstract
The utility model provides a kind of mainboard of Grantley platform, and this mainboard comprises CPU board module and the IO plate module being connected with power connector by signal connector.The mainboard that the utility model provides, by solidifying a few money CPU board modules, with the design IO plate module of need, by the Optional assembling of CPU board module and IO plate module, can reduce the exploitation quantity of mainboard over half at any time, correspondingly reduce man power and material's input simultaneously.
Description
Technical field
The utility model relates to a kind of mainboard of computer realm, specifically relates to a kind of mainboard of Grantley platform.
Background technology
In decades, adopt the mainboard of Intel and AMD chip architecture designs to occupy PC and more than 90% share of server market.Intel and AMD, when each release CPU of new generation, just release and have fixed simultaneously the north and south bridge of arranging in pairs or groups with CPU, and have fixed the type of memory that CPU supports, motherboard design manufacturer cannot change this.Mainboard manufacturer is only simply to select the number of CPU and internal memory, for example according to mainboard, support the number of CPU, can be designed as single channel, two-way, four tunnels, eight road mainboards, according to the number of internal memory design, can be divided into 8 internal memories, 16 internal memories, 24 internal memory mainboards.For IO part, motherboard design manufacturer can optionally change the types such as Ethernet card that design supports, SAS HBA card, SAS RAID card, GPU card, FC HBA card, IB HBA card according to the market demand, every kind of IO type has again many moneys chip can support to realize, so the mainboard of different mainboard manufacturers design is diversified.
Described in comprehensive, although motherboard design both domestic and external manufacturer is a lot, the CPU adopting, bridge sheet group and type of memory are identical, the number of the IO part of the just mainboard of variation and CPU, bridge sheet group, internal memory; Different manufacturers relies on the partial design of these variations to go out the mainboard of differentiation.
In prior art, the method of motherboard design be by all partial design such as CPU, bridge sheet group, internal memory, IO function on a complete mainboard, but this kind of way can have to redesign a complete mainboard in order to revise an IO function, this comprises the parts such as CPU, bridge sheet and internal memory that do not need change, produce expense and the relevant R & D Costs such as manpower and materials such as extra PCB production unnecessary, welding for this reason, pay very large extra cost.Just because of present motherboard design pattern, Yi Ge motherboard design manufacturer is limited to a few money mainboards that limited human and material resources can only development and maintenance minority, and strong mainboard manufacturer also only can tens sections of mainboards of development and maintenance.
Summary of the invention
For overcoming above-mentioned the deficiencies in the prior art, the utility model proposes a kind of mainboard of Grantley platform.
Realizing the solution that above-mentioned purpose adopts is:
A mainboard for Grantley platform, its improvements are: described mainboard comprises CPU board module and the IO plate module being connected with power connector by signal connector.
Further, described CPU board module comprises cpu circuit, bridge sheet group circuit, main memory circuit, BMC circuit, the signal connector of IO plate module and the power connector of power module.
Further, described IO plate module comprises network I/O circuit, storage IO circuit, PCIE groove circuit, keyboard, mouse, VGA and USB circuit.
Further, described IO plate module comprises IO submodule and power module;
Described IO submodule is connected with described CPU board module with described power connector by described signal connector respectively;
Described power module is connected with described CPU board module by described power connector.
Further, by fixing described CPU board module and the different described IO plate module of variation, be combined into polytype mainboard;
Described CPU board module connects one or two power modules, and appoints IO submodule described in one or more.
Further, described signal connector comprises male and female, the connection of the connected sum electric current of the electric signal of two modules that are connected by described male and the realization of described female.
Further, described CPU board module comprises 4 power connectors, when between described CPU board module and described IO submodule, signal connector can not provide enough electric currents, by described power connector, is that described IO submodule is powered.
Further, described power module is for adopting the power module of CRPS power supply.
Further, the interactive signal of described IO submodule and described CPU board module comprises the VGA vision signal of being drawn by BMC chip, the NCSI signal of being drawn by BMC chip, rs 232 serial interface signal, usb signal, network signal, power supply signal, accessory power supply signal, the PCIE3.0 x20 signal of being drawn by CPU.
Further, the PCIE3.0 signal of described IO plate module is from the different PCIE passage of same CPU; The NCSI signal of described IO plate module is from the NCSI signal bifurcated of same BMC and two signals that form.
Compared with prior art, the utlity model has following beneficial effect:
1, the mainboard that the utility model provides is by solidifying a few money CPU board modules, at any time with the design IO plate module of need, by the Optional assembling of CPU board module and IO plate module, can reduce the exploitation quantity of mainboard over half, correspondingly reduce man power and material's input simultaneously.
2, the PCB number of plies of a complete mainboard is the same in each region of mainboard, and the number of the number of plies is decided by the most complicated CPU part; CPU board module of the present utility model and IO plate module can adopt the different PCB numbers of plies to design, and due to IO plate module simplicity of design, so the PCB number of plies adopting is less, generally can accomplish to reduce 2～6 layers than CPU board module.Known according to the quotation of PCB production firm, pcb board is often two-layer less can be cost-saving more than at least 20% in the situation that of same area.
3, user is embodied on IO function difference the otherness overwhelming majority of mainboard demand, adopt after modularized design scheme, only need to design IO plate module and need not design monoblock mainboard and just can meet user's demand, and IO plate module design time is short, be easy to realize, processing, production, test, transportation simply, can realize full-range simplification, dirigibility.
Accompanying drawing explanation
Fig. 1 is Grantley platform motherboard modularization schematic diagram;
Fig. 2 is CPU board module embodiment schematic diagram;
Fig. 3 is IO submodule one embodiment schematic diagram;
Fig. 4 is the Four types a embodiment schematic diagram of IO submodule two, three;
Fig. 5 is the Four types b embodiment schematic diagram of IO submodule two, three;
Fig. 6 is the Four types c embodiment schematic diagram of IO submodule two, three;
Fig. 7 is the Four types d embodiment schematic diagram of IO submodule two, three;
Fig. 8 is the three types a embodiment schematic diagram of IO submodule four, five;
Fig. 9 is the three types b embodiment schematic diagram of IO submodule four, five;
Figure 10 is the three types c embodiment schematic diagram of IO submodule four, five;
Reference numeral: 1-CPU plate module; 2-IO submodule one; 3-IO submodule two; 4-IO submodule three; 5-IO submodule four; 6-IO submodule five; 7-IO submodule six; 8-IO submodule seven; 9-IO partitioned signal connector one; 10-IO partitioned signal connector two; 11-IO partitioned signal connector three; 12-IO partitioned signal connector four; 13-IO partitioned signal connector five; 14-power connector one; 15-power connector two; The male of the power connector three in 16-CPU plate module; The male of the power connector four in 17-CPU plate module; The male of the power connector five in 18-CPU plate module; The male of the power connector six in 19-CPU plate module; The female of the power connector three in 20-IO plate module; The female of the power connector four in 21-IO plate module; The female of the power connector five in 22-IO plate module; The female of the power connector six in 23-IO plate module; 24-power cable; 25-power cable; 26-power cable; 27-power cable.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in further detail.
The utility model provides a kind of mainboard of Grantley platform, according to the feature of the functional characteristics of each part of Grantley platform motherboard and PCB layout layout, mainboard is reasonably split as to several parts or module, thereby mainboard just equals the combination of several parts or module.
CPU board module comprises cpu circuit, bridge sheet group circuit, main memory circuit, BMC (Baseboard Management Controller, baseboard management controller) circuit, IO plate module signal connector and power module connector.
IO plate module comprises network I/O circuit, storage IO circuit, PCIE groove circuit, the interlock circuits such as keyboard, mouse, VGA, USB.
Between CPU board module and IO plate module, by forms such as connector or flexible PCB cables, connect.CPU board module is indeclinable part almost in a mainboard, and IO plate module is in a mainboard, to change than part more frequently.Keep CPU board module constant, and momentarily design different IO plate module according to the demand in market, then combine installation, just can design diversified different mainboard.This method for designing very flexibly, reduced technical difficulty on the one hand, shortened the research and development time, rapidly product is introduced to the market; Manpower requirement and cost have been saved on the other hand.
IO plate module comprises IO submodule and power module; IO submodule is connected with described CPU board module with described power connector by described signal connector respectively; Power module is connected with described CPU board module by described power connector.
By fixing described CPU board module and the different described IO plate module of variation, be combined into polytype mainboard; Described CPU board module connects one or two power modules, and appoints IO submodule described in one or more.
IO plate module comprises maximum five IO submodules and maximum two power modules, during motherboard design, comprises arbitrarily one or more IO submodules, and one or two power module.
In the present embodiment, Grantley platform motherboard is divided into 1 CPU board module and 7 IO submodules, as shown in Figure 1.IO submodule 67 and IO submodule 78 are two power modules, for giving CPU board module and 5 IO submodule power supplies.
Between CPU board module and 7 IO submodules, by corresponding signal connector and power connector, undertaken interconnected respectively.
Described signal connector comprises male and female, by closely cooperating of male and female realize connect the connection of two module electric signals, if be male in CPU board module, in IO plate module, be exactly female.
CPU board module 1 is connected with IO submodule 1 by IO partitioned signal connector 1; CPU board module 1 is connected with IO submodule 23 by IO partitioned signal connector 2 10; CPU board module 1 is connected with IO submodule 34 by IO partitioned signal connector 3 11; CPU board module 1 is connected with IO submodule 45 by IO partitioned signal connector 4 12; CPU board module 1 is connected with IO submodule 56 by IO partitioned signal connector 5 13; CPU board module 1 is connected with IO submodule 67 by power connector 1; CPU board module 1 is connected with IO submodule 78 by power connector 2 15.
CPU board module is provided with 4 power connectors: the male 16 of power connector three, the male 17 of power connector four, the male 18 of power connector five, the male 19 of power connector six.
The female of corresponding power connector is set respectively on IO submodule 23, IO submodule 34, IO submodule 45, IO submodule 56, i.e. the female 20,21,22,23 of connector.
The power connector male of CPU board module connects respectively corresponding female on IO submodule by power cable (24～27), realizes CPU board module and powers to corresponding I/O submodule.
Above-mentioned power connector, in the situation that the signal connector (10～13) that IO submodule is connected with CPU board module can not provide enough current capacities, provides extra power supply deliverability.
The topological structure of the electric current of the mainboard in the present embodiment is as shown in Figure 1: IO submodule 67 and IO submodule 78 are two power modules, electric current is provided to CPU board module 1, in CPU board module, pools together.
CPU board module current distributing to the male 16 of power connector three, the male 18 of the male 17 of power connector four, power connector five, the male 19 of power connector six, IO partitioned signal connector 1, IO partitioned signal connector 2 10, IO partitioned signal connector 3 11, IO partitioned signal connector 4 12, IO partitioned signal connector 5 13.
IO submodule 1 obtains electric current by IO partitioned signal connector 1 from CPU board module.IO submodule 23 obtains the electric current of CPU board module by IO connector for substrate 2 10, if IO submodule 23 needs power dissipation ratio larger, by power cable 24, connect the male 16 of power connector three and the female 20 of power connector three again, from CPU board module, obtain electric current.
In like manner, IO submodule 34 obtains electric current from IO connector for substrate 3 11 and power connector four; IO submodule 45 obtains electric current from IO connector for substrate 4 12 and power connector five; IO submodule 56 obtains electric current from IO connector for substrate 5 13 and power connector six.
In the present embodiment, specifically provide device type:
IO submodule six and IO submodule seven can adopt CRPS power supply (Common Redundant Power Supply, redundant power).
It is 10035388-102LF connector that the female (14～15) of power connector one, two can adopt the model of FCI S.A., or connector of equal value, and male is arranged on CRPS power supply.
It is G630HAA22246EU connector that the female of IO partitioned signal connector (9～13) can adopt AMPHENOL company model, or other forms of connector.Male adopts the mode of golden finger, or other forms of connector.
It is HM306-P1H12 connector that the male (16～19) of power connector three, four, five, six can adopt the model of Foxconn company, or other forms of connector.
It is G874D121202CEU connector that the female (20～23) of power connector three, four, five, six can adopt the model of AMPHENOL company, or other forms of connector.
As shown in Figure 2, Fig. 2 is CPU board modular design embodiment schematic diagram, the part that CPU board module comprises changeless part in mainboard or seldom changes, specifically comprise Intel Xeon CPU 201, internal memory 202, Intel PCH 203, BMC204,5 IO partitioned signal connectors (205～209), 6 power connectors (210～215).
The model of Intel Xeon CPU can be Haswell, and quantity can be 1, or a plurality of, and the utility model is set forth with 2 CPU, adopts QPI bus interconnected between CPU.The model of Intel PCH is C610, adopts DMI2 bus and CPU interconnected.
BMC model adopts the AST2400 of Aspeed company, interconnected by usb bus, PCIE x1 bus and Intel PCH.
By BMC chip, draw VGA vision signal, rs 232 serial interface signal, usb signal, network signal (LAN) and positive 5V power supply and be connected to IO submodule one by IO partitioned signal connector one, realize basic IO function, as shown in Figures 2 and 3.
By BMC chip, draw NCSI signal and adopt the mode of bifurcated to be connected to IO submodule two and IO submodule three, be connected with the network controller sideband signals interface on two IO submodules, realize the outband management function of BMC.
If, not with the network controller of NCSI function, NCSI signal is on the shelf on IO submodule.
First CPU of CPU board module draws 2 PCIE3.0 x20 bus, is incorporated into IO submodule two and IO submodule three respectively through IO partitioned signal connector two and IO partitioned signal connector three.
Positive 12V power supply, positive 3.3V power supply, positive 3.3V accessory power supply are to be also incorporated into respectively IO submodule two and IO submodule three by IO partitioned signal connector two and IO partitioned signal connector three.
As shown in Figure 4 to 7, the Four types embodiment schematic diagram of IO submodule two, three.
According to the feature of Intel Haswell CPU, PCIE3.0 x20 bus can be distributed into (combination 1:x16, x4), and (combination 2:x8, x8, x4), (combination 3:x4, x4, x4, x4, x4), as shown in table 1.Accordingly, IO submodule two and IO submodule three at least can be designed to 4 types.
The PCIE allocation scheme of the first IO submodule utilization combination 2 of IO submodule two and IO submodule three, as shown in Figure 4.
PCIE x4 bus connection 100,000,000 or gigabit networking controller be external RJ45 network interface then, realizes ethernet feature.If 100,000,000 or the gigabit networking controller that adopt have NCSI signaling interface, also need to connect the NCSI signal from CPU board module, chip can adopt 82576 gigabit networking chips of Intel Company.
PCIE x8 bus can connect 10,000,000,000 (10G) ether or then IB network chip connects SFP+ interface, realizes express network function, and chip can adopt the X540 of Intel Company, or the MT27504A1 of mellanox company.
Another one PCIE x8bus can connect SAS HBA chip or then RAID chip connects SAS interface, realizes memory function, and chip can adopt 3008 or 3108 chips of Infineon Technologies Corp..
On IO submodule, also have a power connector female 228, by power cable, connect respective electrical source connector male in CPU board module, can provide a power supply is additionally provided outside power supply at IO connector for substrate.
The PCIE allocation scheme of the second IO submodule utilization combination 3 of IO submodule two and IO submodule three, as shown in Figure 5.5 PCIE x4 bus connect the PCIE x4 connector of a standard separately, can insert the PCIE board of standard on market.NCSI function is on the shelf.On IO submodule, also have a power connector female 228, by power cable, connects in CPU board module power connector male accordingly, can provide a power supply is additionally provided outside power supply at IO connector for substrate.
The PCIE allocation scheme of the third IO submodule utilization combination 2 of IO submodule two and IO submodule three, as Fig. 6.1 PCIE x4 bus connects the PCIE x4 connector of a standard, and 2 PCIE x8 bus connect the PCIE x8 connector of a standard separately, can insert the PCIE board of standard on market.NCSI function is on the shelf.On IO submodule, also have a power connector female 228, by power cable, connects in CPU board module power connector male accordingly, can on IO partitioned signal connector provides the basis of power supply, additionally provide a power supply.
The PCIE allocation scheme of the 4th kind of IO submodule utilization combination 1 of IO submodule two and IO submodule three, as Fig. 7.1 PCIE x4 bus connects the PCIE x4 connector of a standard, 1 PCIE x16 bus connects the PCIE x16connector of a standard, can insert the PCIE board of standard on market, can utilize especially PCIE x16 connector to insert GPU card.NCSI function is on the shelf.On IO submodule, also have a power connector female 228, by power cable, connects in CPU board module power connector male accordingly, can on IO partitioned signal connector provides the basis of power supply, additionally provide a power supply.
Second CPU of CPU board module draws 2 PCIE3.0 x20 bus, passes through respectively IO partitioned signal connector four and IO partitioned signal connector five (is incorporated into IO submodule four and IO submodule five.Positive 12V power supply, positive 12V accessory power supply, positive 3.3V power supply are to be also incorporated into respectively IO submodule four and IO submodule five by IO partitioned signal connector four and IO partitioned signal connector five.According to the feature of Intel Haswell CPU, PCIE3.0 x20 bus can distribute (combination 1:x16, x4), and (combination 2:x8, x8, x4), (combination 3:x4, x4, x4, x4, x4), as shown in table 1.Accordingly, IO submodule four and IO submodule five at least can be designed to 3 types.
As shown in Fig. 8～Figure 10, Fig. 8～Figure 10 is the three types embodiment schematic diagram of IO submodule four, five.
The PCIE allocation scheme of the first IO submodule utilization combination 3 of IO submodule four and IO submodule five, as shown in Figure 8.5 PCIE x4 bus connect the PCIE x4 connector of a standard separately, can insert the PCIE board of standard on market.On IO submodule, also have a power connector female 233, by power cable, connects in CPU board module power connector male accordingly, can provide a power supply is additionally provided outside power supply at IO partitioned signal connector.
The PCIE allocation scheme of the second IO submodule utilization combination 2 of IO submodule four and IO submodule five, as Fig. 9.1 PCIE x4 bus connects the PCIE x4 connector of a standard, and 2 PCIE x8 bus connect the PCIE x8 connector of a standard separately, can insert the PCIE board of standard on market.On IO submodule, also have a power connector female 233, by power cable, connects in CPU board module power connector male accordingly, can provide a power supply is additionally provided outside power supply at IO connector for substrate.
The PCIE allocation scheme of the third IO submodule utilization combination 1 of IO submodule four and IO submodule five, as Figure 10.1 PCIE x4 bus connects the PCIE x4 connector of a standard, 1 PCIE x16 bus connects the PCIE x16 connector of a standard separately, can insert the PCIE board of standard on market, can utilize especially PCIE x16 connector can insert GPU card.On IO submodule, also have a power connector female 233, by power cable, connects in CPU board module power connector male accordingly, can provide a power supply is additionally provided outside power supply at IO connector for substrate.
IO submodule one, IO submodule two, IO submodule three, IO submodule four and IO submodule five utilize the signaling interface that IO partitioned signal connector provides to adopt different manufacturers chip, different purposes chip and connector, can composite design become diversified IO plate, can reach hundreds of, be not limited to above introduced several forms.The mainboard module method for designing of utilizing the utility model to set forth, a kind of CPU board module hundreds of IO submodule of can arranging in pairs or groups, can realize the mainboard of hundreds of difference in functionality.
CPU board module is not only limited to Grantley platform yet, is equally applicable to other CPU platforms of Intel yet, the CPU platform of AMD, or other CPU platforms.
Table 1
The distribution array mode different according to PCIE3.0x20, IO submodule two and IO submodule three at least can be designed to Four types, be that type one is the IO submodule of integrated gigabit networking, 10,000,000,000 networks and storage networking, type two is IO submodules of integrated five PCIE4X grooves, type three is IO submodules of integrated 1 PCIE4X groove, 2 PCIE8X grooves, and type four is IO submodules of integrated 1 PCIE4X groove, 1 PCIE16X groove.
IO submodule four and IO submodule five at least can be designed to three types, be that type one is the IO submodule of integrated five PCIE4X grooves, type two is IO submodules of integrated 1 PCIE4X groove, 2 PCIE8X grooves, and type three is IO submodules of integrated 1 PCIE4X groove, 1 PCIE16X groove.
Finally should be noted that: above embodiment is only for illustrating the application's technical scheme but not restriction to its protection domain; although the application is had been described in detail with reference to above-described embodiment; those of ordinary skill in the field are to be understood that: those skilled in the art still can carry out all changes, revise or be equal to replacement to the embodiment of application after reading the application; but these change, revise or be equal to replacement, within the claim protection domain all awaiting the reply in application.
Claims (10)
1. a mainboard for Grantley platform, is characterized in that: described mainboard comprises CPU board module and the IO plate module being connected with power connector by signal connector.
2. mainboard as claimed in claim 1, is characterized in that: described CPU board module comprises cpu circuit, bridge sheet group circuit, main memory circuit, BMC circuit, the signal connector of IO plate module and the power connector of power module.
3. mainboard as claimed in claim 1, is characterized in that: described IO plate module comprises network I/O circuit, storage IO circuit, PCIE groove circuit, keyboard, mouse, VGA and USB circuit.
4. mainboard as claimed in claim 1, is characterized in that: described IO plate module comprises IO submodule and power module;
Described IO submodule is connected with described CPU board module with described power connector by described signal connector respectively;
Described power module is connected with described CPU board module by described power connector.
5. mainboard as claimed in claim 4, is characterized in that: by fixing described CPU board module and the different described IO plate module of variation, be combined into polytype mainboard;
Described CPU board module connects one or two power modules, and appoints IO submodule described in one or more.
6. mainboard as claimed in claim 1, is characterized in that: described signal connector comprises male and female, the connection of the connected sum electric current of the electric signal of two modules that are connected by described male and the realization of described female.
7. mainboard as claimed in claim 1, it is characterized in that: described CPU board module comprises 4 power connectors, when between described CPU board module and described IO submodule, signal connector can not provide enough electric currents, by described power connector, be that described IO submodule is powered.
8. mainboard as claimed in claim 4, is characterized in that: described power module is for adopting the power module of CRPS power supply.
9. mainboard as claimed in claim 1, is characterized in that: the interactive signal of described IO submodule and described CPU board module comprises the VGA vision signal of being drawn by BMC chip, the NCSI signal of being drawn by BMC chip, rs 232 serial interface signal, usb signal, network signal, power supply signal, accessory power supply signal, the PCIE3.0x20 signal of being drawn by CPU.
10. mainboard as claimed in claim 9, is characterized in that: the PCIE3.0 signal of described IO plate module is from the different PCIE passage of same CPU; The NCSI signal of described IO plate module is from the NCSI signal bifurcated of same BMC and two signals that form.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201420331147.4U CN203950254U (en) | 2014-06-20 | 2014-06-20 | A kind of mainboard of Grantley platform |
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| CN201420331147.4U CN203950254U (en) | 2014-06-20 | 2014-06-20 | A kind of mainboard of Grantley platform |
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Granted publication date: 20141119 |