CN203933155U - For the intelligent controller of omnipotent breaker - Google Patents
For the intelligent controller of omnipotent breaker Download PDFInfo
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- CN203933155U CN203933155U CN201420222419.7U CN201420222419U CN203933155U CN 203933155 U CN203933155 U CN 203933155U CN 201420222419 U CN201420222419 U CN 201420222419U CN 203933155 U CN203933155 U CN 203933155U
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Abstract
The utility model relates to a kind of intelligent controller for omnipotent breaker, it comprises control processor and connects for the power circuit that control processor operating voltage is provided, described control processor also connects with the USB communicating circuit for being connected with upper machine communication, the input of control processor and ground protection treatment circuit, four phase current treatment circuits connect, the output of control processor and trip circuit, signalling contact output circuit and display circuit connect, control processor is according to the driving of threading off of the ground protection current value control trip circuit of the working current value of four phase current treatment circuits inputs or the input of ground protection treatment circuit, and carry out state instruction by signalling contact output circuit.The utility model compact conformation, convenient with upper machine communication, detect easy to maintenancely, intelligent degree is high, and wide accommodation is safe and reliable.
Description
Technical field
The utility model relates to a kind of intelligent controller, and especially a kind of intelligent controller for omnipotent breaker belongs to the technical field of intelligent controller.
Background technology
The intelligentized development of electrical network also further improves the intelligentized requirement of distribution system, and traditional low-voltage circuit breaker product can not meet new application demand, and the low-voltage circuit breaker that a new generation has intellectuality, can communicate by letter becomes inevitable choice.Intelligent controller as the core control part of low-voltage circuit breaker has adopted microprocessor technology; replace Thermomagnetic type and electronic protecting device in the past by digitlization monitoring and protection mode, not only realized the digitlization of protection action but also can realize the function such as remote regulating, the remote measurement of electric power system real-time current, the distant news of alarm failure information, Remote circuit-breaker switching on-off of Protection parameters., distribution system defeated to low pressure provides the foundation to intelligent, networking future development.
Substantially all RS485 interfaces based on MODBUS-RTU communications protocol only of the communication interface of existing product, the interface of computer standard configuration is RS232 interface, product is do while detecting in factory can not be directly and dataphone like this, need to increase the modular converter of a RS232-RS485, therefore bring certain trouble to practical application.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, and a kind of intelligent controller for omnipotent breaker is provided, and its compact conformation is convenient with upper machine communication, detects easy to maintenancely, and intelligent degree is high, and wide accommodation is safe and reliable.
The technical scheme providing according to the utility model, the described intelligent controller for omnipotent breaker, comprise control processor and for the power circuit of control processor operating voltage is provided, described control processor also connects with the USB communicating circuit for being connected with upper machine communication, the input of control processor and ground protection treatment circuit, four phase current treatment circuits connect, the output of control processor and trip circuit, signalling contact output circuit and display circuit connect, control processor is according to the driving of threading off of the ground protection current value control trip circuit of the working current value of four phase current treatment circuits inputs or the input of ground protection treatment circuit, and carry out state instruction by signalling contact output circuit.
Described control processor is also connected with keyboard and indicator light circuit, memory and RS485 communicating circuit.Described control processor is connected with display circuit by display driver circuit; Described display circuit comprises display screen.
Described power circuit comprises diode D1, the cathode terminal of described diode D1 is connected with the cathode terminal of diode D2, the cathode terminal of diode D3, the cathode terminal of diode D4, cathode terminal, the cathode terminal of diode D11 and the drain electrode end of metal-oxide-semiconductor T1 of diode D5, the anode tap of diode D1 is connected with the cathode terminal of diode D6, the anode tap ground connection of diode D6, the anode tap of diode D2 is connected with the cathode terminal of diode D7, the anode tap ground connection of diode D7, the anode tap of diode D3 is connected with the cathode terminal of diode D8, the anode tap ground connection of diode D8, the anode tap of diode D4 is connected with the cathode terminal of diode D9, the anode tap ground connection of diode D9, the anode tap of diode D5 is connected with the cathode terminal of diode D10, the anode tap ground connection of diode D10, one end of the anode tap of diode D11 and resistance R 1, the anode tap of voltage stabilizing didoe D12, the source terminal of metal-oxide-semiconductor T1 connects, and the anode tap ground connection of diode D11,
One end of the other end of resistance R 1 and resistance R 2, the gate terminal of the cathode terminal of voltage stabilizing didoe D12 and metal-oxide-semiconductor T1 connects, the drain electrode end of metal-oxide-semiconductor T1 is connected with one end of resistance R 3, the gate terminal of the other end of resistance R 3 and metal-oxide-semiconductor T2, the cathode terminal of voltage stabilizing didoe D13 connects, the anode tap of voltage stabilizing didoe D13 is connected with the source terminal of metal-oxide-semiconductor T2 and the anode tap of diode D14, the anode tap of the cathode terminal of diode D14 and diode D16, the cathode terminal of diode D15, one end of one end of capacitor C 1 and capacitor C 2 connects, the anode tap ground connection of diode D15, the other end ground connection of the other end of capacitor C 1 and capacitor C 2, one end of the cathode terminal of diode D16 and capacitor C 3, the VIN end of one end of capacitor C 4 and chip U1 connects, the equal ground connection of the other end of the other end of capacitor C 3 and capacitor C 4, the SS/TR end of chip U1 is by capacitor C 5 ground connection, the TR/LCK end of chip U1 is by resistance R 4 ground connection, the GND end ground connection of chip U1, the BOOT end of chip U1 is connected with the PH end of chip U1 by capacitor C 8, the PH end of chip U1 is connected with the cathode terminal of diode D17 and one end of inductance L 1, the anode tap ground connection of diode D17, the other end of inductance L 1 is connected with one end of capacitor C 9 and one end of capacitor C 10, the other end ground connection of the other end of capacitor C 9 and capacitor C 10, the COMP end of chip U1 is connected with one end of resistance R 7 and one end of capacitor C 7, the other end of resistance R 7 is by capacitor C 6 ground connection, the other end ground connection of capacitor C 7, the VSENSE end of chip U1 is connected with one end of resistance R 5 and one end of resistance R 6, one end ground connection of resistance R 6, the other end of resistance R 5 is connected with the other end of inductance L 1.
Described memory comprises chip U2, and it is CAT1161WI-42-GT3 chip that described chip U2 adopts model; Provide with power circuit+5V voltage of the VCC end of chip U2 is connected, the WP end of chip U2 is connected with one end of resistance R 9, provide+5V voltage of one end of the other end of resistance R 9 and resistance R 10, one end of resistance R 11 and power circuit is connected, the other end of resistance R 10 is connected with the SDA end of chip U2, the other end of resistance R 11 is connected with the SCL end of chip U2, chip U2 /RESET end is connected with one end of resistance R 8 and one end of capacitor C 11, provide with power circuit+5V of the other end of resistance R 8 voltage is connected, the other end ground connection of capacitor C 11.
Described USB communicating circuit comprises chip U3 and interface J1, described chip U3 adopts the chip that model is XR21V1410, the LOWPOWER end of described chip U3 is connected with 3.3V voltage by resistance R 79, the VCC end of chip U3 is connected with 3.3V voltage, the USBD+ end of chip U3, the USBD-end of chip U3 and the D+ end of interface J1, D-end is corresponding to be connected, and the USBD+ of chip U3 end, the USBD-end of chip U3 is by electrostatic protection diode D31 ground connection, the G end of interface J1 is connected with one end of capacitor C 56 and one end of inductance L 10, the other end of capacitor C 56 is connected with the 5V end of interface J1 and one end of inductance L 11, provide+5V voltage of one end of the other end of inductance L 11 and capacitor C 57 and power circuit is connected, the other end of capacitor C 57 is connected with the other end of inductance L 10, and the other end ground connection of capacitor C 57, the RX end of chip U3 is connected with the collector terminal of triode Q1, the collector terminal of triode Q1 is also connected with one end of resistance R 77, the other end of resistance R 77 is connected with 3.3V voltage, one end of the base terminal of triode Q1 and resistance R 76, one end of one end of resistance R 78 and capacitor C 55 connects, the other end ground connection of the other end of capacitor C 55 and resistance R 78, provide with power circuit+5V of the other end of resistance R 76 voltage is connected.
Described four phase current treatment circuits comprise resistance R 12, one end of described resistance R 12 is connected with 2.5V voltage, the other end of resistance R 12 is connected with one end of capacitor C 12 and one end of resistance R 13, one end of the other end of resistance R 13 and capacitor C 13, one end of resistance R 14, the end of oppisite phase of one end of resistance R 15 and operational amplifier U1A connects, the other end of the other end of resistance R 15 and capacitor C 14, one end of the output of operational amplifier U1A and inductance L 2 connects, the other end of inductance L 2 is by capacitor C 16 ground connection, the output of operational amplifier U1A is connected with one end of resistance R 18, one end of the other end of resistance R 18 and capacitor C 17, the end of oppisite phase of one end of resistance R 20 and operational amplifier U1B connects, the other end of resistance R 20 is connected with the output of operational amplifier U1B and one end of inductance L 3, the other end of inductance L 3 is by capacitor C 18 ground connection, the other end of capacitor C 12 is connected with one end of resistance R 17 and the other end of resistance R 14, the other end of resistance R 14 is connected with the other end of capacitor C 13, one end, one end of capacitor C 15 and the in-phase end of operational amplifier U1A of resistance R 16, the other end of capacitor C 17 is connected with the in-phase end of operational amplifier U1B and one end of resistance R 19, and the other end of resistance R 19 is connected with the other end of capacitor C 15, the other end of resistance R 16, the other end of resistance R 17, one end and the 2.5V voltage of resistance R 21,
The other end of resistance R 21 is connected with one end of capacitor C 19 and one end of resistance R 22, one end of the other end of resistance R 22 and capacitor C 20, one end of resistance R 23, the end of oppisite phase of one end of capacitor C 21 and operational amplifier U1C connects, the other end of the other end of resistance R 23 and capacitor C 21, the output of operational amplifier U1C, one end of one end of resistance R 25 and inductance L 4 connects, the other end of inductance L 4 is by capacitor C 22 ground connection, one end of the other end of resistance R 25 and capacitor C 24, the end of oppisite phase of one end of resistance R 24 and operational amplifier U1D connects, the other end of resistance R 24 is connected with the output of operational amplifier U1D and one end of inductance L 5, the other end of inductance L 5 is by capacitor C 26 ground connection, the negative power end ground connection of operational amplifier U1D, the positive power source terminal of operational amplifier U1D is connected with one end of+5V voltage and capacitor C 25, the other end ground connection of capacitor C 25, the other end of capacitor C 19 is connected with one end of resistance R 27 and one end of resistance R 28, the other end of the other end of resistance R 27 and capacitor C 20, one end of resistance R 29, the in-phase end of one end of capacitor C 23 and operational amplifier U1C connects, the other end of capacitor C 24 is connected with the in-phase end of operational amplifier U1D and the other end of resistance R 26, the other end of the other end of resistance R 26 and capacitor C 23, the other end of resistance R 29, the other end of resistance R 28, one end of resistance R 30 and 2.5V voltage connect,
The other end of resistance R 30 is connected with one end of capacitor C 27 and one end of resistance R 31, one end of the other end of resistance R 31 and capacitor C 28, one end of capacitor C 29, the end of oppisite phase of one end of resistance R 32 and operational amplifier U2A connects, the other end of the other end of resistance R 32 and capacitor C 29, the output of operational amplifier U2A, one end of one end of resistance R 33 and inductance L 6 connects, the other end of inductance L 6 is by capacitor C 31 ground connection, one end of the other end of resistance R 33 and capacitor C 32, the end of oppisite phase of one end of resistance R 34 and operational amplifier U2B connects, the other end of resistance R 34 is connected with the output of operational amplifier U2B and one end of inductance L 7, the other end of inductance L 7 is by capacitor C 33 ground connection, the other end of capacitor C 27 is connected with one end of resistance R 36 and one end of resistance R 37, the other end of the other end of resistance R 36 and capacitor C 28, one end of resistance R 38, the in-phase end of one end of capacitor C 30 and operational amplifier U2A connects, the other end of capacitor C 32 is connected with the in-phase end of operational amplifier U2B and one end of resistance R 35, the other end of the other end of resistance R 35 and capacitor C 30, the other end of resistance R 38, the other end of resistance R 37, one end of resistance R 39 and 2.5V voltage connect,
The other end of resistance R 39 is connected with one end of capacitor C 36 and one end of resistance R 40, one end of the other end of resistance R 40 and capacitor C 37, one end of capacitor C 34, the end of oppisite phase of one end of resistance R 41 and operational amplifier U2C connects, the other end of the other end of resistance R 41 and capacitor C 34, the output of operational amplifier U2C with, one end of one end of inductance L 8 and resistance R 46 connects, the other end of inductance L 8 is by capacitor C 35 ground connection, one end of the other end of resistance R 46 and capacitor C 39, the end of oppisite phase of one end of resistance R 42 and operational amplifier U2D connects, the other end of resistance R 42 is connected with one end of inductance L 9, the other end of inductance L 9 is by capacitor C 41 ground connection, the negative power end ground connection of operational amplifier U2D, one end of the positive power source terminal of operational amplifier U2D and capacitor C 40 and+5V voltage is connected, the other end ground connection of capacitor C 40, the other end of capacitor C 36 is connected with one end of resistance R 43 and one end of resistance R 44, the other end of resistance R 43 is connected with the other end of capacitor C 37, one end, one end of capacitor C 38 and the in-phase end of operational amplifier U2C of resistance R 45, the other end of capacitor C 39 is connected with the in-phase end of operational amplifier U2D and one end of resistance R 47, and the other end of resistance R 47 is connected with the other end of capacitor C 38, the other end of resistance R 45, the other end and the 2.5V voltage of resistance R 44.
Described ground protection circuit comprises operational amplifier U4A and operational amplifier U4B, one end of the in-phase end of described operational amplifier U4A and resistance R 63, one end of resistance R 64, one end of resistance R 65, one end of resistance R 66, one end of resistance R 71, one end of one end of capacitor C 50 and capacitor C 51 connects, and the other end of the other end of resistance R 71 and capacitor C 51 is all connected with 2.5V voltage, the other end of the end of oppisite phase of operational amplifier U4A and capacitor C 50, one end of resistance R 67, one end of resistance R 68, one end of resistance R 69, one end of resistance R 70, one end of one end of resistance R 72 and capacitor C 52 connects, the other end of the other end of resistance R 72 and capacitor C 52, the output of operational amplifier U4A, one end of one end of capacitor C 53 and resistance R 73 connects, the other end ground connection of capacitor C 53, the other end of resistance R 73 is connected with the end of oppisite phase of operational amplifier U4B and one end of resistance R 75, the other end of resistance R 75 is connected with the output of operational amplifier U4B and one end of capacitor C 54, the other end ground connection of capacitor C 54, the in-phase end of operational amplifier U4B is connected with 2.5V voltage by resistance R 74.
Described trip circuit comprises resistance R 48, one end of described resistance R 48 is connected with the cathode terminal of voltage stabilizing didoe D18 and the gate terminal of metal-oxide-semiconductor T3, the other end of resistance R 48 is connected with the anode tap of voltage stabilizing didoe D18 and the source terminal of metal-oxide-semiconductor T3, and the anode tap ground connection of voltage stabilizing didoe D18, the anode tap of the drain electrode end of metal-oxide-semiconductor T3 and voltage stabilizing didoe D19, one end of capacitor C 42, the in-phase end of one end of resistance R 49 and operational amplifier U3A connects, the cathode terminal of the cathode terminal of voltage stabilizing didoe D19 and diode D20, the cathode terminal of diode D21 connects, the anode tap of the anode tap of diode D20 and diode D21 all with one end of resistance R 53, one end of the output of operational amplifier U3A and capacitor C 43 connects, the positive power source terminal of operational amplifier U3A is connected with one end of 24V voltage and capacitor C 43, the other end ground connection of capacitor C 43, the negative power end ground connection of operational amplifier U3A, one end of the other end of resistance R 53 and resistance R 52, one end of resistance R 55, one end of resistance R 56, one end of resistance R 57, one end of one end capacitor C 47 of resistance R 58 and the cathode terminal of diode D28 connect, the end of oppisite phase of the other end of resistance R 52 and operational amplifier U3A, one end of resistance R 51, the end of oppisite phase of the end of oppisite phase of operational amplifier U3B and operational amplifier U3D connects,
The other end ground connection of capacitor C 42, the other end ground connection of resistance R 51, the other end of resistance R 49 is connected with one end, the cathode terminal of diode D22 and the cathode terminal of diode D23 of resistance R 50, the anode tap of diode D22 is by capacitor C 28 ground connection, the anode tap of diode D23 is by capacitor C 49 ground connection, the other end ground connection of resistance R 50; The other end of capacitor C 43 is connected with the in-phase end of operational amplifier U3B, one end, the cathode terminal of diode D24 and the cathode terminal of diode D25 of resistance R 54, the equal ground connection of anode tap of the other end of resistance R 54, the anode tap of diode D24 and diode D25;
The output of the other end of resistance R 55 and operational amplifier U3B, one end of resistance R 61, the anode tap of the anode tap of diode D26 and diode D27 connects, the other end of resistance R 61 is connected with one end of resistance R 80 and one end of capacitor C 43, the equal ground connection of the other end of the other end of resistance R 80 and capacitor C 43, the end of oppisite phase of the cathode terminal of diode D27 and operational amplifier U3C, one end of one end of resistance R 81 and capacitor C 44 connects, the equal ground connection of the other end of the other end of capacitor C 44 and resistance R 81, the in-phase end of the cathode terminal of diode D26 and operational amplifier U3D, one end of one end of resistance R 83 and capacitor C 46 connects, the equal ground connection of the other end of the other end of resistance R 83 and capacitor C 46,
The other end of resistance R 56 is connected with the in-phase end of operational amplifier U3C and one end of resistance R 60, the other end ground connection of resistance R 60, the output of operational amplifier U3C is connected with the other end of resistance R 57 and one end of capacitor C 45, the other end of capacitor C 45 is connected with the gate terminal of metal-oxide-semiconductor T3, the other end of the output of operational amplifier U3D and resistance R 58 with, one end of resistance R 62, the gate terminal of one end of capacitor C 58 and metal-oxide-semiconductor T4 connects, the equal ground connection of the other end of the other end of resistance R 62 and capacitor C 58, the other end ground connection of capacitor C 47, the source terminal ground connection of metal-oxide-semiconductor T4, the drain electrode end of metal-oxide-semiconductor T4 is connected with the anode tap of diode D30, the cathode terminal of diode D30 is connected with the cathode terminal of diode D29, the anode tap of diode D29 is connected with the anode tap of diode D28, and the anode tap of diode D29 is connected with 24V voltage.
Advantage of the present utility model: the voltage that control processor work is provided by power circuit, obtain earth current value by ground protection treatment circuit, four phase current values while obtaining three phase mains work by four phase current treatment circuits, control processor can drive circuit breaker tripping according to earth current value or working current value by trip circuit, control processor is by USB communicating circuit, RS485 communicating circuit is realized the communication with host computer, can carry out signal and State-output by signalling contact output circuit and display circuit, compact conformation, intelligent degree is high, wide accommodation, safe and reliable.
Brief description of the drawings
Fig. 1 is structured flowchart of the present utility model.
Fig. 2 is the circuit theory diagrams of the utility model power circuit.
Fig. 3 is the circuit theory diagrams of the utility model memory.
Fig. 4 is the circuit theory diagrams of the utility model four phase current treatment circuits.
Fig. 5 is the circuit theory diagrams of the utility model trip circuit.
Fig. 6 is the circuit theory diagrams of the utility model ground protection treatment circuit.
Fig. 7 is the circuit theory diagrams of the signal conversion in the utility model USB communicating circuit.
Fig. 8 is the circuit theory diagrams that in the utility model USB communicating circuit, USB chip is connected with interface.
Description of reference numerals: 1-control processor, 2-RS485 communicating circuit, 3-USB communicating circuit, 4-memory, 5-trip circuit, 6-signalling contact output circuit, 7-display driver circuit, 8-display circuit, 9-keyboard and indicator light circuit, 10-power circuit, 11-ground protection treatment circuit, 12-ground protection sample circuit, 13-tetra-phase current treatment circuits and 14-tetra-phase current sampling circuits.
Embodiment
Below in conjunction with concrete drawings and Examples, the utility model is described in further detail.
As shown in Figure 1: for convenient with upper machine communication, detect easy to maintenance, improve intelligent degree, guarantee the reliability that circuit breaker uses, the utility model comprises control processor 1 and connects for the power circuit 10 that control processor 1 operating voltage is provided, described control processor 1 also connects with the USB communicating circuit 3 for being connected with upper machine communication, the input of control processor 1 and ground protection treatment circuit 11, four phase current treatment circuits 13 connect, the output of control processor 1 and trip circuit 5, signalling contact output circuit 6 and display circuit 8 connect, the ground protection current value control trip circuit 5 that the working current value that control processor 1 is inputted according to four phase current treatment circuits 13 or ground protection treatment circuit 11 the are inputted driving of threading off, and carry out state instruction by signalling contact output circuit 6.
Particularly; control processor 1 can adopt existing micro-chip processor; power circuit 10 can provide control processor 1 and the required operating voltage of other circuit; control processor 1 is by USB(Universal Serial Bus) communicating circuit 3 can easily and realize USB communication between host computer; when host computer is undertaken after USB communication by USB communicating circuit 3 and control processor 1; can control processor 1 be checked easily and be keeped in repair; realize the setting of working state of circuit breaker, running parameter and Protection parameters etc. and check, easy to operate.In the utility model embodiment; ground protection treatment circuit 11 is connected with ground protection sample circuit 12; can cross ground protection sample circuit 12 and obtain the current value of three phase mains in the time of ground connection; ground protection treatment circuit 11 transfers in control processor 1 after the three phase mains earth current value of obtaining being processed, and operates so that control processor 1 is identified and carried out required protection.
Four phase current treatment circuits 13 are connected with four phase current sampling circuits 14, obtain the current value of three phase mains in the time working by four phase current sampling circuits 14, and after being processed, corresponding current value transfers in control processor 1, control processor 1 is interior can set in advance an operating current threshold value, the current value transmitting when four phase current sampling circuits 14 is greater than operating current threshold value, or the current value of transmission is while mating with the warning drop-away current value setting in advance in control processor 1, control processor 5 can drive circuit breaker to thread off by trip circuit 5, to disconnect the electricity consumption loop of three phase mains.Above-mentioned four phase currents are respectively A phase, B phase, C phase and the N phase of three phase mains, and in the specific implementation, power supply that also can three-phase three-wire system, is only A phase, B phase and C phase.Ground protection sample circuit 12 and four phase current sampling circuits 14 all can adopt current transformer.Control processor 1 by signalling contact output circuit 6 the work loop of three phase mains break down or normal condition under the instruction of being correlated with, can realize the straighforward operation of remote status instruction and remote status.Signalling contact output circuit 6 can adopt the realizations such as the contact of a series of auxiliary relay, and its concrete structure can adopt existing structure, and the structure of signalling contact output circuit 6 neither emphasis of the present utility model, repeats no more herein.
Further, described control processor 1 is also connected with keyboard and indicator light circuit 9, memory 4 and RS485 communicating circuit 2.Can be to the relevant Protection parameters of the interior input of control processor 1 by the keyboard in keyboard and indicator light circuit 9, the instruction by the indicator light in keyboard and indicator light circuit 9 for correlation behavior, as operating state or malfunction.Control processor 1 can be realized the communication between host computer by RS485 communicating circuit 2, increases the conversion between 485 signals and 232 signals, improves the versatility of whole intelligent controller.RS485 communicating circuit 2 can adopt existing circuit structure, repeats no more herein.
Described control processor 1 is connected with display circuit 8 by display driver circuit 7; Described display circuit 8 comprises display screen.In the utility model embodiment; control processor 1 can show output to the operating state of circuit breaker and Protection parameters by display circuit 8; in the time that display circuit 8 adopts display screen or other display equipment; drive rear output by display driver circuit 7, display driver circuit 7 can adopt existing drive form.After display circuit 8 outputs, be convenient to checking of operating state and the Protection parameters etc. of staff to circuit breaker.
As shown in Figure 2, described power circuit 10 comprises diode D1, the cathode terminal of described diode D1 is connected with the cathode terminal of diode D2, the cathode terminal of diode D3, the cathode terminal of diode D4, cathode terminal, the cathode terminal of diode D11 and the drain electrode end of metal-oxide-semiconductor T1 of diode D5, the anode tap of diode D1 is connected with the cathode terminal of diode D6, the anode tap ground connection of diode D6, the anode tap of diode D2 is connected with the cathode terminal of diode D7, the anode tap ground connection of diode D7, the anode tap of diode D3 is connected with the cathode terminal of diode D8, the anode tap ground connection of diode D8, the anode tap of diode D4 is connected with the cathode terminal of diode D9, the anode tap ground connection of diode D9, the anode tap of diode D5 is connected with the cathode terminal of diode D10, the anode tap ground connection of diode D10, one end of the anode tap of diode D11 and resistance R 1, the anode tap of voltage stabilizing didoe D12, the source terminal of metal-oxide-semiconductor T1 connects, and the anode tap ground connection of diode D11,
One end of the other end of resistance R 1 and resistance R 2, the gate terminal of the cathode terminal of voltage stabilizing didoe D12 and metal-oxide-semiconductor T1 connects, the drain electrode end of metal-oxide-semiconductor T1 is connected with one end of resistance R 3, the gate terminal of the other end of resistance R 3 and metal-oxide-semiconductor T2, the cathode terminal of voltage stabilizing didoe D13 connects, the anode tap of voltage stabilizing didoe D13 is connected with the source terminal of metal-oxide-semiconductor T2 and the anode tap of diode D14, the anode tap of the cathode terminal of diode D14 and diode D16, the cathode terminal of diode D15, one end of one end of capacitor C 1 and capacitor C 2 connects, the anode tap ground connection of diode D15, the other end ground connection of the other end of capacitor C 1 and capacitor C 2, one end of the cathode terminal of diode D16 and capacitor C 3, the VIN end of one end of capacitor C 4 and chip U1 connects, the equal ground connection of the other end of the other end of capacitor C 3 and capacitor C 4, the SS/TR end of chip U1 is by capacitor C 5 ground connection, the TR/LCK end of chip U1 is by resistance R 4 ground connection, the GND end ground connection of chip U1, the BOOT end of chip U1 is connected with the PH end of chip U1 by capacitor C 8, the PH end of chip U1 is connected with the cathode terminal of diode D17 and one end of inductance L 1, the anode tap ground connection of diode D17, the other end of inductance L 1 is connected with one end of capacitor C 9 and one end of capacitor C 10, the other end ground connection of the other end of capacitor C 9 and capacitor C 10, the COMP end of chip U1 is connected with one end of resistance R 7 and one end of capacitor C 7, the other end of resistance R 7 is by capacitor C 6 ground connection, the other end ground connection of capacitor C 7, the VSENSE end of chip U1 is connected with one end of resistance R 5 and one end of resistance R 6, one end ground connection of resistance R 6, the other end of resistance R 5 is connected with the other end of inductance L 1.
In the utility model embodiment, the cathode terminal of the anode tap of diode D1 and diode D6 is connected with Pn terminal, the cathode terminal of the anode tap of diode D2 and diode D7 is connected with Pd terminal, the cathode terminal of the anode tap of diode D3 and diode D8 is connected with Pa terminal, the cathode terminal of the anode tap of diode D4 and diode D9 is connected with Pb terminal, the cathode terminal of the anode tap of diode D5 and diode D10 is connected with Pc terminal, can realize and being connected of power transformer by Pn terminal, Pa terminal, Pb terminal, Pc terminal and Pd terminal.The other end of resistance R 2 is connected with control processor 1, chip U1 adopts the chip that model is TPS5401DGQ, one end that inductance L 1 is connected with capacitor C 9 and capacitor C 10 forms the output of whole power circuit 10, can provide controller required 5V voltage, in the utility model embodiment, the follow-up 5V voltage of mentioning provides by described power circuit 10, and 2.5V voltage can have 5V voltage dividing potential drop to obtain.In order to test, form Vin voltage tester contact at the cathode terminal of diode D16, form PVCC voltage test points at the cathode terminal of diode D14.
As shown in Figure 3, in the utility model embodiment, memory 4 adopts E
2prom memory, described memory comprises chip U2, it is CAT1161WI-42-GT3 chip that described chip U2 adopts model; Provide with power circuit 10+5V voltage of the VCC end of chip U2 is connected, the WP end of chip U2 is connected with one end of resistance R 9, provide+5V voltage of one end of the other end of resistance R 9 and resistance R 10, one end of resistance R 11 and power circuit 10 is connected, the other end of resistance R 10 is connected with the SDA end of chip U2, the other end of resistance R 11 is connected with the SCL end of chip U2, chip U2 /RESET end is connected with one end of resistance R 8 and one end of capacitor C 11, the other end of resistance R 8 is connected with provide+5V of power circuit 10 voltage, the other end ground connection of capacitor C 11.
Wherein, the SCL end of chip U2, SDA end, DC end ,/RESET end and WP end are all connected with the corresponding pin of control processor 1, to realize the storage content in control processor 1 read memory 4, and to the required content of the interior storage of memory 4.
As shown in Figure 7 and Figure 8, described USB communicating circuit 3 comprises chip U3 and interface J1, described chip U3 adopts the chip that signal is XR21V1410, the LOWPOWER end of described chip U3 is connected with 3.3V voltage by resistance R 79, the VCC end of chip U3 is connected with 3.3V voltage, the USBD+ end of chip U3, the USBD-end of chip U3 and the D+ end of interface J1, D-end is corresponding to be connected, and the USBD+ of chip U3 end, the USBD-end of chip U3 is by electrostatic protection diode D31 ground connection, the G end of interface J1 is connected with one end of capacitor C 56 and one end of inductance L 10, the other end of capacitor C 56 is connected with the 5V end of interface J1 and one end of inductance L 11, provide+5V voltage of one end of the other end of inductance L 11 and capacitor C 57 and power circuit 10 is connected, the other end of capacitor C 57 is connected with the other end of inductance L 10, and the other end ground connection of capacitor C 57, the RX end of chip U3 is connected with the collector terminal of triode Q1, the collector terminal of triode Q1 is also connected with one end of resistance R 77, the other end of resistance R 77 is connected with 3.3V voltage, one end of the base terminal of triode Q1 and resistance R 76, one end of one end of resistance R 78 and capacitor C 55 connects, the other end ground connection of the other end of capacitor C 55 and resistance R 78, the other end of resistance R 76 is connected with provide+5V of power circuit 10 voltage.
In the utility model embodiment, 3.3 required voltages of chip U3 can have that power circuit 10 exports+and 5V voltage transitions obtains, and power supply conversion portion can adopt existing circuit form, repeats no more herein.The emitter terminal of triode Q1 connects for the pin corresponding with control processor 1.Interface J1 is for being connected with the USB interface of host computer, the corresponding connection of pin of chip U3 and control processor 1, and the USB communication then realizing between control processor 1 and host computer is connected.
As shown in Figure 4, described four phase current treatment circuits 13 comprise resistance R 12, one end of described resistance R 12 is connected with 2.5V voltage, the other end of resistance R 12 is connected with one end of capacitor C 12 and one end of resistance R 13, one end of the other end of resistance R 13 and capacitor C 13, one end of resistance R 14, the end of oppisite phase of one end of resistance R 15 and operational amplifier U1A connects, the other end of the other end of resistance R 15 and capacitor C 14, one end of the output of operational amplifier U1A and inductance L 2 connects, the other end of inductance L 2 is by capacitor C 16 ground connection, the output of operational amplifier U1A is connected with one end of resistance R 18, one end of the other end of resistance R 18 and capacitor C 17, the end of oppisite phase of one end of resistance R 20 and operational amplifier U1B connects, the other end of resistance R 20 is connected with the output of operational amplifier U1B and one end of inductance L 3, the other end of inductance L 3 is by capacitor C 18 ground connection, the other end of capacitor C 12 is connected with one end of resistance R 17 and the other end of resistance R 14, the other end of resistance R 14 is connected with the other end of capacitor C 13, one end, one end of capacitor C 15 and the in-phase end of operational amplifier U1A of resistance R 16, the other end of capacitor C 17 is connected with the in-phase end of operational amplifier U1B and one end of resistance R 19, and the other end of resistance R 19 is connected with the other end of capacitor C 15, the other end of resistance R 16, the other end of resistance R 17, one end and the 2.5V voltage of resistance R 21,
The other end of resistance R 21 is connected with one end of capacitor C 19 and one end of resistance R 22, one end of the other end of resistance R 22 and capacitor C 20, one end of resistance R 23, the end of oppisite phase of one end of capacitor C 21 and operational amplifier U1C connects, the other end of the other end of resistance R 23 and capacitor C 21, the output of operational amplifier U1C, one end of one end of resistance R 25 and inductance L 4 connects, the other end of inductance L 4 is by capacitor C 22 ground connection, one end of the other end of resistance R 25 and capacitor C 24, the end of oppisite phase of one end of resistance R 24 and operational amplifier U1D connects, the other end of resistance R 24 is connected with the output of operational amplifier U1D and one end of inductance L 5, the other end of inductance L 5 is by capacitor C 26 ground connection, the negative power end ground connection of operational amplifier U1D, the positive power source terminal of operational amplifier U1D is connected with one end of+5V voltage and capacitor C 25, the other end ground connection of capacitor C 25, the other end of capacitor C 19 is connected with one end of resistance R 27 and one end of resistance R 28, the other end of the other end of resistance R 27 and capacitor C 20, one end of resistance R 29, the in-phase end of one end of capacitor C 23 and operational amplifier U1C connects, the other end of capacitor C 24 is connected with the in-phase end of operational amplifier U1D and the other end of resistance R 26, the other end of the other end of resistance R 26 and capacitor C 23, the other end of resistance R 29, the other end of resistance R 28, one end of resistance R 30 and 2.5V voltage connect,
The other end of resistance R 30 is connected with one end of capacitor C 27 and one end of resistance R 31, one end of the other end of resistance R 31 and capacitor C 28, one end of capacitor C 29, the end of oppisite phase of one end of resistance R 32 and operational amplifier U2A connects, the other end of the other end of resistance R 32 and capacitor C 29, the output of operational amplifier U2A, one end of one end of resistance R 33 and inductance L 6 connects, the other end of inductance L 6 is by capacitor C 31 ground connection, one end of the other end of resistance R 33 and capacitor C 32, the end of oppisite phase of one end of resistance R 34 and operational amplifier U2B connects, the other end of resistance R 34 is connected with the output of operational amplifier U2B and one end of inductance L 7, the other end of inductance L 7 is by capacitor C 33 ground connection, the other end of capacitor C 27 is connected with one end of resistance R 36 and one end of resistance R 37, the other end of the other end of resistance R 36 and capacitor C 28, one end of resistance R 38, the in-phase end of one end of capacitor C 30 and operational amplifier U2A connects, the other end of capacitor C 32 is connected with the in-phase end of operational amplifier U2B and one end of resistance R 35, the other end of the other end of resistance R 35 and capacitor C 30, the other end of resistance R 38, the other end of resistance R 37, one end of resistance R 39 and 2.5V voltage connect,
The other end of resistance R 39 is connected with one end of capacitor C 36 and one end of resistance R 40, one end of the other end of resistance R 40 and capacitor C 37, one end of capacitor C 34, the end of oppisite phase of one end of resistance R 41 and operational amplifier U2C connects, the other end of the other end of resistance R 41 and capacitor C 34, the output of operational amplifier U2C with, one end of one end of inductance L 8 and resistance R 46 connects, the other end of inductance L 8 is by capacitor C 35 ground connection, one end of the other end of resistance R 46 and capacitor C 39, the end of oppisite phase of one end of resistance R 42 and operational amplifier U2D connects, the other end of resistance R 42 is connected with one end of inductance L 9, the other end of inductance L 9 is by capacitor C 41 ground connection, the negative power end ground connection of operational amplifier U2D, one end of the positive power source terminal of operational amplifier U2D and capacitor C 40 and+5V voltage is connected, the other end ground connection of capacitor C 40, the other end of capacitor C 36 is connected with one end of resistance R 43 and one end of resistance R 44, the other end of resistance R 43 is connected with the other end of capacitor C 37, one end, one end of capacitor C 38 and the in-phase end of operational amplifier U2C of resistance R 45, the other end of capacitor C 39 is connected with the in-phase end of operational amplifier U2D and one end of resistance R 47, and the other end of resistance R 47 is connected with the other end of capacitor C 38, the other end of resistance R 45, the other end and the 2.5V voltage of resistance R 44.
The other end of resistance R 12 is connected with L3-end, the other end of capacitor C 12 is connected with L3+ end, one end of capacitor C 19 is connected with L1-end, the other end of capacitor C 19 is connected with L1-end, one end of capacitor C 27 is connected with L2-end, the other end of capacitor C 27 is connected with L2+ end, and one end of capacitor C 36 is connected with L4-end, and the other end of capacitor C 36 is connected with L4+ end.In the specific implementation, L1-end, L1+ end, L2-end, L2+ end, L3-end, L3+ end, L4-end and L4+ end are for being connected with four phase current sampling circuits 14, the two ends that are respectively current transformer connect, L1-end and L1+ end are for connecting the two ends that same current transformer is corresponding, other roughly the same repeat no more.One end that inductance L 2 is connected with capacitor C 16 forms one end that PADIC1 holds, inductance L 3 is connected with capacitor C 18 and forms PADIC end, and PADIC1 end and PADIC end are all connected with the input of control processor 1.One end that inductance L 4 is connected with capacitor C 22 forms PADIA1 end, and one end that inductance L 5 is connected with capacitor C 26 forms PADIA end, and in like manner, PADIA1 end and PADIA end are all connected with the input of control processor 1.One end that inductance L 6 is connected with capacitor C 31 forms PADIB1 end, one end that inductance L 7 is connected with capacitor C 33 forms PADIB end, one end that inductance L 8 is connected with capacitor C 35 forms PADIN1 end, one end that inductance L 9 is connected with capacitor C 41 forms PADIN end, the all input connections corresponding with control processor 1 of PADIB1 end, PADIB end, PADIN1 end and PADIN end, thereby to four phase operating currents after the interior input processing of control processor 1.
As shown in Figure 6, described ground protection circuit 11 comprises operational amplifier U4A and operational amplifier U4B, one end of the in-phase end of described operational amplifier U4A and resistance R 63, one end of resistance R 64, one end of resistance R 65, one end of resistance R 66, one end of resistance R 71, one end of one end of capacitor C 50 and capacitor C 51 connects, and the other end of the other end of resistance R 71 and capacitor C 51 is all connected with 2.5V voltage, the other end of the end of oppisite phase of operational amplifier U4A and capacitor C 50, one end of resistance R 67, one end of resistance R 68, one end of resistance R 69, one end of resistance R 70, one end of one end of resistance R 72 and capacitor C 52 connects, the other end of the other end of resistance R 72 and capacitor C 52, the output of operational amplifier U4A, one end of one end of capacitor C 53 and resistance R 73 connects, the other end ground connection of capacitor C 53, the other end of resistance R 73 is connected with the end of oppisite phase of operational amplifier U4B and one end of resistance R 75, the other end of resistance R 75 is connected with the output of operational amplifier U4B and one end of capacitor C 54, the other end ground connection of capacitor C 54, the in-phase end of operational amplifier U4B is connected with 2.5V voltage by resistance R 74.
In the utility model embodiment, by the other end of resistance R 63, the other end of resistance R 67 is connected with the two ends of same sample circuit output in ground protection sample circuit 12, be connected for the two ends of exporting with the sample circuit of ground protection sample circuit 12 by the other end of resistance R 64 and the other end of resistance R 68, be connected for the two ends of exporting with the sample circuit of ground protection sample circuit 12 by the other end of resistance R 65 and the other end of resistance R 69, be connected for the two ends of exporting with the sample circuit of ground protection sample circuit 12 by the other end of resistance R 66 and the other end of resistance R 70, the end of oppisite phase of operational amplifier U4A, input is for receiving the earth current of ground protection sample circuit 12 samplings, the output of operational amplifier U4A forms PADIG1 end, the output of operational amplifier U4B forms PADIG end, PADIG1 end and PADIG end are all connected with the input of control processor 1, to realize to the interior input grounding protective current of control processor 1 value.
As shown in Figure 5, described trip circuit 5 comprises resistance R 48, one end of described resistance R 48 is connected with the cathode terminal of voltage stabilizing didoe D18 and the gate terminal of metal-oxide-semiconductor T3, the other end of resistance R 48 is connected with the anode tap of voltage stabilizing didoe D18 and the source terminal of metal-oxide-semiconductor T3, and the anode tap ground connection of voltage stabilizing didoe D18, the anode tap of the drain electrode end of metal-oxide-semiconductor T3 and voltage stabilizing didoe D19, one end of capacitor C 42, the in-phase end of one end of resistance R 49 and operational amplifier U3A connects, the cathode terminal of the cathode terminal of voltage stabilizing didoe D19 and diode D20, the cathode terminal of diode D21 connects, the anode tap of the anode tap of diode D20 and diode D21 all with one end of resistance R 53, one end of the output of operational amplifier U3A and capacitor C 43 connects, the positive power source terminal of operational amplifier U3A is connected with one end of 24V voltage and capacitor C 43, the other end ground connection of capacitor C 43, the negative power end ground connection of operational amplifier U3A, one end of the other end of resistance R 53 and resistance R 52, one end of resistance R 55, one end of resistance R 56, one end of resistance R 57, one end of one end capacitor C 47 of resistance R 58 and the cathode terminal of diode D28 connect, the end of oppisite phase of the other end of resistance R 52 and operational amplifier U3A, one end of resistance R 51, the end of oppisite phase of the end of oppisite phase of operational amplifier U3B and operational amplifier U3D connects,
The other end ground connection of capacitor C 42, the other end ground connection of resistance R 51, the other end of resistance R 49 is connected with one end, the cathode terminal of diode D22 and the cathode terminal of diode D23 of resistance R 50, the anode tap of diode D22 is by capacitor C 28 ground connection, the anode tap of diode D23 is by capacitor C 49 ground connection, the other end ground connection of resistance R 50; The other end of capacitor C 43 is connected with the in-phase end of operational amplifier U3B, one end, the cathode terminal of diode D24 and the cathode terminal of diode D25 of resistance R 54, the equal ground connection of anode tap of the other end of resistance R 54, the anode tap of diode D24 and diode D25;
The output of the other end of resistance R 55 and operational amplifier U3B, one end of resistance R 61, the anode tap of the anode tap of diode D26 and diode D27 connects, the other end of resistance R 61 is connected with one end of resistance R 80 and one end of capacitor C 43, the equal ground connection of the other end of the other end of resistance R 80 and capacitor C 43, the end of oppisite phase of the cathode terminal of diode D27 and operational amplifier U3C, one end of one end of resistance R 81 and capacitor C 44 connects, the equal ground connection of the other end of the other end of capacitor C 44 and resistance R 81, the in-phase end of the cathode terminal of diode D26 and operational amplifier U3D, one end of one end of resistance R 83 and capacitor C 46 connects, the equal ground connection of the other end of the other end of resistance R 83 and capacitor C 46,
The other end of resistance R 56 is connected with the in-phase end of operational amplifier U3C and one end of resistance R 60, the other end ground connection of resistance R 60, the output of operational amplifier U3C is connected with the other end of resistance R 57 and one end of capacitor C 45, the other end of capacitor C 45 is connected with the gate terminal of metal-oxide-semiconductor T3, the other end of the output of operational amplifier U3D and resistance R 58 with, one end of resistance R 62, the gate terminal of one end of capacitor C 58 and metal-oxide-semiconductor T4 connects, the equal ground connection of the other end of the other end of resistance R 62 and capacitor C 58, the other end ground connection of capacitor C 47, the source terminal ground connection of metal-oxide-semiconductor T4, the drain electrode end of metal-oxide-semiconductor T4 is connected with the anode tap of diode D30, the cathode terminal of diode D30 is connected with the cathode terminal of diode D29, the anode tap of diode D29 is connected with the anode tap of diode D28, and the anode tap of diode D29 is connected with 24V voltage.
In the utility model embodiment, the required 24V voltage of trip circuit 5 is provided by external circuit, the anode tap of diode D22 forms MCUTRIP end, hold with control processor 1 and be connected by MCUTRIP, resistance R 61 forms MCRTRIP end with the link of resistance R 80, is held with control processor 1 and is connected by MCRTRIP.
The voltage that the utility model provides control processor 1 to work by power circuit 10, obtain earth current value by ground protection treatment circuit 11, four phase current values while obtaining three phase mains work by four phase current treatment circuits 13, control processor 1 can drive circuit breaker tripping according to earth current value or working current value by trip circuit 5, control processor 1 is by USB communicating circuit 3, RS485 communicating circuit 2 is realized the communication with host computer, can carry out signal and State-output by signalling contact output circuit 6 and display circuit 8, compact conformation, intelligent degree is high, wide accommodation, safe and reliable.
Claims (9)
1. the intelligent controller for omnipotent breaker, comprise control processor (1) and for the power circuit (10) of control processor (1) operating voltage is provided, it is characterized in that: described control processor (1) also connects with the USB communicating circuit (3) for being connected with upper machine communication, the input of control processor (1) and ground protection treatment circuit (11), four phase current treatment circuits (13) connect, the output of control processor (1) and trip circuit (5), signalling contact output circuit (6) and display circuit (8) connect, control processor (1) is according to the driving of threading off of the ground protection current value control trip circuit (5) of the working current value of four phase current treatment circuits (13) inputs or ground protection treatment circuit (11) input, and carry out state instruction by signalling contact output circuit (6).
2. the intelligent controller for omnipotent breaker according to claim 1, is characterized in that: described control processor (1) is also connected with keyboard and indicator light circuit (9), memory (4) and RS485 communicating circuit (2).
3. the intelligent controller for omnipotent breaker according to claim 1, is characterized in that: described control processor (1) is connected with display circuit (8) by display driver circuit (7); Described display circuit (8) comprises display screen.
4. the intelligent controller for omnipotent breaker according to claim 1, is characterized in that: described power circuit (10) comprises diode D1, the cathode terminal of described diode D1 is connected with the cathode terminal of diode D2, the cathode terminal of diode D3, the cathode terminal of diode D4, cathode terminal, the cathode terminal of diode D11 and the drain electrode end of metal-oxide-semiconductor T1 of diode D5, the anode tap of diode D1 is connected with the cathode terminal of diode D6, the anode tap ground connection of diode D6, the anode tap of diode D2 is connected with the cathode terminal of diode D7, the anode tap ground connection of diode D7, the anode tap of diode D3 is connected with the cathode terminal of diode D8, the anode tap ground connection of diode D8, the anode tap of diode D4 is connected with the cathode terminal of diode D9, the anode tap ground connection of diode D9, the anode tap of diode D5 is connected with the cathode terminal of diode D10, the anode tap ground connection of diode D10, one end of the anode tap of diode D11 and resistance R 1, the anode tap of voltage stabilizing didoe D12, the source terminal of metal-oxide-semiconductor T1 connects, and the anode tap ground connection of diode D11,
One end of the other end of resistance R 1 and resistance R 2, the gate terminal of the cathode terminal of voltage stabilizing didoe D12 and metal-oxide-semiconductor T1 connects, the drain electrode end of metal-oxide-semiconductor T1 is connected with one end of resistance R 3, the gate terminal of the other end of resistance R 3 and metal-oxide-semiconductor T2, the cathode terminal of voltage stabilizing didoe D13 connects, the anode tap of voltage stabilizing didoe D13 is connected with the source terminal of metal-oxide-semiconductor T2 and the anode tap of diode D14, the anode tap of the cathode terminal of diode D14 and diode D16, the cathode terminal of diode D15, one end of one end of capacitor C 1 and capacitor C 2 connects, the anode tap ground connection of diode D15, the other end ground connection of the other end of capacitor C 1 and capacitor C 2, one end of the cathode terminal of diode D16 and capacitor C 3, the VIN end of one end of capacitor C 4 and chip U1 connects, the equal ground connection of the other end of the other end of capacitor C 3 and capacitor C 4, the SS/TR end of chip U1 is by capacitor C 5 ground connection, the TR/LCK end of chip U1 is by resistance R 4 ground connection, the GND end ground connection of chip U1, the BOOT end of chip U1 is connected with the PH end of chip U1 by capacitor C 8, the PH end of chip U1 is connected with the cathode terminal of diode D17 and one end of inductance L 1, the anode tap ground connection of diode D17, the other end of inductance L 1 is connected with one end of capacitor C 9 and one end of capacitor C 10, the other end ground connection of the other end of capacitor C 9 and capacitor C 10, the COMP end of chip U1 is connected with one end of resistance R 7 and one end of capacitor C 7, the other end of resistance R 7 is by capacitor C 6 ground connection, the other end ground connection of capacitor C 7, the VSENSE end of chip U1 is connected with one end of resistance R 5 and one end of resistance R 6, one end ground connection of resistance R 6, the other end of resistance R 5 is connected with the other end of inductance L 1.
5. the intelligent controller for omnipotent breaker according to claim 2, is characterized in that: described memory comprises chip U2, and it is CAT1161WI-42-GT3 chip that described chip U2 adopts model, provide with power circuit (10)+5V voltage of the VCC end of chip U2 is connected, the WP end of chip U2 is connected with one end of resistance R 9, one end of the other end of resistance R 9 and resistance R 10, provide+5V voltage of one end of resistance R 11 and power circuit (10) connects, the other end of resistance R 10 is connected with the SDA end of chip U2, the other end of resistance R 11 is connected with the SCL end of chip U2, chip U2 /RESET end is connected with one end of resistance R 8 and one end of capacitor C 11, the other end of resistance R 8 is connected with provide+5V voltage of power circuit (10), the other end ground connection of capacitor C 11.
6. the intelligent controller for omnipotent breaker according to claim 1, it is characterized in that: described USB communicating circuit (3) comprises chip U3 and interface J1, described chip U3 adopts the chip that model is XR21V1410, the LOWPOWER end of described chip U3 is connected with 3.3V voltage by resistance R 79, the VCC end of chip U3 is connected with 3.3V voltage, the USBD+ end of chip U3, the USBD-end of chip U3 and the D+ end of interface J1, D-end is corresponding to be connected, and the USBD+ of chip U3 end, the USBD-end of chip U3 is by electrostatic protection diode D31 ground connection, the G end of interface J1 is connected with one end of capacitor C 56 and one end of inductance L 10, the other end of capacitor C 56 is connected with the 5V end of interface J1 and one end of inductance L 11, provide+5V voltage of one end of the other end of inductance L 11 and capacitor C 57 and power circuit (10) is connected, the other end of capacitor C 57 is connected with the other end of inductance L 10, and the other end ground connection of capacitor C 57, the RX end of chip U3 is connected with the collector terminal of triode Q1, the collector terminal of triode Q1 is also connected with one end of resistance R 77, the other end of resistance R 77 is connected with 3.3V voltage, one end of the base terminal of triode Q1 and resistance R 76, one end of one end of resistance R 78 and capacitor C 55 connects, the other end ground connection of the other end of capacitor C 55 and resistance R 78, the other end of resistance R 76 is connected with provide+5V voltage of power circuit (10).
7. the intelligent controller for omnipotent breaker according to claim 1, it is characterized in that: described four phase current treatment circuits (13) comprise resistance R 12, one end of described resistance R 12 is connected with 2.5V voltage, the other end of resistance R 12 is connected with one end of capacitor C 12 and one end of resistance R 13, one end of the other end of resistance R 13 and capacitor C 13, one end of capacitor C 14, the end of oppisite phase of one end of resistance R 15 and operational amplifier U1A connects, the other end of the other end of resistance R 15 and capacitor C 14, one end of the output of operational amplifier U1A and inductance L 2 connects, the other end of inductance L 2 is by capacitor C 16 ground connection, the output of operational amplifier U1A is connected with one end of resistance R 18, one end of the other end of resistance R 18 and capacitor C 17, the end of oppisite phase of one end of resistance R 20 and operational amplifier U1B connects, the other end of resistance R 20 is connected with the output of operational amplifier U1B and one end of inductance L 3, the other end of inductance L 3 is by capacitor C 18 ground connection, the other end of capacitor C 12 is connected with one end of resistance R 17 and the other end of resistance R 14, the other end of resistance R 14 is connected with the other end of capacitor C 13, one end, one end of capacitor C 15 and the in-phase end of operational amplifier U1A of resistance R 16, the other end of capacitor C 17 is connected with the in-phase end of operational amplifier U1B and one end of resistance R 19, and the other end of resistance R 19 is connected with the other end of capacitor C 15, the other end of resistance R 16, the other end of resistance R 17, one end and the 2.5V voltage of resistance R 21,
The other end of resistance R 21 is connected with one end of capacitor C 19 and one end of resistance R 22, one end of the other end of resistance R 22 and capacitor C 20, one end of resistance R 23, the end of oppisite phase of one end of capacitor C 21 and operational amplifier U1C connects, the other end of the other end of resistance R 23 and capacitor C 21, the output of operational amplifier U1C, one end of one end of resistance R 25 and inductance L 4 connects, the other end of inductance L 4 is by capacitor C 22 ground connection, one end of the other end of resistance R 25 and capacitor C 24, the end of oppisite phase of one end of resistance R 24 and operational amplifier U1D connects, the other end of resistance R 24 is connected with the output of operational amplifier U1D and one end of inductance L 5, the other end of inductance L 5 is by capacitor C 26 ground connection, the negative power end ground connection of operational amplifier U1D, the positive power source terminal of operational amplifier U1D is connected with one end of+5V voltage and capacitor C 25, the other end ground connection of capacitor C 25, the other end of capacitor C 19 is connected with one end of resistance R 27 and one end of resistance R 28, the other end of the other end of resistance R 27 and capacitor C 20, one end of resistance R 29, the in-phase end of one end of capacitor C 23 and operational amplifier U1C connects, the other end of capacitor C 24 is connected with the in-phase end of operational amplifier U1D and the other end of resistance R 26, the other end of the other end of resistance R 26 and capacitor C 23, the other end of resistance R 29, the other end of resistance R 28, one end of resistance R 30 and 2.5V voltage connect,
The other end of resistance R 30 is connected with one end of capacitor C 27 and one end of resistance R 31, one end of the other end of resistance R 31 and capacitor C 28, one end of capacitor C 29, the end of oppisite phase of one end of resistance R 32 and operational amplifier U2A connects, the other end of the other end of resistance R 32 and capacitor C 29, the output of operational amplifier U2A, one end of one end of resistance R 33 and inductance L 6 connects, the other end of inductance L 6 is by capacitor C 31 ground connection, one end of the other end of resistance R 33 and capacitor C 32, the end of oppisite phase of one end of resistance R 34 and operational amplifier U2B connects, the other end of resistance R 34 is connected with the output of operational amplifier U2B and one end of inductance L 7, the other end of inductance L 7 is by capacitor C 33 ground connection, the other end of capacitor C 27 is connected with one end of resistance R 36 and one end of resistance R 37, the other end of the other end of resistance R 36 and capacitor C 28, one end of resistance R 38, the in-phase end of one end of capacitor C 30 and operational amplifier U2A connects, the other end of capacitor C 32 is connected with the in-phase end of operational amplifier U2B and one end of resistance R 35, the other end of the other end of resistance R 35 and capacitor C 30, the other end of resistance R 38, the other end of resistance R 37, one end of resistance R 39 and 2.5V voltage connect,
The other end of resistance R 39 is connected with one end of capacitor C 36 and one end of resistance R 40, one end of the other end of resistance R 40 and capacitor C 37, one end of capacitor C 34, the end of oppisite phase of one end of resistance R 41 and operational amplifier U2C connects, the other end of the other end of resistance R 41 and capacitor C 34, the output of operational amplifier U2C with, one end of one end of inductance L 8 and resistance R 46 connects, the other end of inductance L 8 is by capacitor C 35 ground connection, one end of the other end of resistance R 46 and capacitor C 39, the end of oppisite phase of one end of resistance R 42 and operational amplifier U2D connects, the other end of resistance R 42 is connected with one end of inductance L 9, the other end of inductance L 9 is by capacitor C 41 ground connection, the negative power end ground connection of operational amplifier U2D, one end of the positive power source terminal of operational amplifier U2D and capacitor C 40 and+5V voltage is connected, the other end ground connection of capacitor C 40, the other end of capacitor C 36 is connected with one end of resistance R 43 and one end of resistance R 44, the other end of resistance R 43 is connected with the other end of capacitor C 37, one end, one end of capacitor C 38 and the in-phase end of operational amplifier U2C of resistance R 45, the other end of capacitor C 39 is connected with the in-phase end of operational amplifier U2D and one end of resistance R 47, and the other end of resistance R 47 is connected with the other end of capacitor C 38, the other end of resistance R 45, the other end and the 2.5V voltage of resistance R 44.
8. the intelligent controller for omnipotent breaker according to claim 1, it is characterized in that: described ground protection circuit (11) comprises operational amplifier U4A and operational amplifier U4B, one end of the in-phase end of described operational amplifier U4A and resistance R 63, one end of resistance R 64, one end of resistance R 65, one end of resistance R 66, one end of resistance R 71, one end of one end of capacitor C 50 and capacitor C 51 connects, the other end of the other end of resistance R 71 and capacitor C 51 is all connected with 2.5V voltage, the other end of the end of oppisite phase of operational amplifier U4A and capacitor C 50, one end of resistance R 67, one end of resistance R 68, one end of resistance R 69, one end of resistance R 70, one end of one end of resistance R 72 and capacitor C 52 connects, the other end of the other end of resistance R 72 and capacitor C 52, the output of operational amplifier U4A, one end of one end of capacitor C 53 and resistance R 73 connects, the other end ground connection of capacitor C 53, the other end of resistance R 73 is connected with the end of oppisite phase of operational amplifier U4B and one end of resistance R 75, the other end of resistance R 75 is connected with the output of operational amplifier U4B and one end of capacitor C 54, the other end ground connection of capacitor C 54, the in-phase end of operational amplifier U4B is connected with 2.5V voltage by resistance R 74.
9. the intelligent controller for omnipotent breaker according to claim 1, it is characterized in that: described trip circuit (5) comprises resistance R 48, one end of described resistance R 48 is connected with the cathode terminal of voltage stabilizing didoe D18 and the gate terminal of metal-oxide-semiconductor T3, the other end of resistance R 48 is connected with the anode tap of voltage stabilizing didoe D18 and the source terminal of metal-oxide-semiconductor T3, and the anode tap ground connection of voltage stabilizing didoe D18, the anode tap of the drain electrode end of metal-oxide-semiconductor T3 and voltage stabilizing didoe D19, one end of capacitor C 42, the in-phase end of one end of resistance R 49 and operational amplifier U3A connects, the cathode terminal of the cathode terminal of voltage stabilizing didoe D19 and diode D20, the cathode terminal of diode D21 connects, the anode tap of the anode tap of diode D20 and diode D21 all with one end of resistance R 53, one end of the output of operational amplifier U3A and capacitor C 43 connects, the positive power source terminal of operational amplifier U3A is connected with one end of 24V voltage and capacitor C 43, the other end ground connection of capacitor C 43, the negative power end ground connection of operational amplifier U3A, one end of the other end of resistance R 53 and resistance R 52, one end of resistance R 55, one end of resistance R 56, one end of resistance R 57, one end of one end capacitor C 47 of resistance R 58 and the cathode terminal of diode D28 connect, the end of oppisite phase of the other end of resistance R 52 and operational amplifier U3A, one end of resistance R 51, the end of oppisite phase of the end of oppisite phase of operational amplifier U3B and operational amplifier U3D connects,
The other end ground connection of capacitor C 42, the other end ground connection of resistance R 51, the other end of resistance R 49 is connected with one end, the cathode terminal of diode D22 and the cathode terminal of diode D23 of resistance R 50, the anode tap of diode D22 is by capacitor C 28 ground connection, the anode tap of diode D23 is by capacitor C 49 ground connection, the other end ground connection of resistance R 50; The other end of capacitor C 43 is connected with the in-phase end of operational amplifier U3B, one end, the cathode terminal of diode D24 and the cathode terminal of diode D25 of resistance R 54, the equal ground connection of anode tap of the other end of resistance R 54, the anode tap of diode D24 and diode D25;
The output of the other end of resistance R 55 and operational amplifier U3B, one end of resistance R 61, the anode tap of the anode tap of diode D26 and diode D27 connects, the other end of resistance R 61 is connected with one end of resistance R 80 and one end of capacitor C 43, the equal ground connection of the other end of the other end of resistance R 80 and capacitor C 43, the end of oppisite phase of the cathode terminal of diode D27 and operational amplifier U3C, one end of one end of resistance R 81 and capacitor C 44 connects, the equal ground connection of the other end of the other end of capacitor C 44 and resistance R 81, the in-phase end of the cathode terminal of diode D26 and operational amplifier U3D, one end of one end of resistance R 83 and capacitor C 46 connects, the equal ground connection of the other end of the other end of resistance R 83 and capacitor C 46,
The other end of resistance R 56 is connected with the in-phase end of operational amplifier U3C and one end of resistance R 60, the other end ground connection of resistance R 60, the output of operational amplifier U3C is connected with the other end of resistance R 57 and one end of capacitor C 45, the other end of capacitor C 45 is connected with the gate terminal of metal-oxide-semiconductor T3, the other end of the output of operational amplifier U3D and resistance R 58 with, one end of resistance R 62, the gate terminal of one end of capacitor C 58 and metal-oxide-semiconductor T4 connects, the equal ground connection of the other end of the other end of resistance R 62 and capacitor C 58, the other end ground connection of capacitor C 47, the source terminal ground connection of metal-oxide-semiconductor T4, the drain electrode end of metal-oxide-semiconductor T4 is connected with the anode tap of diode D30, the cathode terminal of diode D30 is connected with the cathode terminal of diode D29, the anode tap of diode D29 is connected with the anode tap of diode D28, and the anode tap of diode D29 is connected with 24V voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420222419.7U CN203933155U (en) | 2014-04-30 | 2014-04-30 | For the intelligent controller of omnipotent breaker |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420222419.7U CN203933155U (en) | 2014-04-30 | 2014-04-30 | For the intelligent controller of omnipotent breaker |
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| Publication Number | Publication Date |
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| CN203933155U true CN203933155U (en) | 2014-11-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201420222419.7U Withdrawn - After Issue CN203933155U (en) | 2014-04-30 | 2014-04-30 | For the intelligent controller of omnipotent breaker |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956829A (en) * | 2014-04-30 | 2014-07-30 | 罗格朗低压电器（无锡）有限公司 | Intelligent controller used for universal circuit breaker |
-
2014
- 2014-04-30 CN CN201420222419.7U patent/CN203933155U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103956829A (en) * | 2014-04-30 | 2014-07-30 | 罗格朗低压电器（无锡）有限公司 | Intelligent controller used for universal circuit breaker |
| CN103956829B (en) * | 2014-04-30 | 2015-12-23 | 罗格朗低压电器（无锡）有限公司 | For the intelligent controller of omnipotent breaker |
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