CN203912103U

CN203912103U - Image transmission circuit of high speed framing camera

Info

Publication number: CN203912103U
Application number: CN201420351054.8U
Authority: CN
Inventors: 瞿鑫; 吴云峰; 郑天策; 李华栋; 夏涛; 戴磊
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2014-06-27
Filing date: 2014-06-27
Publication date: 2014-10-29
Anticipated expiration: 2024-06-27

Abstract

The technical problem to be solved in the utility model is that, multipath image data collected by the high speed framing camera in the prior art are transmitted in multipath transmission channels and are received by multiple receiving network interface cards, size is large and long-distance transmission is not convenient. In order to solve the problem, the image transmission circuit of a high speed framing camera comprises a multipath data input terminal, a network transformer, a physical layer chip, a DDR memory cell, a FPGA unit and a single-path data output terminal. The multipath data input terminal is connected with the physical layer chip through the network transformer. The physical layer chip is connected with the DDR memory cell through the FPGA unit. The single-path data output terminal is connected with the physical layer chip.

Description

The image transmission circuit of high speed framing camera

Technical field

The utility model relates to field of image transmission, especially relates to the image transmission circuit of high speed framing camera.

Background technology

High speed framing camera is not only applied to the fields such as digital photography, intelligent transportation and checkout equipment, is also widely used in the industry such as machine vision, medical treatment.The data volume of the view data that high speed framing camera gathers is very large, and the transmission of big data quantity is also more and more higher to the requirement of camera transmission rate.In framing camera shooting process, organize CCD (Charge Coupled Device) camera continuous sampling more, every group of camera has fixing adjustable nanosecond rank time delay, thereby, observe the dynamic process of particle by the multiple series of images obtaining.

In the prior art, for the transmission of high speed framing camera photographic images, multiple reception network interface cards need to be set in computer, many group cameras are connected with the multiple reception network interface cards in computer by many netting twines respectively, the volume and weight that many netting twines and multiple built-in reception network interface card take is very large, cost is high, and, be unfavorable for the integrated of the long-distance transmissions of image and system.

Utility model content

Technical problem to be solved in the utility model is that the multiway images data that prior art high speed framing camera collects need to be transmitted by multiplexer channel, and utilizes multiple reception network interface cards to receive, and volume is large, is unfavorable for long-distance transmissions.

For addressing the above problem, the utility model provides the image transmission circuit of high speed framing camera, comprise multichannel data input, network transformer, physical chip, DDR memory cell, FPGA unit and single channel data output end, described multichannel data input is connected with physical chip by network transformer, physical chip is connected with DDR memory cell by FPGA unit, and single channel data output end is connected with physical chip.

Further, described multichannel data input comprises at least two data transmission interfaces.

Further, described data transmission interface is specially RJ-45 interface.

Further, also comprise flash memory, flash memory is connected with described FPGA unit.

Further, described single channel data output end comprises SFP module.

Further, described DDR memory cell comprises an external interface, and described external interface is UART interface.

The beneficial effects of the utility model are: by FPGA unit and DDR memory cell, after the multiway images data that the application's image transmission circuit obtains at the multiple CCD cameras of reception, converting multichannel input to single channel transmits, no longer need multiplexer channel, greatly reduce the volume and weight of equipment, and then, more be conducive to the integrated of long-distance transmissions and system, and also improve the stability of transfer of data, in addition, owing to being single channel output, making controller only need to possess one and receive network interface card;

By SFP module, view data can, in the mode of light signal, be transmitted through optical fiber, thereby the distance that view data can be transmitted is farther, throughput is larger;

By the external interface in DDR memory cell, the application's image transmission circuit can externally connected with display screen, and directly multilevel image data shows, no longer relies on controller, can off-line working.

Brief description of the drawings

Fig. 1 is the structural representation of the image transmission circuit of the utility model high speed framing camera.

Embodiment

Below in conjunction with accompanying drawing, the technical solution of the utility model is described in detail.

The image transmission circuit of high speed framing camera of the present utility model, comprise multichannel data input, network transformer, physical chip, DDR memory cell, FPGA unit and single channel data output end, described multichannel data input is connected with physical chip by network transformer, physical chip is connected with DDR memory cell by FPGA unit, and single channel data output end is connected with physical chip.

By FPGA unit and DDR memory cell, after the multiway images data that the application's image transmission circuit obtains at the multiple CCD cameras of reception, convert multichannel input to single channel and transmit, no longer need multiplexer channel, greatly reduced the volume and weight of equipment, and then, more be conducive to the integrated of long-distance transmissions and system, and also improved the stability of transfer of data, in addition, owing to being single channel output, making controller only need to possess one and receive network interface card.

The image transmission circuit of the application's high speed framing camera, be applied between at least two CCD cameras and the computer as controller, for being merged into single channel transmission channel from the multiplexer channel of CCD camera, thereby make view data be transferred to controller through single channel transmission channel, in controller, only need one to receive network interface card, i.e. capture card.As shown in Figure 1, described image transmission circuit 1 comprises multichannel data input, network transformer, physical chip, DDR memory cell, FPGA unit and single channel data output end.Wherein, multichannel data input is connected with physical chip by network transformer, and physical chip is connected with DDR memory cell by FPGA unit, and single channel data output end is connected with physical chip.

In this application, multiple CCD cameras are made a video recording continuously, and the nanosecond time is fixed in each camera time delay, to view data, can observe dynamic process according to view data by multiple CCD collected by cameras.And multiple CCD cameras are connected with described image transmission circuit 1 by multiple data transmission interfaces at the multichannel data input of described image transmission circuit 1, the corresponding data transmission interface of each CCD camera.Concrete, because the application's described image transmission circuit 1 is applied in the environment that comprises at least two CCD cameras, therefore, described multichannel data input comprises at least two data transmission interfaces, described data transmission interface is RJ-45 interface.

In specific implementation process, when multiple CCD collected by cameras are after view data, enter described image transmission circuit through CAT-5 netting twine by multichannel data input, first, network transformer carries out signal enhancing and level match to view data, make view data meet Internet Transmission requirement, then, physical chip carries out physical code and code stream control to view data, then, by FPGA unit to view data decode, decapsulation, thereby go back original digital image data, then by reduction after view data store in DDR memory cell.Wherein, multiple CCD collected by cameras to multiway images data all store with DDR memory cell in.

In this application, by FPGA unit controls, read arbitrary road view data of poke in DDR memory cell, then, carry out physical code and code stream control through physical chip, last, export to controller by single channel data output end.Preferably, single channel data output end comprises SFP (Small Form Pluggable, SFP) module, SFP module is for being converted to light signal by the gigabit Ethernet signal of telecommunication, thereby, in this application, single channel data output end can be converted to light signal by the signal of telecommunication by view data, make light signal by Optical Fiber Transmission to controller.It should be noted that, preferably, because Internet Transmission is two-way, by controller sending controling instruction to FPGA unit, thereby realize the control of FPGA unit to DDR memory cell, control command is by single channel data output end, through physical chip, be delivered to FPGA unit, by this structure, can make the stability of transfer of data be improved.

In addition, the control mode of FPGA unit comprises physical layer and data link layer, and due to the gigabit Ethernet IP kernel that FPGA unit has itself, data link layer is realized by described IP kernel, and physical layer is realized by physical chip.In specific implementation process, XC4FX20 chip can be selected in FPGA unit, and DDR memory cell can be selected HYB25D256160BT chip, and physical chip can be selected 88E1111 chip.It should be noted that, XC4FX20 chip is the fpga chip with two IP kernels, it can process the transmission of two-way view data, if there are 8 tunnel view data to need transmission, need 4 fpga chips, but, the quantity difference of the IP kernel having due to different fpga chips, if adopt the chip of other models, transmit that 8 tunnel view data may need still less or more chip, those of ordinary skill in the art can select the included chip-count in FPGA unit and chip model according to actual conditions, and the application does not limit.

Further, in this application, described image transmission circuit 1 also comprises flash memory, and described flash memory is connected with FPGA unit.Flash memory is used for storing data, and in the time of described image transmission circuit 1 power down, described flash memory still ensures that data do not lose.

Preferably, in this application, DDR memory cell comprises an external interface, concrete, described external interface is UART interface, and this external interface is for externally connected with display screen, in the time that external interface is connected with a LCDs, view data by asynchronous serial communication mode by image data transmission in LCDs, can show view data.

Claims

1. the image transmission circuit of high speed framing camera, it is characterized in that, comprise multichannel data input, network transformer, physical chip, DDR memory cell, FPGA unit and single channel data output end, described multichannel data input is connected with physical chip by network transformer, physical chip is connected with DDR memory cell by FPGA unit, and single channel data output end is connected with physical chip.

2. the image transmission circuit of high speed framing camera as claimed in claim 1, is characterized in that, described multichannel data input comprises at least two data transmission interfaces.

3. the image transmission circuit of high speed framing camera as claimed in claim 2, is characterized in that, described data transmission interface is specially RJ-45 interface.

4. the image transmission circuit of high speed framing camera as claimed in claim 1, is characterized in that, also comprises flash memory, and flash memory is connected with described FPGA unit.

5. the image transmission circuit of high speed framing camera as claimed in claim 1, is characterized in that, described single channel data output end comprises SFP module.

6. the image transmission circuit of high speed framing camera as claimed in claim 1, is characterized in that, described DDR memory cell comprises an external interface, and described external interface is UART interface.