CN203910785U - Semiconductor device - Google Patents
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- CN203910785U CN203910785U CN201320675635.2U CN201320675635U CN203910785U CN 203910785 U CN203910785 U CN 203910785U CN 201320675635 U CN201320675635 U CN 201320675635U CN 203910785 U CN203910785 U CN 203910785U
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000001465 metallisation Methods 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 13
- 238000000576 coating method Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 10
- 229920005591 polysilicon Polymers 0.000 claims description 9
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- 239000010937 tungsten Substances 0.000 claims description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910010293 ceramic material Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- 239000004411 aluminium Substances 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 229910021332 silicide Inorganic materials 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 29
- 238000009413 insulation Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Abstract
The utility model provides a semiconductor device comprising a compensation zone, a transistor unit and a gate electrode metalized layer, wherein the compensation zone comprises a p zone and an n zone, the transistor unit is positioned on the compensation zone and comprises a gate electrode which is surrounded by a gate electrode dielectric, and the gate electrode metalized layer is arranged on the gate electrode dielectric. The semiconductor device comprises a plug with which a contact hole is filled, the contact hole which is formed by penetrating the gate electrode dielectric between the gate electrode and the gate electrode metalized layer, and therefore the gate electrode and the gate electrode metalized layer can be electrically connected.
Description
Technical field
The utility model relates to semiconductor device, relates in particular to a kind of super junction device with reliable contact structures.
Background technology
Super junction transistors has reduced conduction resistance by extending vertically up to n district in semiconductor body and the compensation in p district.For illustrative purposes, Fig. 1 shows a kind of typical super junction transistors device.
As shown in fig. 1, this device has semiconductor body, and this semiconductor body has compensating basin, and this compensating basin comprises p district (p post) 130 and n district (n post) 134.Compensating basin is connected to MOS transistor unit, and this MOS transistor unit comprises source electrode 118, tagma 138 and control grid 114.Insulation system 140 is by grid 114 and tagma 138, source electrode 118, n district (n post) 134 and metal layer 110 electricity isolation.And a part for insulation system 140 can be used as gate insulator.Transistorized drain electrode 128 is connected to highly doped substrate 124.Resilient coating 126 is between described substrate and described compensating basin.Each source electrode contact is electrically connected mutually by metal layer 110.Drain electrode contact is structured in the back side of device and is covered by the metallization 128 of super junction device.
Described compensation means, in the blocking-up operating period of super junction transistors, the image charge that the donor ion of the positively charged in n post has is in the electronegative acceptor ion in p post.Therefore,, in each plane parallel with the upper surface of super junction transistors, net charge must be more much smaller than the absolute value of two independent electric charges.Different from traditional power transistor, super junction transistors has relatively high transverse electric field Ex, the boundary of its maximum between p post and n post.In normal blocking-up operating period, the maximum of this electric field must not exceed the critical electric field (being roughly 200kV/cm) of Si.Can be according to formula E in blocking-up operation
x=∫ ρ (x)/ε dx calculates electric field Ex with the integration of the whole electric charges in semi-conducting material, and wherein, ρ (x) represents charge density, and ε represents the dielectric constant of described semi-conducting material.Charge density ρ (x) is all multiplied by elementary charge e difference afterwards by donor doping n (x) and acceptor doping p (x) and provides.Ignore respectively the minority doping in p post and n post, by the lateral charge dosage d to give a definition with the 1/cm2 of unit
pand d
n: d
p=∫ p (x) dx, for example, starts to horizontal pn knot with the center of p post (" A "), that is, and and W
p, and the integration d of total electrical charge
n=∫ n (x) dx, ties the center that starts to arrive n post (" B ") with horizontal pn, that is, and and W
n.D
pand d
nabsolute value must be less than about 1 ~ 2 × 10
12atom/cm2 is to guarantee blocking ability.
In conducting operating process, only in n post for example with super junction transistors chip area probably only half carry load current.
In order to improve the dynamic characteristic of super junction transistors, wish to reduce to have the required chip area of power transistor of required conducting resistance.Another advantage of less semiconductor regions is less device cost.
Object is to improve doping density in n post better to be surpassed the conductance of junction transistors.
As mentioned above, the horizontal integration of the quilt in x direction of the doping in a n post or p post-by being approximately 2 × 10
12the value restriction of atom/cm2.The doping density for example increasing in n post will be d
nproduce the lower value of a described n post width half.This is also same for p post, its drain space and can not contributing for the conductance of conducting state.
As first approximation, the conductance of n post therefore with width 2 × d
nirrelevant, only relevant with integration amount ∫ n (x) dx of doping.
The method of unique conduction resistance that is used for increasing for the amount of the n doping of on state characteristic and be used for reducing described super junction transistors is to reduce cell pitch p to have more n post at every chip area.
But, in this case, can be used for the chip area of gate electrode and the width c of gate contact is all reduced.
Less gate electrode width will cause resistance to increase and be dispersed and the inhomogeneous switch behavior of super junction transistors.Too little contact hole or contact trench can not be filled gate metalized reliably, and this is by the integrity problem that causes contact resistance to increase and produce along with the operating time of super junction transistors.
Need so a kind of structure, it can make the cellular construction of super junction transistors have little pitch, thereby keeps contacting and uniform switch with the reliable of grid.
Utility model content
The purpose of this utility model is to solve above one or more problems.
In order to realize described object, according to an aspect of the present utility model, provide a kind of semiconductor device, it comprises:
Compensating basin, it comprises p district and n district;
Be positioned at the transistor unit that comprises gate electrode on described compensating basin, described gate electrode is surrounded by gate-dielectric; And
Be arranged in the gate metallization on gate-dielectric,
It is characterized in that, described semiconductor device also comprises the connector of the contact hole that fills up the formation of the gate-dielectric through gate electrode and gate metallization, so that electric connection grid electrode and gate metallization.
In certain embodiments, described connector is formed by polysilicon.
In certain embodiments, described connector is formed by barrier material layer and the tungsten layer on barrier material layer.
In certain embodiments, described barrier material layer comprises conducting ceramic material.
In certain embodiments, described conducting ceramic material comprises one of titanium nitride and tantalum nitride.
In certain embodiments, the thickness of described tungsten layer is at least half of the width of described contact hole.
In certain embodiments, described semiconductor device also comprises the metal silicide layer between barrier material layer and contact hole bottom.
In certain embodiments, described connector is recessed below the upper surface of gate-dielectric.
In certain embodiments, described connector has the space of having filled different materials.
In certain embodiments, described different materials comprises in air, vacuum, silica, silicon nitride and gate metal.
In certain embodiments, described gate electrode is disposed in groove.
In certain embodiments, described semiconductor device also comprises in vertical direction by the source metallization layer of insulator and gate metallization isolation.
In certain embodiments, described gate electrode has 1/2 the width that is less than transistor unit pitch.
In certain embodiments, described gate electrode has 1/3 the width that is less than transistor unit pitch.
In certain embodiments, described semiconductor device also comprises substrate and the resilient coating between substrate and compensating basin.
In certain embodiments, described resilient coating is greater than the doping content on its top in the doping content of its underpart.
In certain embodiments, described n district is greater than the doping content on its top in the doping content of its underpart.
In certain embodiments, described transistor unit also comprises the tagma that is arranged in compensating basin and the source region that embeds described tagma.
In certain embodiments, described semiconductor device is super junction device.
In certain embodiments, described gate metallization comprises in aluminium, copper and silicon.
Brief description of the drawings
These and other feature and advantage of the present utility model are by by becoming obviously below with reference to the detailed description of accompanying drawing, in the accompanying drawings:
The sectional view of the super junction transistors of the schematically illustrated typical case of Fig. 1.
Fig. 2 a-2c is schematically illustrated according to the sectional view of three of a part for super junction transistors of the present utility model limiting examples.
Fig. 3 is schematically illustrated according to the sectional view of the different embodiment that electrically contact between the gate metallization in super junction transistors of the present utility model and gate electrode structure.
Embodiment
Referring now to the accompanying drawing that embodiment of the present utility model is shown, embodiment of the present utility model is more fully described hereinafter.But the utility model can carry out specifically to implement and should not be construed as limited to embodiment described in this paper in many different forms.Or rather, it is in order to make the disclosure content more thoroughly with complete that these embodiment are provided, and will pass on all sidedly scope of the present utility model to those skilled in the art.Spread all in full, similar numeral refers to similar element.In addition, the Ceng He of each shown in accompanying drawing district is schematically and is not necessarily to scale.Therefore the utility model is not limited to the relative size shown in accompanying drawing, spacing and aligning.In addition, be familiar with as those skilled in the art, the layer being formed on substrate or other layer mentioned in this article can refer to be formed directly into the layer on substrate or other layer, the layer in one or more interlayer that also can refer to form on substrate or other layer.And term " the first conduction type " and " the second conduction type " refer to contrary conduction type, for example N or P type, but the each embodiment that describes and illustrate here also comprises its complementary embodiment.
The term that used is in this article just to describing the object of specific embodiment and being not intended to limit the utility model.As used herein, singulative " ", " one " and " being somebody's turn to do " intention also comprise plural form, unless otherwise clearly instruction of context.Also will understand, when using term " to comprise " herein and/or when " comprising ", it specifies the existence of feature, entirety, step, operation, element and/or the parts narrated, but does not get rid of existence or the interpolation of one or more further features, entirety, step, operation, element, parts and/or its cohort.
Unless otherwise limited, all terms (comprising technology and scientific terminology) that use herein have the implication identical with the implication of conventionally understanding as the utility model those skilled in the art.Also should be interpreted as thering is the implication consistent with they implications in background and the association area of this specification by understanding term as used herein, and by not explaining in mode idealized or form-separating excessively, so limit unless clear and definite in this article.
Accompanying drawing is by illustrating relative doping content at doping type " n " or " p " side instruction "-" or "+".For example, " n-" represents the doping content lower than the doping content of " n " doped region, and " n+ " doped region has than " n " the doping content that doped region is high.The doped region of identical relative doping content there is no need to have identical absolute doping content.For example, two different " n " doped regions can have identical or different absolute doping content.
Fig. 2 a-2c shows the schematic sectional view of three limiting examples of super junction transistors.Show the different possibility for realizing compensating basin and selectable buffer district.These examples are also nonrestrictive, and it can be combined into different schemes by any way.For the sake of simplicity, only a part of active area, that is, the cross section in the region of carrying normal load electric current is illustrated.And transistorized other parts, as edge termination system, scribe area or grid connection etc. does not clearly illustrate in Fig. 2 a-2c.Shown device has semiconductor body, it has compensating basin, and described compensating basin comprises p district (p post) 230 and n district (n post) 234, wherein said compensation,, the difference of the doping between p post and n post can be both also can change uniformly in vertical direction.
Described compensating basin is connected to MOS transistor unit, and MOS transistor unit comprises source electrode 218, tagma 238 and control grid 214.In shown example, grid is built into the planar gate electrodes that is positioned at semiconductor body top.But described grid also can enter in the groove in described semiconductor body to realize in etching.
Insulation system 240, for example oxide, by grid 214 and tagma 238, source electrode 218, n district (n post) 234 and metal layer 210 electricity isolation.And a part for insulation system 240 can be used as gate insulator.
Transistorized drain electrode 228 is connected to highly doped substrate 224.Optional buffer layer 226 can be between substrate and compensating basin.Resilient coating has the conduction type identical with substrate, but has than the doping of this substrate lower concentration.The doping of the above resilient coating can change in the vertical direction.For example, Fig. 2 b illustrates stepping doped level in described resilient coating.For example, described resilient coating can comprise multiple sublayers, and as the first sublayer (resilient coating 1) and the second sublayer (resilient coating 2), and the doping of described the second sublayer can be higher than the doping of described the first sublayer.Again for example, the doping that Fig. 2 c illustrates described n district (n post) 234 is along progressively increasing from described insulation system 240 to the direction of described resilient coating 226 and/or increasing gradually.According to an embodiment (not shown in Fig. 2 a-2c), the doping of the doping of n district (n post) and/or p district (p post) can be along have one or more local doping maximums and one or more local doping minimum from described insulation system 240 to the direction of described resilient coating 226.
Each source electrode contact is electrically connected by described metal layer 210, and described metal layer builds public source pad at the end face of chip.Unit grid 214 is connected to build and contact with the public grid of metallization at end face by polysilicon.And two electrodes (for source electrode, another is for grid) therefore, with identical or different metallization are arranged on device end face and by for example Si oxide passivation layer or silicon nitride passivation layer or be isolated from each other by both simultaneously.Drain electrode contact is structured in the back side of device and is covered by the metallization 228 of super junction device.
In super junction transistors, due to suitable work function and manufacturability thereof for n channel mosfet, the preferred material of gate electrode is the polysilicon of n doping.For example, but the series resistance of polysilicon is subject to the solubility restriction of dopant material (phosphorus), the layer that is therefore 500nm for thickness, square resistance can not drop to 10 Ω
□below.
Meanwhile, the super junction transistors that has a strip element can not have connection between substantially parallel electrode.Therefore, the grid potential of the parallel units of super junction transistors may be different because of some little (unintentional) architectural differences between internal feedback, the unit of drain electrode or temperature gradient in the chip example of several possibilities (only for).Thus, in the case of between neighboring gates polysilicon strip not for example, low ohm connection by low ohm material (metal wire), even the switch behavior of adjacent cells may be also different.
The problem that inhomogeneous switch brings increases along with the chip area of super junction transistors.
In the utility model, disclosed structure is for being greater than 20mm
2, or be greater than 35mm
2, or be greater than 50mm
2the chip area compared with large even more important.
According to the utility model, for the best gate charge of super junction transistors, the width w of the gate electrode shown in Fig. 2 a-2c should not exceed about 50% of cell pitch p.In one embodiment, the width w of gate electrode is less than 1/2 of cell pitch p.In another embodiment, the width of gate electrode is less than 1/3 of cell pitch p.
The front metal of super junction transistors has the conductance more much higher than gate electrode.Therefore, in this utility model, front metal utilize structuring part that low ohm connection (for example metal connection) is connected to gate pads for repeatedly contacting gate electrode.
In addition,, in order to provide uniform grid voltage distribute and therefore uniform unit switch behavior is provided, can between gate electrode structure and metal gates finger piece, use electrical connection.
Fig. 3 is schematically illustrated according to the sectional view of the different embodiment that electrically contact between the gate metallization in super junction transistors of the present utility model and gate electrode structure.
In Fig. 3, contact hole 328 is formed through the gate-dielectric 340 between gate metallization 320 and gate electrode 314.Multiple different electric conducting material is filled in contact hole 328 to form plug structure, and this plug structure is electrically connected the gate metallization of super junction transistors 320 and gate electrode 314.
According to an embodiment, gate metallization 320 can comprise one or more in aluminium, copper and silicon.
According to an embodiment, contact hole 328 is filled with polysilicon layer to form plug structure.Deposition after, for example by shelter or exposed etching or by CMP(chemico-mechanical polishing) from unwanted region, remove polysilicon.When deposition polysilicon by doping in place, or after deposition or in recessed doped polycrystalline silicon afterwards.
According to another embodiment, contact hole 328 is coated with barrier material.This barrier material can comprise conducting ceramic material, for example titanium nitride, tantalum nitride etc.Then the remainder of contact hole 328 has for example been filled tungsten by depositing operation, to form plug structure.
According to an embodiment, the thickness of the tungsten depositing is at least half of the width of contact hole 328.Unnecessary tungsten can be for example by eat-backing and/or CMP removes from the surface of super junction transistors, as shown in Figure 3.
According to an embodiment, for example patterning tungsten independently during the patterning of remaining front-side metallization layer.In this case, tungsten layer may reside between remaining front-side metallization layer and gate-dielectric.
According to an embodiment, before deposited barrier material, at least at the bottom of contact hole 328 plated metal, for example titanium, and this metal is annealed, thus form Metal-silicides Contact district.
According to an embodiment (not shown in Fig. 3), plug structure can around the upper surface of dielectric 340 to be sunken into.
According to an embodiment (not shown in Fig. 3), plug structure can not filled up completely, but can have the space that is filled with one or more different materials.These materials can comprise air, vacuum, silica, silicon nitride, gate metal etc.
According to an embodiment, super junction transistors can also build with the cellular construction that gate electrode is arranged in groove.In this case, the gate electrode in groove can be touched by plug structure as described above.
According to an embodiment, the gate electrode of super junction transistors can directly be contacted from gate pads by plug structure as described above.
According to an embodiment, source metallization layer and gate metallization can be positioned on different metal layers, and it is in vertical direction by such as SiO
2insulator isolation.This embodiment contributes to minimize the region such as gate pads and gate fingers, and these regions can not contribute to electric current.Use such layout to contribute to obtain the lower conduction resistance of device.
In the description of carrying out about Fig. 2 a-2c and Fig. 3 in the above, in order to give prominence to better the utility model, therefore only improvement structure of the present utility model be have been described in detail, well known to a person skilled in the art some semiconductor device structures and only summarize or even omitted.In addition, the formation of the semiconductor device structure in the utility model all can adopt semiconductor fabrication process well known to those skilled in the art to complete, and repeats no more here.
Although describe the utility model and advantage thereof in detail by exemplary embodiment above, but those skilled in the art are to be understood that, in the case of not departing from the spirit and scope of the present utility model that are defined by the following claims, can carry out multiple replacement and modification to the utility model.
Claims (19)
1. a semiconductor device, it comprises:
Compensating basin, it comprises p district and n district;
Be positioned at the transistor unit that comprises gate electrode on described compensating basin, described gate electrode is surrounded by gate-dielectric; And
Be arranged in the gate metallization on gate-dielectric,
It is characterized in that, described semiconductor device also comprises the connector of the contact hole that fills up the formation of the gate-dielectric through gate electrode and gate metallization, so that electric connection grid electrode and gate metallization.
2. semiconductor device according to claim 1, is characterized in that, described connector is formed by polysilicon.
3. semiconductor device according to claim 1, is characterized in that, described connector is formed by barrier material layer and the tungsten layer on barrier material layer.
4. semiconductor device according to claim 3, is characterized in that, in certain embodiments, described barrier material layer comprises conducting ceramic material.
5. semiconductor device according to claim 4, is characterized in that, described conducting ceramic material comprises one of titanium nitride and tantalum nitride.
6. semiconductor device according to claim 3, is characterized in that, the thickness of described tungsten layer is at least half of the width of described contact hole.
7. semiconductor device according to claim 3, is characterized in that, described semiconductor device also comprises the metal silicide layer between barrier material layer and contact hole bottom.
8. semiconductor device according to claim 1, is characterized in that, described connector is recessed below the upper surface of gate-dielectric.
9. semiconductor device according to claim 1, is characterized in that, described connector has the space of having filled different materials.
10. semiconductor device according to claim 9, is characterized in that, described different materials comprises in air, vacuum, silica, silicon nitride and gate metal.
11. semiconductor device according to claim 1, is characterized in that, described gate electrode is disposed in groove.
12. semiconductor device according to claim 1, is characterized in that, described gate electrode has 1/2 the width that is less than transistor unit pitch.
13. semiconductor device according to claim 1, is characterized in that, described gate electrode has 1/3 the width that is less than transistor unit pitch.
14. semiconductor device according to claim 1, is characterized in that, described semiconductor device also comprises substrate and the resilient coating between substrate and compensating basin.
15. semiconductor device according to claim 14, is characterized in that, described resilient coating is greater than the doping content on its top in the doping content of its underpart.
16. semiconductor device according to claim 1, is characterized in that, described n district is greater than the doping content on its top in the doping content of its underpart.
17. semiconductor device according to claim 1, is characterized in that, described transistor unit also comprises the tagma that is arranged in compensating basin and the source electrode that embeds described tagma.
18. semiconductor device according to claim 1, is characterized in that, described semiconductor device is super junction device.
19. semiconductor device according to claim 1, is characterized in that, described gate metallization comprises in aluminium, copper and silicon.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320675635.2U CN203910785U (en) | 2013-10-30 | 2013-10-30 | Semiconductor device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320675635.2U CN203910785U (en) | 2013-10-30 | 2013-10-30 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203910785U true CN203910785U (en) | 2014-10-29 |
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ID=51785039
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| CN201320675635.2U Expired - Lifetime CN203910785U (en) | 2013-10-30 | 2013-10-30 | Semiconductor device |
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| Country | Link |
|---|---|
| CN (1) | CN203910785U (en) |
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2013
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