CN203894413U - Satellite navigation signal processor resisting narrow-band interference based on FPGA - Google Patents
Satellite navigation signal processor resisting narrow-band interference based on FPGA Download PDFInfo
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- CN203894413U CN203894413U CN201320823919.1U CN201320823919U CN203894413U CN 203894413 U CN203894413 U CN 203894413U CN 201320823919 U CN201320823919 U CN 201320823919U CN 203894413 U CN203894413 U CN 203894413U
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- 238000004364 calculation method Methods 0.000 claims abstract description 15
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- 230000011218 segmentation Effects 0.000 claims description 13
- 230000003993 interaction Effects 0.000 claims description 10
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- 238000000034 method Methods 0.000 abstract description 3
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- 230000009286 beneficial effect Effects 0.000 abstract description 2
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- 230000037431 insertion Effects 0.000 abstract description 2
- 230000003595 spectral effect Effects 0.000 abstract description 2
- 230000002401 inhibitory effect Effects 0.000 abstract 2
- 230000000052 comparative effect Effects 0.000 abstract 1
- 238000001514 detection method Methods 0.000 abstract 1
- 241001269238 Data Species 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
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- 238000010168 coupling process Methods 0.000 description 1
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- 238000005516 engineering process Methods 0.000 description 1
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- 229910052627 muscovite Inorganic materials 0.000 description 1
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Abstract
The utility model discloses a satellite navigation signal processor resisting narrow-band interference based on an FPGA, and relates to the technical field of communication. The processor comprises a clock domain crossing buffering input module, a windowing circuit, an FFT module, a frequency domain filter, an IFFT module, a delayer, an overlap-adder, and a reverse windowing circuit. The frequency domain filter comprises a power calculation circuit, a segmented accumulative circuit, a threshold generating circuit, and a comparative amplitude-limiting circuit. The beneficial effects of the utility model lie in that the processor carried out the FIR filtering of intermediate frequency data, and converts the data from the time domain to the frequency domain; the detection of an interference signal is achieved through a self-adaption threshold algorithm, and the processor processes spectral lines exceeding the threshold; finally, the processor carries out delay overlap-adding and reverse windowing, thereby completing the accurate reconstruction of an original signal, and achieving the purpose of inhibiting narrow-band interference; the processor is excellent in performance of inhibiting narrow-band interference, is lower in insertion loss, is small in resource occupation, and is suitable for a satellite navigation receiver of an anti-interference type.
Description
Technical field
The utility model relates to communication technical field, particularly the anti-arrowband of a kind of satellite navigation signals Interaction Handler.
Background technology
GLONASS (Global Navigation Satellite System) (Global Navigation Satellite System, GNSS) is the satellite-based radio navigation system taking artificial earth satellite as guidance station.At present, the existing GLONASS (Global Navigation Satellite System) in the whole world comprises the GPS of the U.S., Muscovite GLONASS, the Galileo of European Union, and the Big Dipper of China (BeiDou/Compass is called for short BD).
Because global navigational satellite is generally all positioned at middle orbit, apart from approximately 20000 kilometers, ground, its signal transmission power is limited, and very faint while arriving ground, even at open field, received power is conventionally also than the low 20～30dB of neighbourhood noise.And carrier wave frequency range of global navigational satellite signal, spread-spectrum code rate, modulation system etc. are all full disclosures.Therefore navigation signal is very easily subject to intentional or unintentional interference on ground and terrestrial space, and in the time that interference strength exceedes the anti-jamming margin that system self spreading gain brings, navigation and positioning accuracy will sharply worsen, until the complete losing lock of receiver.
In general, undesired signal expects that according to its bandwidth the size of the GNSS signal bandwidth receiving can be divided into broadband and arrowband disturbs relatively.Arrowband disturbs for GNSS system, very common, and harm is very large.
Utility model content
The purpose of this utility model is: for the problem of above-mentioned existence, provide one to take resource few, interference free performance is superior, and the FPGA realization that utilizes that is easy to realize is carried out anti-arrowband Interaction Handler to satellite navigation signals.
The purpose of this utility model realizes by following technical proposals: the anti-arrowband of a kind of satellite navigation signals based on FPGA Interaction Handler, comprise cross clock domain buffering load module, the first windowing circuit, the one FFT module, the one IFFT module, the first delayer, the second delayer, the second windowing circuit, the 2nd FFT module, the 2nd IFFT module, overlap-add device, anti-windowing circuit, the first frequency domain filter and the second frequency domain filter, cross clock domain buffering load module, the first windowing circuit, the one FFT module, the first frequency domain filter, the one IFFT module, the first delayer, overlap-add device, anti-windowing circuit is linked in sequence, cross clock domain buffering load module is connected with the second delayer, the second delayer, the second windowing circuit, the 2nd FFT module, the second frequency domain filter, the 2nd IFFT sequence of modules connects, the 2nd IFFT module is connected with overlap-add device.
Further, the first frequency domain filter and the second frequency domain filter comprise that power calculation circuit, segmentation summation circuit, thresholding produce relatively relatively amplitude limiter circuit of amplitude limiter circuit, second of circuit, first, relatively amplitude limiter circuit, segmentation summation circuit, second compare amplitude limiter circuit and are connected power calculation circuit with first respectively, segmentation summation circuit produces circuit with thresholding and is connected, and thresholding generation circuit compares amplitude limiter circuit with the first comparison amplitude limiter circuit, second respectively and is connected.
Further, the first windowing circuit and the second windowing circuit all include FIR wave filter.
Further, cross clock domain buffering load module is made up of 1 I/O Address controller and 1 two-port RAM, and I/O Address controller is connected with two-port RAM.
Further, a FFT module and the 2nd FFT module all comprise 1 256 FFT and 1 FFT time schedule controller.
The beneficial effects of the utility model: the utility model is by carrying out FIR filtering to intermediate frequency data, by 256 FFT, data are transformed into frequency domain, undesired signal is detected by adaptive threshold algorithm at frequency domain, the spectral line that exceedes thresholding is processed simultaneously, finally by postponing overlap-add and anti-windowing process, complete the accurate reconstruct to original signal, thereby reach, arrowband is disturbed to the object suppressing.Compared with traditional processor, there is superior Suppression of narrow band interference performance and less insertion loss, take resource few, be applicable to the satellite navigation receiver of anti-interference type.
Brief description of the drawings
Fig. 1 is structural representation of the present utility model.
Fig. 2 is the work schematic diagram of the first frequency domain filter 4 and the second frequency domain filter 10.
In Fig. 1,1 is cross clock domain buffering load module, and 2 is the first windowing circuit, 3 is a FFT module, and 4 is the first frequency domain filter, and 5 is an IFFT module, 6 is the first delayer, 7 is the second delayer, and 8 is the second windowing circuit, and 9 is the 2nd FFT module, 10 is the second frequency domain filter, 11 is the 2nd IFFT module, and 12 is overlapping summitor, and 13 is anti-windowing circuit.
In Fig. 2,401 is power calculation circuit, and 402 is segmentation summation circuit, and 403 is that thresholding produces circuit, and 404 is the first comparison amplitude limiter circuit, and 405 is the second comparison amplitude limiter circuit.
Embodiment
Below in conjunction with specific embodiments and the drawings, the utility model is further described.
Embodiment: as shown in Figure 1, the anti-arrowband of a kind of satellite navigation signals based on FPGA Interaction Handler, comprise cross clock domain buffering load module 1, the first windowing circuit 2, FFT (Fast Fourier Transform (FFT)) module 3, the first frequency domain filter 4, IFFT (inverse fast Fourier transform) module 5, the first delayers 6, overlap-add device 12, anti-windowing circuit 13, the second delayer 7, the second windowing circuit 8, the 2nd FFT module 9, the second frequency domain filter 10, the 2nd IFFT module 11.Wherein, cross clock domain buffering load module 1, the first windowing circuit 2, a FFT module 3, the first frequency domain filter 4, an IFFT module 5, the first delayer 6, overlap-add device 12, anti-windowing circuit 13 are linked in sequence, the second delayer 7 is connected with cross clock domain buffering load module 1, the second delayer 7, the second windowing circuit 8, the 2nd FFT module 9, the second frequency domain filter 10, the 2nd IFFT module 11 are linked in sequence, and the 2nd IFFT module 11 is connected with overlap-add device 12.
Cross clock domain buffering load module 1 is made up of 1 I/O Address controller and 1 two-port RAM, and I/O Address controller is connected with two-port RAM.I/O Address controller is read address and write address for generation of two-port RAM, this I/O Address controller can carry out address space distribution according to the speed of the speed of input data and output data, prevent that the read-write operation of two-port RAM is in same sector address space, two-port RAM is used for as data buffer storage with the speed difference between coupling input and output.
The first windowing circuit 2 and the second windowing circuit 8 all include FIR wave filter, for data are carried out to low-pass filtering, and filtering high frequency band external noise signal.The one FFT module 3 and the 2nd FFT module 9 all comprise 1 256 FFT and a FFT time schedule controller, and major function is that filtered time domain data is transformed into frequency domain.
The first frequency domain filter 4 and the second frequency domain filter 10 all comprise 402,1 thresholding of 401,1 segmentation summation circuit of 1 power calculation circuit and produce relatively relatively amplitude limiter circuit 405 of amplitude limiter circuit 404 and second of circuit 403 and first.I road signal is input to respectively relatively amplitude limiter circuit 404 of power calculation circuit 401 and first, Q road signal is input to respectively relatively amplitude limiter circuit 405 of power calculation circuit 401 and second, power calculation circuit 401 output terminals respectively with segmentation summation circuit 402, first compares amplitude limiter circuit 404, second compares amplitude limiter circuit 405 connects, segmentation summation circuit 402 output terminals produce circuit 403 with thresholding and are connected, thresholding produces circuit 403 and compares amplitude limiter circuit 404 with first respectively, second compares amplitude limiter circuit 405 connects, I road signal is from the first relatively amplitude limiter circuit 404 output terminal outputs, Q road signal is from the second relatively amplitude limiter circuit 405 output terminal outputs.Power calculation circuit 401 calculates I road, the Q road signal intensity of input, result of calculation sends segmentation summation circuit 402, relatively amplitude limiter circuit 405 of the first comparison amplitude limiter circuit 404 and second to simultaneously, and segmentation summation circuit 402 outputs to thresholding and produces circuit 403 after 256 power datas are added up.Thresholding produces circuit 403 and automatically generates threshold value according to multistage performance number, add up owing to having adopted signal power, threshold value can be adjusted automatically according to signal intensity, this threshold value is sent to first simultaneously and compares amplitude limiter circuit 404, second compares amplitude limiter circuit 405, result after the signal power value of the first comparison amplitude limiter circuit 404 and the current input of the second comparison amplitude limiter circuit 405 use and threshold value compare, input signal is processed, judge according to the multiple that exceedes threshold value, multiple is higher, decay to signal is stronger, the first comparison amplitude limiter circuit 404 and second relatively amplitude limiter circuit 405 is to be all shifted and to be realized the decay to strong signal by data.
Power calculation circuit 401 can carry out segmented power calculating to the signal of input, and result of calculation is added up by segmentation summation circuit 402.Thresholding produces repeatedly segmented power result of calculation of circuit 403 bases, sets automatically interference threshold value and sends the first comparison amplitude limiter circuit 404, the second comparison amplitude limiter circuit 405 to.Relatively amplitude limiter circuit produces by the data of input and current thresholding the threshold value that circuit 403 produces and compares, to exceed the input data of thresholding carry out notch process after output, thereby the effective filtering of realization to narrow-band interference signal.
The one IFFT module 5 and the 2nd IFFT module 11, be respectively the inverse operation of a FFT module 3 and the 2nd FFT module 9 functions, for frequency domain data after filtering is reduced into time domain data.The first delayer 6 and the second delayer 7 are for realizing 50% delay to block data.Overlap-add device 12 is for realizing the addition of the anti-interference data of two-way.Anti-windowing circuit 13, for overlapping summitor 12 data after treatment are carried out to anti-windowing computing, is realized the accurate reconstruct to original signal.
The foregoing is only preferred embodiment of the present utility model; not in order to limit the utility model; all any amendments of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.
Claims (5)
1. the anti-arrowband of the satellite navigation signals based on a FPGA Interaction Handler, it is characterized in that: comprise cross clock domain buffering load module, the first windowing circuit, the one FFT module, the one IFFT module, the first delayer, the second delayer, the second windowing circuit, the 2nd FFT module, the 2nd IFFT module, overlap-add device, anti-windowing circuit, the first frequency domain filter and the second frequency domain filter, described cross clock domain buffering load module, the first windowing circuit, the one FFT module, the first frequency domain filter, the one IFFT module, the first delayer, overlap-add device, anti-windowing circuit is linked in sequence, described cross clock domain buffering load module is connected with the second delayer, described the second delayer, the second windowing circuit, the 2nd FFT module, the second frequency domain filter, the 2nd IFFT sequence of modules connects, the 2nd IFFT module is connected with overlap-add device.
2. the anti-arrowband of the satellite navigation signals based on FPGA as claimed in claim 1 Interaction Handler, it is characterized in that: described the first frequency domain filter and the second frequency domain filter comprise power calculation circuit, segmentation summation circuit, thresholding produces circuit, first compares amplitude limiter circuit, second compares amplitude limiter circuit, described power calculation circuit compares amplitude limiter circuit with first respectively, segmentation summation circuit, the second relatively amplitude limiter circuit connection, segmentation summation circuit produces circuit with thresholding and is connected, thresholding produces circuit and compares amplitude limiter circuit with first respectively, the second relatively amplitude limiter circuit connection.
3. the anti-arrowband of the satellite navigation signals based on FPGA as claimed in claim 1 Interaction Handler, is characterized in that: described the first windowing circuit and the second windowing circuit all include FIR wave filter.
4. the anti-arrowband of the satellite navigation signals based on FPGA as claimed in claim 1 Interaction Handler, it is characterized in that: described cross clock domain buffering load module is made up of 1 I/O Address controller and 1 two-port RAM, and described I/O Address controller is connected with two-port RAM.
5. the anti-arrowband of the satellite navigation signals based on FPGA as claimed in claim 1 Interaction Handler, is characterized in that: a described FFT module and the 2nd FFT module all comprise 1 256 FFT and 1 FFT time schedule controller.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320823919.1U CN203894413U (en) | 2013-12-16 | 2013-12-16 | Satellite navigation signal processor resisting narrow-band interference based on FPGA |
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| CN201320823919.1U CN203894413U (en) | 2013-12-16 | 2013-12-16 | Satellite navigation signal processor resisting narrow-band interference based on FPGA |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105301607A (en) * | 2015-11-20 | 2016-02-03 | 武汉梦芯科技有限公司 | Device, system and method for narrowband interference suppression of single-frequency and multi-frequency GNSS signals |
| CN105911565A (en) * | 2016-04-08 | 2016-08-31 | 中国科学院微电子研究所 | Method and device for inhibiting narrowband interference |
| CN108551351A (en) * | 2018-04-13 | 2018-09-18 | 中国科学院微电子研究所 | Inhibit the method and device of narrowband interference |
| CN111812682A (en) * | 2020-07-24 | 2020-10-23 | 华力智芯(成都)集成电路有限公司 | Narrow-band interference resistant circuit |
| CN112698363A (en) * | 2020-12-29 | 2021-04-23 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
| CN113391122A (en) * | 2021-06-09 | 2021-09-14 | 中电科思仪科技股份有限公司 | Method for improving selectivity of frequency spectrum monitoring channel |
| CN114362837A (en) * | 2022-01-10 | 2022-04-15 | 中国电子科技集团公司第五十四研究所 | Spread spectrum satellite signal narrowband interference self-adaption eliminating device |
| CN115865572A (en) * | 2022-11-10 | 2023-03-28 | 中国电子科技集团公司第十研究所 | High-speed parallel receiver data reconstruction system and method |
-
2013
- 2013-12-16 CN CN201320823919.1U patent/CN203894413U/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105301607A (en) * | 2015-11-20 | 2016-02-03 | 武汉梦芯科技有限公司 | Device, system and method for narrowband interference suppression of single-frequency and multi-frequency GNSS signals |
| CN105911565A (en) * | 2016-04-08 | 2016-08-31 | 中国科学院微电子研究所 | Method and device for inhibiting narrowband interference |
| CN105911565B (en) * | 2016-04-08 | 2018-12-21 | 中国科学院微电子研究所 | A kind of method and device inhibiting narrowband interference |
| CN108551351A (en) * | 2018-04-13 | 2018-09-18 | 中国科学院微电子研究所 | Inhibit the method and device of narrowband interference |
| CN108551351B (en) * | 2018-04-13 | 2020-08-04 | 中国科学院微电子研究所 | Method and device for suppressing narrow-band interference |
| CN111812682A (en) * | 2020-07-24 | 2020-10-23 | 华力智芯(成都)集成电路有限公司 | Narrow-band interference resistant circuit |
| CN112698363A (en) * | 2020-12-29 | 2021-04-23 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
| CN112698363B (en) * | 2020-12-29 | 2024-04-16 | 成都国星通信有限公司 | High-precision data acquisition method and acquisition circuit for Beidou anti-interference antenna |
| CN113391122A (en) * | 2021-06-09 | 2021-09-14 | 中电科思仪科技股份有限公司 | Method for improving selectivity of frequency spectrum monitoring channel |
| CN114362837A (en) * | 2022-01-10 | 2022-04-15 | 中国电子科技集团公司第五十四研究所 | Spread spectrum satellite signal narrowband interference self-adaption eliminating device |
| CN114362837B (en) * | 2022-01-10 | 2023-12-29 | 中国电子科技集团公司第五十四研究所 | Narrow-band interference self-adaptive elimination device for spread spectrum satellite signals |
| CN115865572A (en) * | 2022-11-10 | 2023-03-28 | 中国电子科技集团公司第十研究所 | High-speed parallel receiver data reconstruction system and method |
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Granted publication date: 20141022 |