CN203858578U - Self-adaption access control system of multi-channel input/output device - Google Patents
Self-adaption access control system of multi-channel input/output device Download PDFInfo
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- CN203858578U CN203858578U CN201420289405.7U CN201420289405U CN203858578U CN 203858578 U CN203858578 U CN 203858578U CN 201420289405 U CN201420289405 U CN 201420289405U CN 203858578 U CN203858578 U CN 203858578U
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Abstract
The utility model discloses a self-adaption access control system of a multi-channel input/output device. The self-adaption access control system comprises a first channel interface to a Nth channel interface, series/parallel conversion components, a register, a base address and length counter, an address selection component, a data selection component, an arbitration controller, a buffer memory and a clock generator, wherein the N is a positive integer which is larger than 1, and the series/parallel conversion components correspond to the first channel interface to a Nth channel interface. By means of the self-adaption access control system, the problems of data processing speed and buffer are well solved, concurrent work of a plurality of input/output devices of different communication speeds and different frame lengths is achieved as well, meanwhile influence on the control speed caused by the fact that software participates in serial communication, and work efficiency of the system is improved.
Description
Technical field
The utility model relates to input-output apparatus technical field, relates in particular to a kind of hyperchannel input-output apparatus adaptive access control system.
Background technology
Internet of Things gets up based on internet development, extension and the expansion of internet, specifically refer to by information sensing equipment such as radio-frequency (RF) identification, infrared inductor, laser scanners, by the agreement of agreement, realization any time, any place, any object carry out message exchange and communicate by letter, with a kind of network of realizing intellectuality identification, locating, follow the tracks of, monitor and manage.Along with the arrival in Internet of Things epoch, the input-output apparatus kind being applied to and quantity also sharply increase, but the development of traditional I/O (I/O) equipment is but relatively slow, can not agree with the needs of Internet of Things high speed development, how reliably efficiently the input-output apparatus of multiple different performance to be connected in corresponding system, and handle communication speed and the buffer size of distinct interface data well, and eliminate software and participate in the impact of serial communication on control rate, urgently to be resolved hurrily.
Utility model content
The purpose of this utility model is, by a kind of hyperchannel input-output apparatus adaptive access control system, to solve the problem that above background technology part is mentioned.
For reaching this object, the utility model by the following technical solutions:
A kind of hyperchannel input-output apparatus adaptive access control system, it comprises that first to N channel interface, N is greater than 1 positive integer, serial/parallel converting member, register, base address and the length counter corresponding with each described channel interface, address selection parts, data selection parts, arbitration controller, memory buffer, and clock generator; Wherein, described serial/parallel converting member one end interface channel interface, the other end connects register, connection base address, described address addressing parts one end and length counter, the other end connects arbitration controller, memory buffer, described data selection parts one end connects register, and the other end connects arbitration controller, memory buffer, and described clock generator connects arbitration controller.
Especially, described register comprises data receiver register and data transmitter register.
Especially, described hyperchannel input-output apparatus adaptive access control system comprises the first to the 8th channel interface.
The utility model provides hyperchannel input-output apparatus adaptive access control system in the upper design of a field programmable gate array (FPGA), the data transmit-receive of every paths interface, and the processing of its internal data, effect, buffering first in first out (FIFO), arbitration is controlled and data-carrier store is directly accessed (DMA) all by hardware circuit concurrent completing automatically, need not participate in by software, processing speed and the buffer problem of data are so not only solved well, and realize the concurrent work of multiple different input-output apparatus of different communication speed and different frame length, also eliminated software and participated in the impact of serial communication on control rate simultaneously, improve the work efficiency of system.
Brief description of the drawings
The hyperchannel input-output apparatus adaptive access control system structural drawing that Fig. 1 provides for the utility model embodiment.
Embodiment
Below in conjunction with drawings and Examples, the utility model is described in further detail.Be understandable that, specific embodiment described herein is only for explaining the utility model, but not to restriction of the present utility model.It also should be noted that, for convenience of description, in accompanying drawing, only show the part relevant to the utility model but not full content.
Please refer to shown in Fig. 1 the hyperchannel input-output apparatus adaptive access control system structural drawing that Fig. 1 provides for the utility model embodiment.
In the present embodiment, hyperchannel input-output apparatus adaptive access control system specifically comprises: first to N channel interface, N is greater than 1 positive integer, the serial/parallel converting member corresponding with each described channel interface and parallel/serial converting member, register, base address and length counter, address selection parts, data selection parts, arbitration controller, memory buffer, and clock generator.
Described serial/parallel converting member one end interface channel interface, the other end connects register, connection base address, described address addressing parts one end and length counter, the other end connects arbitration controller, memory buffer, described data selection parts one end connects register, the other end connects arbitration controller, memory buffer, and described clock generator connects arbitration controller.
In the present embodiment, described register comprises data receiver register and data transmitter register.Hyperchannel input-output apparatus adaptive access control system comprises the first to the 8th channel interface, be that N gets 8, the first to the 8th channel interface provides 8 paths altogether, receives and dispatches work when can supporting 8 road peripheral channel simultaneously, and the speed of each interface and frame length can be different.
Each path has a corresponding base address and length counter, current length is exactly the address that each path is read and write memory buffer, address selection parts are exactly according to arbitration control logic signal from first to the 8th path of arbitration controller output at present, in 16 request sources, select a wherein road, as the operation address of current memory buffer.Same, each path interface has a corresponding register, and register comprises data receiver register and data transmitter register, receives in this way, and its content is write buffering memory in time; Send in this way, its content must read from memory buffer; Data selection parts are exactly from 8 circuit-switched data receiving registers and transmitter register, to select a wherein road according to the arbitration control logic signal of arbitration controller output at present, as current memory buffer behaviour's data.
The effect of arbitration controller is: 8 paths, read-write separately, totally 16 request sources, they can initiate operation requests to memory buffer simultaneously, but memory buffer can only be selected an operation requests, this just need to adopt arbitration controller, and it selects a request from effective request according to control algolithm.Selected channel interface, current address selection parts and data selection parts are also for it takies.
The technical solution of the utility model designs on a field programmable gate array, the data transmit-receive of every paths interface, and the processing of its internal data, effect, buffering FIFO, arbitration control and data DMA are by hardware circuit concurrent completing automatically, need not participate in by software, processing speed and the buffer problem of data are so not only solved well, and realize the concurrent work of multiple different input-output apparatus of different communication speed and different frame length, also eliminated software and participated in the impact of serial communication on control rate simultaneously, improve the work efficiency of system.The utility model inside is provided with a large amount of bufferings, access arbitration steering logic, and high speed input/output interface frequency detection circuit, can detect the speed of respective channel interface automatically, automatically configures corresponding communication speed.In addition, the utility model can be identified automatically according to synchronizing information and data message the interface communication speed of input-output apparatus, and the length of frame, supports parity checking, CRC check, and built-in multichannel buffering FIFO, supports the concurrent transmitting-receiving work of hyperchannel.
Note, above are only preferred embodiment of the present utility model and institute's application technology principle.Skilled person in the art will appreciate that the utility model is not limited to specific embodiment described here, can carry out for a person skilled in the art various obvious variations, readjust and substitute and can not depart from protection domain of the present utility model.Therefore, although the utility model is described in further detail by above embodiment, but the utility model is not limited only to above embodiment, in the situation that not departing from the utility model design, can also comprise more other equivalent embodiment, and scope of the present utility model is determined by appended claim scope.
Claims (3)
1. a hyperchannel input-output apparatus adaptive access control system, it is characterized in that, comprise that first to N channel interface, N is greater than 1 positive integer, serial/parallel converting member, register, base address and the length counter corresponding with each described channel interface, address selection parts, data selection parts, arbitration controller, memory buffer, and clock generator; Wherein, described serial/parallel converting member one end interface channel interface, the other end connects register, connection base address, described address addressing parts one end and length counter, the other end connects arbitration controller, memory buffer, described data selection parts one end connects register, and the other end connects arbitration controller, memory buffer, and described clock generator connects arbitration controller.
2. hyperchannel input-output apparatus adaptive access control system according to claim 1, is characterized in that, described register comprises data receiver register and data transmitter register.
3. hyperchannel input-output apparatus adaptive access control system according to claim 2, is characterized in that, this system comprises the first to the 8th channel interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420289405.7U CN203858578U (en) | 2014-05-30 | 2014-05-30 | Self-adaption access control system of multi-channel input/output device |
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| CN201420289405.7U CN203858578U (en) | 2014-05-30 | 2014-05-30 | Self-adaption access control system of multi-channel input/output device |
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| CN203858578U true CN203858578U (en) | 2014-10-01 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110083461B (en) * | 2019-03-29 | 2021-09-24 | 郑州信大捷安信息技术股份有限公司 | Multitasking system and method based on FPGA |
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2014
- 2014-05-30 CN CN201420289405.7U patent/CN203858578U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110083461B (en) * | 2019-03-29 | 2021-09-24 | 郑州信大捷安信息技术股份有限公司 | Multitasking system and method based on FPGA |
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