CN203850001U - Power down protection circuit of static memory - Google Patents
Power down protection circuit of static memory Download PDFInfo
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- CN203850001U CN203850001U CN201420158807.3U CN201420158807U CN203850001U CN 203850001 U CN203850001 U CN 203850001U CN 201420158807 U CN201420158807 U CN 201420158807U CN 203850001 U CN203850001 U CN 203850001U
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- selection signal
- chip selection
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Abstract
The utility model provides a power down protection circuit of a static memory. The power down protection circuit comprises an energy storage unit and a chip selection signal control unit, wherein the energy storage unit is externally connected with an external power supply and is used for providing a reserve power supply under a power down condition; the chip selection signal control unit is connected with the energy storage unit and is used for transmitting a chip selection signal to the static memory; when the external power supply is normally connected, the chip selection signal control unit is used for transmitting a first control signal to a chip selection signal end of the static memory; the first control signal is used for enabling the static memory to be at a normal working state; at the power down state, the chip selection signal control unit is used for transmitting a second control signal to the chip selection signal end of the static memory; and the second control signal is used for enabling the static memory to be at an invalid state to keep storage information. Compared with the prior art, a power supply end and the chip selection signal end of the static memory are at a double-power-supply power supplying state; the control of the power down protection circuit is not needed and the switching of double power supplies is automatically finished; and the switching meets high-speed requirements.
Description
Technical field
The present invention relates to technical field of data storage, especially relate to a kind of static memory power-down protection circuit.
Background technology
In the various electronic equipments taking microprocessor as core, storer is conventional and requisite information recording device at present, and wherein static memory, with its distinctive performance, has special using value.As a kind of volatile storage, the integrality of protection information in the time of power down, low-power consumption, low cost, long-time power-down protection circuit are essential,
But existing conventional power-down protection circuit mode; still the many deficiencies that exist; circuit is preserved in the power down being made up of monitoring voltage and RC delay circuit, voltage changeover switch and sram chip of for example having authorized utility model power down to preserve employing in storer (patent No.: ZL96209364.5); although it is easy to use that its technical scheme has; data such as do not lose at the advantage; but in this technical scheme, do not consider the state of chip selection signal under power-down state, cause storer quiescent dissipation higher.
Therefore, current conventional power-down protection circuit mode, exists following not enough:
1, do not consider the state of chip selection signal under power-down state, cause storer quiescent dissipation higher, as described in patent [ZL96209364.5];
Although 2 have considered the slave mode of chip selection signal under power-down state, the job requirement while not handling normal condition well, is not suitable with high speed storing, has affected storage speed;
3, power-down protection circuit has complicated voltage detecting and control circuit, causes oneself power consumption larger;
4, use the battery power supply that backups, longevity, cost is high.
Summary of the invention
Object of the present invention is exactly in order to overcome the deficiencies in the prior art, and a kind of static memory power-down protection circuit is provided, and its concrete technical scheme is as follows:
A kind of static memory power-down protection circuit, comprising: energy-storage units, chip selection signal control module;
Described energy-storage units, connects external power source, for provide standby power supply under power down situation;
Described chip selection signal control module, connects energy-storage units, for chip selection signal is transferred to static store;
Connect when normal at external power source, described chip selection signal control module transmits the first control signal to static store chip selection signal end, and described the first control signal makes static store in normal operating conditions; In the time of power-down state, described chip selection signal control module transmits the second control signal to static store chip selection signal end, described the second control signal make static store in disarmed state to keep storage information.
Further, described energy-storage units also includes energy-storage travelling wave tube, in described energy-storage units, the anodic bonding external power source of diode D1, its negative electrode is connected with capacitor C 1, capacitor C 2, one end of resistance R 1 and the power input of static storage cell simultaneously, the other end of resistance R 1 is connected with the positive terminal of energy-storage travelling wave tube, and the negative pole end of described energy-storage travelling wave tube is connected with the other end of capacitor C 1, capacitor C 2 and ground connection.
Further, in described chip selection signal control module, two input ends of Sheffer stroke gate U1 connect outside chip selection signal simultaneously, its output terminal connects an input end of Sheffer stroke gate U2, another input end of described Sheffer stroke gate U2 connects external power source, described Sheffer stroke gate U2 output terminal connects the chip selection signal input end of static storage cell, the positive supply termination external power source of described Sheffer stroke gate U1, U2, the negative power end ground connection of Sheffer stroke gate U1, U2.
Further, described energy-storage travelling wave tube is super capacitor.
Compared with prior art, beneficial effect of the present invention is as follows: take into full account power down feature, make the power end, chip selection signal end of storer in dual power supply state, without power-fail detection circuit control, automatically complete the switching of dual power supply, and its switching meets high speed requirement; In the time of normal power supply, chip selection signal can be affected by external signal control store performance; Adopt high-speed door circuit, under power-down state, oneself power consumption is extremely low; When power-down state, by the control of chip selection signal, make storer there is very low quiescent dissipation.Its circuit is simple, with low cost simultaneously.
Brief description of the drawings
Fig. 1 is the theory diagram of embodiment of the present invention static memory power-down protection circuit.
Fig. 2 is the circuit diagram of embodiment of the present invention static memory power-down protection circuit.
Embodiment
In order to make object of the present invention, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein, only in order to explain the present invention, is not intended to limit the present invention.
As shown in Figure 1, a kind of power-down protection circuit, comprises energy-storage units 1, chip selection signal control module 2; Described energy-storage units 1, connects external power source, for provide standby power supply under power down situation; Described chip selection signal control module 2, connects energy-storage units 1, for chip selection signal is transferred to static store; Connect when normal at external power source, described chip selection signal control module transmits the first control signal to static store chip selection signal end, and described the first control signal makes static store in normal operating conditions; In the time of power-down state, described chip selection signal control module transmits the second control signal to static store chip selection signal end, described the second control signal make static store in disarmed state to keep storage information.
Wherein, as shown in Figure 2, in described energy-storage units, the anodic bonding external power source of diode D1, its negative electrode is connected with capacitor C 1, capacitor C 2, one end of resistance R 1 and the power input of static storage cell simultaneously, the other end of resistance R 1 is connected with the positive terminal of energy-storage travelling wave tube, and the negative pole end of described energy-storage travelling wave tube is connected with the other end of capacitor C 1, capacitor C 2 and ground connection.And in described chip selection signal control module, two input ends of Sheffer stroke gate U1 connect outside chip selection signal simultaneously, its output terminal connects an input end of Sheffer stroke gate U2, another input end of described Sheffer stroke gate U2 connects external power source, described Sheffer stroke gate U2 output terminal connects the chip selection signal input end of static storage cell, the positive supply termination external power source of described Sheffer stroke gate U1, U2, the negative power end ground connection of Sheffer stroke gate U1, U2.
Wherein: described energy-storage travelling wave tube is super capacitor, farad capacitor, can be also common large bulk capacitance.Thereby improve the life-span, avoid commonly using at present battery and backup power supply and cause longevity, cost is high.
Described Sheffer stroke gate U1～U2 is high-speed cmos integrated device, has the feature of high-speed low-power-consumption.
Described diode D1 can be low-leakage current switching diode.
Described resistance R 1 current-limiting resistance, the current limliting when energy-storage travelling wave tube is charged, generally can adopt little resistance resistance.
The principle of work of described power-down protection circuit is as follows: under normal operating conditions; diode D1 is in forward conduction; external power source 3.3V produces backup battery VBAT by diode D1; for static store, Sheffer stroke gate U1～U2 provide power supply; and provide charging for energy-storage travelling wave tube; resistance R 1 is little resistance current-limiting resistance, and capacitor C 1～C2 is filter capacitor.Outside chip selection signal CS is as the input of Sheffer stroke gate U1, after anti-phase, export an input end of Sheffer stroke gate U2 to, another input end of Sheffer stroke gate U2 is external power source 3.3V, and therefore outside chip selection signal CS can keep the sheet choosing of former phase control static store, realizes normal read-write capability.
And in the time there is no external power source 3.3V, circuit is in power down operations state, now diode D1 is in reverse operation state, there is very little leakage current, energy-storage travelling wave tube is by current-limiting resistance R1, release energy, produce the required power supply VBAT of circuit working, the working power of static store, Sheffer stroke gate U1～U2 is provided by VBAT.Under this state, an input end that meets external power source 3.3V of Sheffer stroke gate U2 is now power-down state, namely low level, therefore the output terminal of Sheffer stroke gate U2 is always high level, be connected to after static store, guarantee that the chip selection signal of static store is also high level always, allow static store in disarmed state, realize static store under extremely low power dissipation, keep storage information.
The above is only the preferred embodiment of the present invention; it should be pointed out that for those skilled in the art, under the premise without departing from the principles of the invention; any innovation and creation, amendment that is no more than connotation scope of the present invention, all falls into protection scope of the present invention.
Claims (4)
1. a static memory power-down protection circuit, is characterized in that, comprising: energy-storage units, chip selection signal control module;
Described energy-storage units, connects external power source, for provide standby power supply under power down situation;
Described chip selection signal control module, connects energy-storage units, for chip selection signal is transferred to static store;
Connect when normal at external power source, described chip selection signal control module transmits the first control signal to static store chip selection signal end, and described the first control signal makes static store in normal operating conditions; In the time of power-down state, described chip selection signal control module transmits the second control signal to static store chip selection signal end, described the second control signal make static store in disarmed state to keep storage information.
2. power-down protection circuit according to claim 1; it is characterized in that; described energy-storage units also includes energy-storage travelling wave tube; in described energy-storage units; the anodic bonding external power source of diode D1; its negative electrode is connected with capacitor C 1, capacitor C 2, one end of resistance R 1 and the power input of static storage cell simultaneously, and the other end of resistance R 1 is connected with the positive terminal of energy-storage travelling wave tube, and the negative pole end of described energy-storage travelling wave tube is connected with the other end of capacitor C 1, capacitor C 2 and ground connection.
3. power-down protection circuit according to claim 2; it is characterized in that; in described chip selection signal control module; two input ends of Sheffer stroke gate U1 connect outside chip selection signal simultaneously; its output terminal connects an input end of Sheffer stroke gate U2, and another input end of described Sheffer stroke gate U2 connects external power source, and described Sheffer stroke gate U2 output terminal connects the chip selection signal input end of static storage cell; the positive supply termination external power source of described Sheffer stroke gate U1, U2, the negative power end ground connection of Sheffer stroke gate U1, U2.
4. according to the power-down protection circuit described in claim 2 or 3, it is characterized in that, described energy-storage travelling wave tube is super capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420158807.3U CN203850001U (en) | 2014-04-03 | 2014-04-03 | Power down protection circuit of static memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420158807.3U CN203850001U (en) | 2014-04-03 | 2014-04-03 | Power down protection circuit of static memory |
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| Publication Number | Publication Date |
|---|---|
| CN203850001U true CN203850001U (en) | 2014-09-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420158807.3U Expired - Fee Related CN203850001U (en) | 2014-04-03 | 2014-04-03 | Power down protection circuit of static memory |
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| CN (1) | CN203850001U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107563229A (en) * | 2017-09-14 | 2018-01-09 | 苏州恒成芯兴电子技术有限公司 | A kind of power down protection module suitable for solid state hard disc |
-
2014
- 2014-04-03 CN CN201420158807.3U patent/CN203850001U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107563229A (en) * | 2017-09-14 | 2018-01-09 | 苏州恒成芯兴电子技术有限公司 | A kind of power down protection module suitable for solid state hard disc |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140924 Termination date: 20150403 |
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| EXPY | Termination of patent right or utility model |