CN203840332U - Short wave transmitting-receiving digital signal processing circuit based on CPCI bus - Google Patents
Short wave transmitting-receiving digital signal processing circuit based on CPCI bus Download PDFInfo
- Publication number
- CN203840332U CN203840332U CN201420009340.6U CN201420009340U CN203840332U CN 203840332 U CN203840332 U CN 203840332U CN 201420009340 U CN201420009340 U CN 201420009340U CN 203840332 U CN203840332 U CN 203840332U
- Authority
- CN
- China
- Prior art keywords
- chip
- digital signal
- signal processing
- cpci bus
- processing circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn - After Issue
Links
Landscapes
- Transceivers (AREA)
Abstract
The utility model discloses a short wave transmitting-receiving digital signal processing circuit based on a CPCI bus. The circuit comprises one FPGA chip and one DSP chip. The FPGA chip and the DSP chip are in communication connection. A CPCI bus interface is arranged on the DSP chip. The FPGA chip is used for achieving logic control inside the circuit, up/down conversion and filtering processing of multi-path signals and external interface control. The DSP chip is used for achieving processing of signals in a transmitting-receiving channel. A post selector, a power amplifier and an antenna on a transmitter end are controlled according to a transmitter control protocol. A preselector of a receiver is controlled according to a receiver control protocol. The short wave transmitting-receiving digital signal processing circuit based on the CPCI bus can have the transmitting and receiving functions combined in one circuit.
Description
Technical field
The utility model relates to a kind of shortwave transmitting-receiving digital signal processing circuit based on cpci bus, belongs to design of electronic circuits technology.
Background technology
The present invention for the transceiving integrated integrated equipment of shortwave designed.In short-wave large-power communication equipment in the past, sending and receiving signal/digital signal treatment circuit is separate, and volume is large, takes up room also many.Transmitting-receiving digital signal processing circuit input and output on market are all intermediate-freuqncy signals, need extra frequency mixing module; And on market, lack the shortwave digital signal processing module of zero intermediate frequency, cause the integrated level of equipment not high.Along with the application of high performance DSP and fpga chip, can realize the transmission circuit that integrated level is high; By ripe CPCI technology, can release the transmitting-receiving digital signal processing circuit that autgmentability is strong.
Utility model content
Goal of the invention: in order to overcome the deficiencies in the prior art, the utility model provides a kind of shortwave transmitting-receiving digital signal processing circuit based on cpci bus, and transmission-receiving function is synthesized on a circuit.
Technical scheme: for solving the problems of the technologies described above, the technical solution adopted in the utility model is:
Shortwave transmitting-receiving digital signal processing circuit based on cpci bus, comprises 1 fpga chip and 1 dsp chip, and between described fpga chip and dsp chip, communication connects, and is provided with cpci bus interface on described dsp chip.
As prior art, this transmitting-receiving digital signal processing circuit receives clock signal that foreign frequency combiner circuit provides, the intermediate-freuqncy signal of outside radio circuit is carried out demodulation process, audio signal is modulated into short-wave radio frequency signal and is sent to external radio frequency circuit to amplify by zero intermediate frequency technology, be unlike the prior art, this transmitting-receiving digital signal processing circuit is communicated by letter with main control module by cpci bus.
As prior art, described fpga chip is for realizing the logic control of inside circuit, the up/down frequency conversion of multiple signals and filtering processing and external interface are controlled, and fpga chip is sent to outside business module, by High Speed Serial, received the data of business module by High Speed Serial doing the required sound intermediate frequency data of business function simultaneously; Described DSP processes for realizing the signal of transceiver channel, controls transmitter candidate's device, power amplifier and day tune of end according to transmitter control protocol, controls the preselector of receiver according to receiver control protocol.
Specifically, the signal work for the treatment of of the transceiver channel of described dsp chip, specifically comprise the AD distortion compensation filtering of transmission channel, steps such as the AGC of transmission channel adjustment, transmission channel AM modulation, transmission channel merging, also complete the steps such as demodulation process of the filtering of receive path, the digital AGC of receive path and receive path simultaneously.Described fpga chip and dsp chip real-time, interactive deal with data.
Preferably, described fpga chip is realized the up/down frequency conversion of multiple signals and filtering and is processed that the device adopting is respectively upconverter and low-converter is realized, and wherein upconverter adopts AD9857, low-converter to adopt HSP50216.
Preferably, described fpga chip is sent to outside business module, by High Speed Serial, is received in the data of business module by High Speed Serial doing the required sound intermediate frequency data of business function, and the High Speed Serial using is serial communication chip MAX488.
Preferably, be connected with 3 external audio sampling AD chips on described dsp chip, the audio signal that described dsp chip collects 3 external audio sampling AD chips is modulated into short-wave radio frequency signal by zero intermediate frequency technology.Preferably, described external audio sampling AD chip is AD73322.
Preferably, be provided with an AD chip on described transceiver channel, first the signal after described upconversion process delivers to AD chip, and then dsp chip is controlled the modulation of AD chip and produced a short out ripple radiofrequency signal, by sendaisle, sends out; Described transceiver channel receives a road intermediate-freuqncy signal, first by AD chip, samples, and then by after down-converted, delivers to fpga chip and dsp chip and carry out demodulation process.Preferably, described AD chip AD9244.
While generally coming, the voltage of provide+12V of cpci bus ,-12V ,+5V ,+3.3V, two TPS54312 chip voltage stabilizing generation+0.2V voltages of the inner use of described transmitting-receiving digital signal processing circuit, offer fpga chip and dsp chip.
Beneficial effect: the shortwave transmitting-receiving digital signal processing circuit based on cpci bus that the utility model provides, can realize transmission-receiving function is synthesized in a circuit; This circuit adopts zero intermediate frequency radiating circuit, does not need extra mixting circuit, can improve integrated level, reduce equipment volume and weight; Between this circuit domain main control module, adopt the communication of cpci bus direction, there is the advantages such as extensibility is strong, transmission rate is high, communication reliability is good; This circuit can carry out Bootload by cpci bus, need not open machine, has software programmable flexibly, convenient, level and smooth elevating function.
Accompanying drawing explanation
Fig. 1 is structural representation of the present utility model;
Fig. 2 is the winding diagram of A/D chip in Fig. 1;
Fig. 3 is the winding diagram of 50216 low-converter chips in Fig. 1;
Fig. 4 is the winding diagram of DSP6416 chip in Fig. 1;
Fig. 5 is the winding diagram of three AD7330 chips in Fig. 1;
Fig. 6 is the winding diagram of 574245 chips in Fig. 1;
Fig. 7 is the winding diagram of upconverter chip in Fig. 1;
Fig. 8 is the winding diagram of power unit in Fig. 1;
Fig. 9 is the winding diagram of EP2SGX30DFFPGA chip in Fig. 1;
Figure 10 is the winding diagram of the utility model when reality is used.
Embodiment
Below in conjunction with accompanying drawing, the utility model is further described.
Be a kind of shortwave based on cpci bus transmitting-receiving digital signal processing circuit as shown in Figure 1 to 9, the clock signal that this transmitting-receiving digital signal processing circuit reception foreign frequency combiner circuit provides, the intermediate-freuqncy signal of outside radio circuit carried out demodulation process, audio signal is modulated into short-wave radio frequency signal by zero intermediate frequency technology and sends to external radio frequency circuit to amplify, by cpci bus, communicate by letter with main control module; Serial FLASH chip EPCS16SI16N, the serial communication chip MAX488 etc. that comprise AD chip AD73322, the FPGA of 1 fpga chip EP2SGX30,1 dsp chip TMS320C6416,1 upconverter AD9857,1 low-converter HSP50216,1 AD chip AD9244,3 external audio samplings; The voltage of provide+12V of cpci bus ,-12V ,+5V ,+3.3V, inside circuit is used two TPS54312 chip voltage stabilizing generation+1.2V to offer dsp chip and fpga chip.
On described dsp chip, be provided with cpci bus interface; Between described fpga chip and dsp chip, communication connects, and real-time, interactive deal with data.
Described fpga chip is for realizing the logic control of inside circuit, the up/down frequency conversion of multiple signals and filtering processing and external interface are controlled, and fpga chip is sent to outside business module, by High Speed Serial, received the data of business module by High Speed Serial doing the required sound intermediate frequency data of business function simultaneously.Described fpga chip is sent to outside business module, by High Speed Serial, is received in the data of business module by High Speed Serial doing the required sound intermediate frequency data of business function, and the High Speed Serial using is serial communication chip MAX488.
Described DSP processes for realizing the signal of transceiver channel, controls transmitter candidate's device, power amplifier and day tune of end according to transmitter control protocol, controls the preselector of receiver according to receiver control protocol; Specifically comprise the AD distortion compensation filtering of transmission channel, steps such as the AGC of transmission channel adjustment, transmission channel AM modulation, transmission channel merging, also complete the steps such as demodulation process of the filtering of receive path, the digital AGC of receive path and receive path simultaneously.Described fpga chip and dsp chip real-time, interactive deal with data.On described dsp chip, be connected with 3 external audio sampling AD chips, the audio signal that described dsp chip collects 3 external audio sampling AD chips is modulated into short-wave radio frequency signal by zero intermediate frequency technology.Preferably, described external audio sampling AD chip is AD73322.
On described transceiver channel, be provided with an AD chip AD9244, first signal after described upconversion process delivers to AD9244, then dsp chip is controlled AD9244 modulation and is produced a short out ripple radiofrequency signal (without outside intermediate frequency local oscillator signal), by sendaisle, sends out; Described transceiver channel receives a road intermediate-freuqncy signal, first by AD9244, samples, and then by after down-converted, delivers to fpga chip and dsp chip and carry out demodulation process.
In order to improve the isolation between the transmitting-receiving radiofrequency signal of inside circuit, at the radio frequency input and output side of circuit board, add radome, so just can reduce the interference between mutual channel, improve greatly Electro Magnetic Compatibility.
As shown in figure 10, shortwave transmitting-receiving digital signal processing circuit is communicated by letter with main control module in equipment by cpci bus, receives the control command of main control module, and each state information is offered to main control module in foregoing circuit wiring in use.Outside frequency synthesizer circuit provides digital signal processing circuit required clock signal, and the intermediate-freuqncy signal of radio circuit is given digital signal processing circuit and made demodulation process simultaneously.Digital signal processing circuit can be modulated into audio signal short-wave radio frequency signal, gives radio circuit and amplifies, and modulating part adopts zero intermediate frequency technology.
The above is only preferred implementation of the present utility model; be noted that for those skilled in the art; do not departing under the prerequisite of the utility model principle; can also make some improvements and modifications, these improvements and modifications also should be considered as protection range of the present utility model.
Claims (8)
1. the transmitting-receiving of the shortwave based on cpci bus digital signal processing circuit, is characterized in that: comprise 1 fpga chip and 1 dsp chip, between described fpga chip and dsp chip, communication connects, and is provided with cpci bus interface on described dsp chip.
2. the shortwave based on cpci bus according to claim 1 is received and dispatched digital signal processing circuit, it is characterized in that: described fpga chip is for realizing the logic control of inside circuit, the up/down frequency conversion of multiple signals and filtering processing and external interface are controlled, and fpga chip is sent to outside business module, by High Speed Serial, received the data of business module by High Speed Serial doing the required sound intermediate frequency data of business function simultaneously; Described DSP processes for realizing the signal of transceiver channel, controls transmitter candidate's device, power amplifier and day tune of end according to transmitter control protocol, controls the preselector of receiver according to receiver control protocol.
3. the shortwave based on cpci bus according to claim 2 is received and dispatched digital signal processing circuit, it is characterized in that: described fpga chip is realized the up/down frequency conversion of multiple signals and filtering and processed that the device adopting is respectively upconverter and low-converter is realized, and wherein upconverter adopts AD9857, low-converter to adopt HSP50216.
4. the shortwave based on cpci bus according to claim 2 is received and dispatched digital signal processing circuit, it is characterized in that: described fpga chip is sent to outside business module, by High Speed Serial, received in the data of business module by High Speed Serial doing the required sound intermediate frequency data of business function, and the High Speed Serial using is serial communication chip MAX488.
5. the shortwave based on cpci bus according to claim 2 is received and dispatched digital signal processing circuit, it is characterized in that: on described dsp chip, be connected with 3 external audio sampling AD chips, the audio signal that described dsp chip collects 3 external audio sampling AD chips is modulated into short-wave radio frequency signal by zero intermediate frequency technology.
6. the shortwave transmitting-receiving digital signal processing circuit based on cpci bus according to claim 5, is characterized in that: described external audio sampling AD chip is AD73322.
7. the shortwave based on cpci bus according to claim 2 is received and dispatched digital signal processing circuit, it is characterized in that: on described transceiver channel, be provided with an AD chip, first signal after described upconversion process delivers to AD chip, then dsp chip is controlled the modulation of AD chip and is produced a short out ripple radiofrequency signal, by sendaisle, sends out; Described transceiver channel receives a road intermediate-freuqncy signal, first by AD chip, samples, and then by after down-converted, delivers to fpga chip and dsp chip and carry out demodulation process.
8. the shortwave transmitting-receiving digital signal processing circuit based on cpci bus according to claim 7, is characterized in that: described AD chip AD9244.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420009340.6U CN203840332U (en) | 2014-01-07 | 2014-01-07 | Short wave transmitting-receiving digital signal processing circuit based on CPCI bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420009340.6U CN203840332U (en) | 2014-01-07 | 2014-01-07 | Short wave transmitting-receiving digital signal processing circuit based on CPCI bus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203840332U true CN203840332U (en) | 2014-09-17 |
Family
ID=51518125
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420009340.6U Withdrawn - After Issue CN203840332U (en) | 2014-01-07 | 2014-01-07 | Short wave transmitting-receiving digital signal processing circuit based on CPCI bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203840332U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103763001A (en) * | 2014-01-07 | 2014-04-30 | 熊猫电子集团有限公司 | Short wave transmit-receive digital signal processing circuit based on CPCI bus |
-
2014
- 2014-01-07 CN CN201420009340.6U patent/CN203840332U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103763001A (en) * | 2014-01-07 | 2014-04-30 | 熊猫电子集团有限公司 | Short wave transmit-receive digital signal processing circuit based on CPCI bus |
| CN103763001B (en) * | 2014-01-07 | 2016-01-20 | 熊猫电子集团有限公司 | Based on the shortwave transceiving digital signals treatment circuit of cpci bus |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104702306B (en) | Parallel Digital is to time converter architecture | |
| CN206517409U (en) | A kind of wireless double-channel communication system | |
| CN204272108U (en) | A kind ofly can support the communicator of ultrashort wave relaying with short-wave radio set intercommunication | |
| CN104301058A (en) | Multi-code-rate multi-channel multi-system measurement and control system of microsatellite | |
| WO2008067685A1 (en) | A wireless communication apparatus and the configuration method thereof | |
| US10812128B2 (en) | System and method for exchanging information | |
| US20090116510A1 (en) | High frequency communication device with minimal off chip components | |
| CN203590218U (en) | Microwave outdoor unit | |
| CN103763001B (en) | Based on the shortwave transceiving digital signals treatment circuit of cpci bus | |
| CN203840332U (en) | Short wave transmitting-receiving digital signal processing circuit based on CPCI bus | |
| WO2017113369A1 (en) | Signal transmission circuit, and tuned antenna | |
| CN204177972U (en) | Beidou satellite navigation single/double mode hand-hold radio frequency component | |
| CN106160778B (en) | portable station channel box | |
| CN103414490A (en) | Wireless telecom equipment with reconfigurable carrier frequency and reconfigurable signal bandwidth | |
| CN104507007B (en) | A kind of true diversity wireless microphone system | |
| CN208904993U (en) | A kind of double-channel wireless broadband transmission equipment | |
| CN206807446U (en) | A kind of RF transceiver circuit system | |
| CN203377874U (en) | Ethernet bus-based short wave transmit-receive integrated radio frequency module | |
| CN102790640B (en) | Field programmable gate array (FPGA) based multi-system, multi-band and multi-carrier digital repeater | |
| CN203377875U (en) | Ethernet bus-based four-channel shortwave transmit-receive unit | |
| CN202871972U (en) | Composite antenna and mobile terminal | |
| CN206807425U (en) | A kind of radio-frequency module of multichannel transmitting-receiving | |
| CN103427867A (en) | Short wave transceiving integration radio frequency module based on Ethernet bus | |
| CN204596129U (en) | Miniaturized high-speed number for state net II type concentrator passes communication module | |
| CN205212830U (en) | Maritime affairs radio station with count ability of passing on gong |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140917 Effective date of abandoning: 20160120 |
|
| C25 | Abandonment of patent right or utility model to avoid double patenting |