CN203840299U - Quadrature pulse decoding circuit for rotation incremental encoder - Google Patents
Quadrature pulse decoding circuit for rotation incremental encoder Download PDFInfo
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- CN203840299U CN203840299U CN201320867122.1U CN201320867122U CN203840299U CN 203840299 U CN203840299 U CN 203840299U CN 201320867122 U CN201320867122 U CN 201320867122U CN 203840299 U CN203840299 U CN 203840299U
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- xor gate
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- 238000002955 isolation Methods 0.000 claims abstract description 13
- 230000002441 reversible effect Effects 0.000 description 5
- 230000011218 segmentation Effects 0.000 description 5
- 238000001914 filtration Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000009987 spinning Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
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- Transmission And Conversion Of Sensor Element Output (AREA)
- Indicating Or Recording The Presence, Absence, Or Direction Of Movement (AREA)
Abstract
The utility model discloses a quadrature pulse decoding circuit for a rotation incremental encoder. The quadrature pulse decoding circuit comprises a signal isolation circuit and is characterized by also comprising four exclusive-OR gates U1-1, U1-2, U1-3 and U1-4, and four monostable triggers U2, U3, U4 and U5. After quadrature pulse signals P1 and P2 pass through the signal isolation circuit, the quadrature pulse signal P2 accesses input ends of the monostable triggers U4 and U5. Output ends of the U4 and U5 are connected to the exclusive-OR gate U1-3. After passing through the signal isolation circuit, the quadrature pulse signals P1 and P2 access the exclusive-OR gate U1-2. An output end of the U1-2 is connected with an input end of the monostable trigger U2 and an input end of the monostable trigger U3 respectively. Output ends of the monostable triggers U2 and U3 are connected to the exclusive-OR gates U1-1. An output end of the exclusive-OR gates U1-2 and an output end of the exclusive-OR gates U1-3 are connected to an input end of the exclusive-OR gates U1-4. With the quadrature pulse decoding circuit, problems that interference can be mixed in signals easily in sensing and division of the quadrature pulses of the rotation incremental encoder, and interference cannot be eliminated automatically, and thus result counting precision is affected in the prior art are solved.
Description
Technical field
The utility model belongs to encoder orthogonal pulses decoding technique field, relates in particular to a kind of increment of rotation encoder orthogonal pulses decoding circuit.
Background technology
In the measuring technique of electrical control and machine-building, encoder is to apply equipment more widely.Increment of rotation encoder must solve the phase demodulation (or sensing) of spinning movement and the problem of counting pulse signal in using.Require high should the having of resolution, also need the encoder pulse signal to segment.The sensing of code device signal and segmentation have many kinds, and the sensing that is easy to realize just has R-S to trigger, J-K triggering etc.; Pulse segmentation has also 1,2,4 segmentations etc., and some sensing and segmentation are separate, and some is to be mutually related.But be all easy to noise jamming to sneak in signal, and can not automatically eliminate, thereby affect result count precision.
Summary of the invention
The technical problems to be solved in the utility model: a kind of increment of rotation encoder orthogonal pulses decoding circuit, the orthogonal pulses of increment of rotation encoder is carried out to sensing and segment being easy to of existing noise jamming is sneaked in signal to solve prior art, and can not automatically eliminate, thereby affect the problems such as result count precision.
Technical solutions of the utility model:
A kind of increment of rotation encoder orthogonal pulses decoding circuit, it comprises signal isolation circuit, also comprise four XOR gate U1-1, U1-2, U1-3 and U1-4, four monostable trigger U2, U3, U4 and U5, orthogonal pulses signal P1 and P2 are after signal isolation circuit, P2 access monostable trigger U4 and U5 input, monostable trigger U4 and U5 output are connected to XOR gate U1-3, orthogonal pulses signal P1 after signal isolation circuit and P2 access XOR gate U1-2, XOR gate U1-2 output and monostable trigger U2, U3 input connects respectively, monostable trigger U2, U3 output is connected to XOR gate U1-1, XOR gate U1-2 output and XOR gate U1-3 output access XOR gate U1-4 input.
Described four XOR gate U1-1, U1-2, forms four XOR gate chips together with U1-3 is integrated in U1-4.
Four monostable trigger U2, U3, U4 and U5, wherein U2 and U3 integrate, and U4 and U5 integrate, and form two two monostable triggers.
The utility model beneficial effect:
The utility model circuit structure is simple, increment of rotation encoder orthogonal pulses signal is after signal processing circuit is carried out routine isolation and filter amplifying processing, by obtaining one after a series of monostable triggerings and XOR, the identification signal that two and four subdivision and count pulses and both forward and reverse directions rotate, the identification signal that one of them subdivision and count pulse and both forward and reverse directions are rotated is input to counter or slot control machine counts and measure use for system, signal processing circuit of the present invention aims at the orthogonal pulses signal in orthogonal of magnetic induction orthogonal pulses generator and decodes used, this signal processing circuit adopts common buffer circuit and four monostable triggers and four exclusive or logic gate compositions, this circuit is simple, economical, practical, performance is good, easy to implement, it is made up of common and the most few element, device cost is cheap doubly more a lot of than encoder dedicated decoders, there is good practical value, and can suppress mechanical edge and shake the interference causing, having solved prior art carries out sensing to the orthogonal pulses of increment of rotation encoder and segments being easy to of existing interference is sneaked in signal, and can not automatically eliminate, thereby affect the problems such as result count precision.
brief description of the drawings:
Fig. 1 is the utility model signal processing circuit principle schematic;
Fig. 2 is XOR quadrature decoder sequential chart of the present utility model.
embodiment:
A kind of increment of rotation encoder orthogonal pulses decoding circuit, it comprises (see figure 1) signal isolation circuit, also comprise four XOR gate U1-1, U1-2, U1-3 and U1-4, four monostable trigger U2, U3, U4 and U5, orthogonal pulses signal P1 and P2 are after signal isolation circuit, P2 access monostable trigger U4 and U5 input, monostable trigger U4 and U5 output are connected to XOR gate U1-3, and XOR gate U1-3 output is connected with two subdivision and count clock signal terminals; Monostable trigger U4 output is connected with a subdivision and count clock signal terminal; Orthogonal pulses signal P1 after signal isolation circuit and P2 access XOR gate U1-2, XOR gate U1-2 output is connected respectively with monostable trigger U2, U3 input, monostable trigger U2, U3 output are connected to XOR gate U1-1, and XOR gate U1-1 output is connected with four subdivision and count clock signal terminals; XOR gate U1-2 output and XOR gate U1-3 output access XOR gate U1-4 input, XOR gate U1-4 output is connected to both forward and reverse directions and rotates identification signal end.
Described four XOR gate U1-1, U1-2, forms four XOR gate chips together with U1-3 is integrated in U1-4; Four monostable trigger U2, U3, U4 and U5, wherein U2 and U3 integrate, and U4 and U5 integrate, and form two two monostable triggers, to increase decoding circuit integrated level, reduce the volume of circuit, increase circuit anti-interference.
In Fig. 1, the upper R5 of monostable trigger U2, U3, U4 and U5 and C5, R6 and C6, R7 and C7, R8 and C8 form the timing resistor electric capacity of each monostable trigger, and VCC provides power supply, and timing resistor and electric capacity are determined the width of output pulse.
Can draw from Fig. 2 XOR quadrature decoder of the present utility model sequential chart, in the time of forward rotation, Pc1, Pc2, Pc4 are always corresponding to the positive level of Pud; And in the time rotating backward, Pc1, Pc2, Pc4 are always corresponding to the negative level of Pud, and practice proves, and Fig. 2 sequential is carried out to Hardware or software implementation, can realize position accurately, reliably counting, the existing fluted disc of resolution add approach switch 4 ~ 16 times (1 ~ 4 teeth).
1 and 2 can find out with reference to the accompanying drawings, shown in the principle schematic of signal processing circuit shown in Fig. 1 and Fig. 2, oscillogram is on all four, the utility model decoding circuit is without extra clock pulse, simple monostable trigger and XOR compute chip and a small amount of resistance capacitance, just can complete increment of rotation encoder orthogonal pulses decoding function, and the signal of the reversible counting that multiple segmentation selects is provided, i.e. output signal: Pc1, Pc2, Pc4(select one of them) and Pud.
Should be greater than Xt in order to improve reliability Yt; After while connecing just along counter, be output as/2Q(2Q of monostable trigger U3 is non-), or reverse in outside, when the width of sub-divided pulse is less than 1/4 of the edge vibrations cycle, can suppress mechanical edge and shake the interference causing, can other anti-noise measure of dual-purpose for high-frequency electromagnetic interference, as input capacitance filtering, synchronous filtering, optical coupling input etc.
Claims (3)
1. an increment of rotation encoder orthogonal pulses decoding circuit, it comprises signal isolation circuit, it is characterized in that: also comprise four XOR gate U1-1, U1-2, U1-3 and U1-4, four monostable trigger U2, U3, U4 and U5, orthogonal pulses signal P1 and P2 are after signal isolation circuit, P2 access monostable trigger U4 and U5 input, monostable trigger U4 and U5 output are connected to XOR gate U1-3, orthogonal pulses signal P1 after signal isolation circuit and P2 access XOR gate U1-2, XOR gate U1-2 output and monostable trigger U2, U3 input connects respectively, monostable trigger U2, U3 output is connected to XOR gate U1-1, XOR gate U1-2 output and XOR gate U1-3 output access XOR gate U1-4 input.
2. a kind of increment of rotation encoder orthogonal pulses decoding circuit according to claim 1, is characterized in that: described four XOR gate U1-1, U1-2, forms four XOR gate chips together with U1-3 is integrated in U1-4.
3. a kind of increment of rotation encoder orthogonal pulses decoding circuit according to claim 1, is characterized in that: four monostable trigger U2, U3, U4 and U5, and wherein U2 and U3 integrate, and U4 and U5 integrate, and form two two monostable triggers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320867122.1U CN203840299U (en) | 2013-12-26 | 2013-12-26 | Quadrature pulse decoding circuit for rotation incremental encoder |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320867122.1U CN203840299U (en) | 2013-12-26 | 2013-12-26 | Quadrature pulse decoding circuit for rotation incremental encoder |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203840299U true CN203840299U (en) | 2014-09-17 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320867122.1U Expired - Lifetime CN203840299U (en) | 2013-12-26 | 2013-12-26 | Quadrature pulse decoding circuit for rotation incremental encoder |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106124962A (en) * | 2016-06-15 | 2016-11-16 | 安庆师范学院 | A kind of once inside out selects network and upset sequence decompression architecture thereof and decompressing method |
-
2013
- 2013-12-26 CN CN201320867122.1U patent/CN203840299U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106124962A (en) * | 2016-06-15 | 2016-11-16 | 安庆师范学院 | A kind of once inside out selects network and upset sequence decompression architecture thereof and decompressing method |
| CN106124962B (en) * | 2016-06-15 | 2017-08-25 | 安庆师范学院 | A kind of once inside out selection network and its upset sequence decompression architecture and decompressing method |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20160505 Address after: Jin Zhu Xi Lu Lake District 550081 Guizhou city of Guiyang province No. 2 aluminum technology building Patentee after: GUIZHOU INNOVATIVE LIGHT METAL PROCESS EQUIPMENT ENGINEERING TECHNOLOGY RESEARCH CENTER CO.,LTD. Address before: 550081 Guizhou Province, Guiyang City Lake District Jinyang Road No. 469 Patentee before: Guiyang Aluminum Magnesium Design & Research Institute Co.,Ltd. |
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| CX01 | Expiry of patent term |
Granted publication date: 20140917 |
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| CX01 | Expiry of patent term |