CN203813748U - Signal amplitude detection circuit - Google Patents
Signal amplitude detection circuit Download PDFInfo
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- CN203813748U CN203813748U CN201320838101.7U CN201320838101U CN203813748U CN 203813748 U CN203813748 U CN 203813748U CN 201320838101 U CN201320838101 U CN 201320838101U CN 203813748 U CN203813748 U CN 203813748U
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Abstract
The utility model provides a signal amplitude detection circuit which comprises a detector and a trimming algorithm module. The detector comprises a preset standard threshold reference quantity. A signal to be tested is inputted into the detector. The output end of the detector is connected with the trimming algorithm module. The trimming algorithm module is used for recording an output result of the detector, decoding the output result and outputting amplitude coding values. The trimming algorithm module further generates a control signal. The control signal controls the standard threshold reference quantity to rise from a ground level to a power level or fall from the power level to the ground level. In addition, when crossover happens between the standard threshold reference quantity and the tested signal, the output result of the detector is 1; or else, the output result of the detector is 0. The signal amplitude detection circuit detects signal amplitude in a digital mode and is simple in structure, low in power consumption, small in chip area, stable in result, and none in PVT drift.
Description
Technical field
The utility model relates to semiconductor integrated circuit field, relates more specifically to a kind of circuit for detection of signal amplitude.
Background technology
Traditional circuit for detection of signal amplitude adopts analog circuit filtering or analogue signal amplitude-power conversion circuits mode to detect signal amplitude conventionally, mainly realizes the detection to signal amplitude by the mode of analog circuit.But analog circuit is because of the reason of fabrication process parameters, and the deviation of testing result is larger conventionally.Analog filter bandwidth can not accurately be determined in addition, and analogue signal amplitude-power conversion circuits working point can not accurately be determined; And no matter be to use analog filter or analogue signal amplitude-power conversion circuits, if need follow-up digital circuit to detect signal amplitude, all needing additionally increases a set of A-D change-over circuit, thereby makes the whole circuit structure complexity for detection of signal amplitude, is not easy to realize.
Therefore, be necessary to provide a kind of improved circuit for detection of signal amplitude to overcome above-mentioned defect.
Utility model content
The purpose of this utility model has been to provide a kind of circuit for detection of signal amplitude, should use digital form to detect signal amplitude for detection of the circuit of signal amplitude, simple in structure, low in energy consumption, and chip area is little, and result is stable drifts about without PVT.
For achieving the above object, the utility model provides a kind of circuit for detection of signal amplitude, comprise detector and trim algoritic module, described detector is preset with baseline threshold reference quantity, described detector is inputted in measured signal, the output of described detector with described in trim algoritic module and be connected, the described algoritic module that trims records the Output rusults of described detector and described Output rusults is carried out to output amplitude encoded radio after decoding, and described in trim algoritic module and also produce a control signal, described in described control signal control, baseline threshold reference quantity rises to power level or drops to ground level from power level from ground level, and, in the time that described baseline threshold reference quantity and described measured signal are handed over more, the Output rusults of described detector is 1, otherwise the Output rusults of described detector is 0.
Preferably, described control signal is 2 system digital signals of N position, and N is more than or equal to 2 positive integer, and baseline threshold reference quantity is with 2 described in described control signal control
nfor gear evenly rises to power level or drops to ground level from power level from ground level.
Preferably, described detector comprises the first inverter, the second inverter, with door, the first XOR gate and the second XOR gate, described measured signal comprises positive measured signal and negative measured signal, described positive measured signal and control signal are inputted the input of described the first inverter, described negative measured signal and control signal are inputted the input of described the second inverter, the output of described the first inverter is connected with described the first XOR gate and with an input of door respectively, the output of described the second inverter is connected with described the first XOR gate and with another input of door respectively, described the first XOR gate and being all connected with the input of described the second XOR gate with the output of door, described the first XOR gate and being connected with two inputs of described the second XOR gate respectively with the output of door, the output of described the second XOR gate is exported the Output rusults of described detector.
Preferably, described detector also comprises the first electric capacity and the second electric capacity, and one end of described the first electric capacity is connected with the output of described the first XOR gate and an input of the second XOR gate, other end ground connection; One end of described the second electric capacity is connected with the output of door and another input of the second XOR gate with described, other end ground connection.
Preferably, described the first inverter and the second inverter have identical architectural feature.
Preferably, described the first inverter comprises that the first control switch group, the second control switch group, current source group and electric current sink group, the input of described current source group and the heavy group of electric current is inputted in described measured signal, signal after the output output conversion of the heavy group of described current source group and electric current, described the first control switch group is connected with described current source group, control the work of described current source group, described the second control switch group is connected with the heavy group of described electric current, controls the work of the heavy group of described electric current.
Preferably, closure and the disconnection of the first control switch group and the second control switch group described in described control signal control, and described the first control switch group and the second control switch group include N control switch, described current source group comprises N current source, the heavy group of described electric current comprises that N electric current is heavy, the N of described the first control switch group control switch correspondence is connected with N current source of described current source group, the N of described the second control switch group control switch heavy connection of N electric current corresponding and the heavy group of described electric current.
Preferably, a described N current source and N heavy field effect transistor or the bipolar junction transistor of all can be of electric current.
Compared with prior art, circuit for detection of signal amplitude of the present utility model, rise to power level or drop to ground level from power level from ground level by baseline threshold reference quantity described in described control signal control, described measured signal is handed over more with baseline threshold reference quantity in its level amplitude range, and in the time that described baseline threshold reference quantity and described measured signal are handed over more, the Output rusults of described detector is 1, otherwise the Output rusults of described detector is 0; Thereby can know the range value of described measured signal by adjudicating the state of Output rusults of described detector, and the utility model is to use digital form to detect signal amplitude, simple in structure, low in energy consumption, and chip area is little, result is stable drifts about without PVT.
By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.
Brief description of the drawings
Fig. 1 is the structured flowchart of the utility model for detection of the circuit of signal amplitude.
Fig. 2 is the oscillogram of the utility model for detection of the circuit working of signal amplitude.
Fig. 3 is the sequential chart of the utility model for detection of the circuit working of signal amplitude.
Fig. 4 is the circuit structure diagram of the utility model for detection of the detector of the circuit of signal amplitude.
Fig. 5 is the structured flowchart of the first inverter shown in Fig. 4.
Embodiment
With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of circuit for detection of signal amplitude, should use digital form to detect signal amplitude for detection of the circuit of signal amplitude, simple in structure, low in energy consumption, and chip area is little, result is stable drifts about without PVT (technique-voltage-temperature).
Please refer to Fig. 1-3, as shown in the figure, the circuit for detection of signal amplitude of the present utility model comprises detector and trims algoritic module; In described detector, be preset with baseline threshold reference quantity ref (as shown in Figure 2); Measured signal input inputs described detector, the output of described detector with described in trim algoritic module and be connected, the described Output rusults out1 that trims algoritic module and record described detector, described in trim algoritic module the Output rusults out1 of described detector carried out to decoding output amplitude encoded radio out2; And described in trim algoritic module and also produce a control signal ctrl, wherein, described control signal is 2 system digital signals of N position, and N is more than or equal to 2 positive integer, described control signal ctrl controls described baseline threshold reference quantity ref with 2
nfor gear rises to power level VCC (seeing Fig. 2) or drops to ground level GND (not shown) from power level VCC from ground level GND equably; And in the time that described baseline threshold reference quantity ref and described measured signal input hand over more, the Output rusults out1 of described detector is 1, otherwise the Output rusults out1 of described detector is 0 (seeing Fig. 3); Thereby the length that is 1 by the Output rusults out1 of described detector, and by the described conversion that trims algoritic module, can effectively test out the amplitude of described measured signal input, be described amplitude coding value out2.In the utility model, because of the value of N larger, the gear that described baseline threshold reference quantity ref rises or declines is more, more with the crossover point of described measured signal input, make the accuracy of Output rusults out1 of described detector higher, therefore the value of N can need to set according to precision, and its value is larger, and the precision of Output rusults is higher.
Particularly, please tie again with reference to figure 4 and Fig. 5.Described detector comprise the first inverter inv1, the second inverter inv2, with door AND, the first XOR gate NOR1 and the second XOR gate NOR2, described measured signal input is differential input signal, it includes positive measured signal inputp and negative measured signal inputn, described positive measured signal inputp and control signal ctrl input the input of described the first inverter inv1, and described negative measured signal inputn and control signal ctrl input the input of described the second inverter inv2, thereby described control signal ctrl controls upset and the output signal pb of described positive measured signal inputp in described the first inverter inv1, and controls upset and the output signal nb of described negative measured signal inputn in described the second inverter inv2 simultaneously, the output of described the first inverter inv1 is connected with described the first XOR gate NOR1 and with an input of door AND respectively, the output of described the second inverter inv2 is connected with described the first XOR gate NOR1 and with another input of door AND respectively, described the first XOR gate NOR1 and being all connected with the input of described the second XOR gate NOR2 with the output of door AND, described the first XOR gate NOR1 and being all connected with the input of described the second XOR gate NOR2 with the output of door AND, the output of described the second XOR gate NOR2 is exported the Output rusults out1 of described detector.In preferred implementation of the present utility model, described detector also comprises the first electric capacity c1 and the second electric capacity c2, one end of described the first electric capacity c1 is connected with the output of described the first XOR gate NOR1 and an input of the second XOR gate NOR2, other end ground connection; One end of described the second electric capacity c2 is connected with the door output of AND and another input of the second XOR gate NOR2 with described, other end ground connection; Thereby described the first electric capacity c1 and the second electric capacity c2 can filtering described in the signal dip of the first XOR gate NOR1 output and the noise of the signal din that described and door AND export, make whole circuit working more stable.
Separately, in preferred implementation of the present utility model, described the first inverter inv1 and the second inverter inv2 have identical architectural feature, therefore, the architectural feature of only introducing described the first inverter inv1 at this, no longer repeats to introduce the architectural feature of described the second inverter inv2.As shown in Figure 5, described the first inverter inv1 comprises that the first control switch group, the second control switch group, current source group and electric current sink group, described positive measured signal inputp inputs the input of described current source group and the heavy group of electric current, signal pb after the output output conversion of the heavy group of described current source group and electric current, described the first control switch group is connected with described current source group, control the work of described current source group, described the second control switch group is connected with the heavy group of described electric current, controls the work of the heavy group of described electric current, wherein said the first control switch group and the second control switch group include N control switch, the control end of each described control switch is subject to the binary numeral control that described control signal ctrl is corresponding, described current source group comprises N current source, and N current source is all connected in parallel, the heavy group of described electric current comprises that N electric current is heavy, and N electric current sinks and is all connected in parallel, the N of described the first control switch group control switch correspondence is connected with N current source of described current source group, the N of described the second control switch group control switch heavy connection of N electric current corresponding and the heavy group of described electric current, closure and the disconnection of the first control switch group and the second control switch group described in another described control signal control, (as shown in Figure 5), and each control word of described control signal is corresponding controls a switch of switch of the first control switch group and the second control switch group, thus N switch of the N of described control signal control word described the first control switch of correspondence and the second control switch.Separately, in preferred implementation of the present utility model, heavy field effect transistor or the bipolar junction transistor of all can be of a described N current source and N electric current, can certainly for other can serve as, electric current sinks or device or the circuit of current source.
The course of work of the utility model signal magnitude detector is described below in conjunction with Fig. 1-5.
After a described control end rst who trims algoritic module puts 1, the whole circuit for detection of signal amplitude is started working.Described control signal ctrl controls described baseline threshold reference quantity with 2
nfor evenly rising to power level VCC from ground level GND, gear (certainly also can pass through the control mode of the described control signal ctrl of change, make described baseline threshold reference quantity be reduced to ground level GND from power level VCC), complete once from ground to power supply or the scanning of the level from power supply to ground; And described in scanning process, trimming algoritic module and detecting the state of described detector Output rusults out1, in the time that measured signal input and described baseline threshold reference quantity are passed through, the Output rusults out1 of described detector is 1, when handing over more described in the Output rusults out1 of detector be 0; In scanning process, described in trim algoritic module and record the state of the export structure out1 of described detector; In the time of the end of scan, described in trim algoritic module each state information decoding of described detector Output rusults out1 obtained to measured signal input amplitude coding value out2, described another control end cal that trims algoritic module is put to 1 expression testing process simultaneously and finishes.
Particularly, when the level of the measured signal input of input (positive measured signal inputp and negative measured signal inputn) is higher than described baseline threshold reference quantity, as shown in Fig. 2 left side, positive measured signal inputp output signal pb after described the first inverter inv1, negative measured signal inputn output signal nb after the second inverter inv2, and signal pb and np are " 0 "; Signal pb, nb are by the first XOR gate NOR being attached thereto, and output signal dip is " 1 "; Signal pb, nb by be attached thereto with door AND, output signal din is " 0 "; Signal dip and din obtain the Output rusults out1 of described detector by the second XOR gate NOR being attached thereto, and out1 is " 0 ", represent that the measured signal input of input does not hand over more with described baseline threshold reference quantity.When the level of measured signal input of input is lower than described baseline threshold reference quantity, as shown in Fig. 2 the right, positive measured signal inputp output signal pb after described the first inverter inv1, negative measured signal inputn output signal nb after the second inverter inv2, and signal pb and np are " 1 "; Signal pb, nb are by the first XOR gate NOR being attached thereto, and output signal dip is " 0 "; Signal pb, nb by be attached thereto with door AND, output signal din is " 1 "; Signal dip and din obtain the Output rusults out1 of described detector by the second XOR gate NOR being attached thereto, and out1 is " 0 ", represent that the measured signal input of input does not hand over more with described baseline threshold reference quantity.When the level of the measured signal input inputting equals described baseline threshold reference quantity, as shown in Fig. 2 centre, positive measured signal inputp output signal pb after described the first inverter inv1, negative measured signal inputn output signal nb after the second inverter inv2, and signal pb is " 0 ", np is " 1 "; Signal pb, nb are by the first XOR gate NOR being attached thereto, and output signal dip is " 0 "; Signal pb, nb by be attached thereto with door AND, output signal din is " 0 "; Signal dip and din obtain the Output rusults out1 of described detector by the second XOR gate NOR being attached thereto, and out1 is " 1 ", and the measured signal input that represents input has occurred to hand over described baseline threshold reference quantity and got over; Also as long as described measured signal input and described baseline threshold reference quantity occur to hand over more, the Output rusults out1 of described detector is " 1 ", and described baseline threshold reference quantity rises to power level VCC from ground level GND, make the level value of described measured signal input all can occur to hand over more (significantly with described baseline threshold reference quantity, N value is larger, crossover point is more), thus the state that the Output rusults out1 of described detector is " 1 " has reacted the signal amplitude of described measured signal input; Export out2 by the described conversion that trims the Output rusults out1 of algoritic module to everyone has a copy detector, described Output rusults out2 is the signal amplitude of described measured signal input.
In addition, the processing procedure of described inverter to measured signal input is described below, because described the first inverter inv1 is identical with the architectural feature of the second inverter inv2, only describes described the first inverter inv1 at this.When N-1 current source of the first control switch group Parallel Control current source group opened, and only 1 heavy unlatching of electric current of the heavy group of the second control switch group Parallel Control electric current simultaneously, the now effect of current source group is much larger than the effect of the heavy group of electric current, current source open threshold value lower be measured signal input amplitude when higher current source presented leading role, make output signal pb upset (with respect to measured signal input negate); When only 1 the current source unlatching of the first control switch group Parallel Control current source group, open and N-1 electric current of the heavy group of the second control switch group Parallel Control electric current is heavy simultaneously, the now heavy effect of electric current is much larger than current source effect, electric current is heavy open threshold value lower be measured signal input amplitude electric current is heavy when lower has presented leading role, make to export pb upset; For the normal state of above two kinds of situations, when the individual current source of the N-M (M is the positive integer that is less than N) of the first control switch group Parallel Control current source group is opened, and simultaneously M electric current of the heavy group of the second control switch group Parallel Control electric current is heavy while opening, current source group, the heavy group of electric current are exported the overturn point of bp according to weight control separately; Particularly, when the current source number of access current source group is greater than the heavy heavy number of electric current of organizing of access electric current, current source plays a leading role, current source open threshold value lower be measured signal input amplitude when higher current source presented leading role, make output signal pb upset; When the heavy number of electric current of the heavy group of access electric current is greater than the number of the current source of access current source group, electric current is heavy to play a leading role, electric current is heavy open threshold value lower be measured signal input amplitude electric current is heavy when lower has presented leading role, make to export pb upset.Be that pb turn threshold is directly determined by the weight of current source group, the heavy group access of electric current.In addition; in Fig. 3, jdg is depicted as the decision error of described detector to measured signal input; notoriously; because measured signal input is analog signal; and analog signal conventionally has noise dither in amplitude; make described detector in the time that the critical friendship of its Output rusults out1 state transition is got over, occur that decision error, this decision error are in Fig. 3 shown in jdg.
In conjunction with most preferred embodiment, the utility model is described above, but the utility model is not limited to the embodiment of above announcement, and should contains the various amendments of carrying out according to essence of the present utility model, equivalent combinations.
Claims (8)
1. the circuit for detection of signal amplitude, it is characterized in that, comprise detector and trim algoritic module, described detector is preset with baseline threshold reference quantity, described detector is inputted in measured signal, the output of described detector with described in trim algoritic module and be connected, the described algoritic module that trims records the Output rusults of described detector and described Output rusults is carried out to decoding output amplitude encoded radio, and described in trim algoritic module and also produce a control signal, described in described control signal control, baseline threshold reference quantity rises to power level or drops to ground level from power level from ground level, and, in the time that described baseline threshold reference quantity and described measured signal are handed over more, the Output rusults of described detector is 1, otherwise the Output rusults of described detector is 0.
2. the circuit for detection of signal amplitude as claimed in claim 1, is characterized in that, described control signal is 2 system digital signals of N position, and N is more than or equal to 2 positive integer, and baseline threshold reference quantity is with 2 described in described control signal control
nfor gear evenly rises to power level or drops to ground level from power level from ground level.
3. the circuit for detection of signal amplitude as claimed in claim 2, it is characterized in that, described detector comprises the first inverter, the second inverter, with door, the first XOR gate and the second XOR gate, described measured signal comprises positive measured signal and negative measured signal, described positive measured signal and control signal are inputted the input of described the first inverter, described negative measured signal and control signal are inputted the input of described the second inverter, the output of described the first inverter is connected with described the first XOR gate and with an input of door respectively, the output of described the second inverter is connected with described the first XOR gate and with another input of door respectively, described the first XOR gate and being all connected with the input of described the second XOR gate with the output of door, described the first XOR gate and being all connected with the input of described the second XOR gate with the output of door, the output of described the second XOR gate is exported the Output rusults of described detector.
4. the circuit for detection of signal amplitude as claimed in claim 3, it is characterized in that, described detector also comprises the first electric capacity and the second electric capacity, and one end of described the first electric capacity is connected with the output of described the first XOR gate and an input of the second XOR gate, other end ground connection; One end of described the second electric capacity is connected with the output of door and another input of the second XOR gate with described, other end ground connection.
5. the circuit for detection of signal amplitude as claimed in claim 4, is characterized in that, described the first inverter and the second inverter have identical architectural feature.
6. the circuit for detection of signal amplitude as claimed in claim 5, it is characterized in that, described the first inverter comprises that the first control switch group, the second control switch group, current source group and electric current sink group, the input of described current source group and the heavy group of electric current is inputted in described measured signal, signal after the output output conversion of the heavy group of described current source group and electric current, described the first control switch group is connected with described current source group, control the work of described current source group, described the second control switch group is connected with the heavy group of described electric current, controls the work of the heavy group of described electric current.
7. the circuit for detection of signal amplitude as claimed in claim 6, it is characterized in that, the ON/OFF of the first control switch group and the second control switch group described in described control signal control, and described the first control switch group and the second control switch group include N control switch, described current source group comprises N current source, the heavy group of described electric current comprises that N electric current is heavy, the N of described the first control switch group control switch correspondence is connected with N current source of described current source group, the N of described the second control switch group control switch heavy connection of N electric current corresponding and the heavy group of described electric current.
8. the circuit for detection of signal amplitude as claimed in claim 7, is characterized in that, a described N current source and N heavy field effect transistor or the bipolar junction transistor of all can be of electric current.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320838101.7U CN203813748U (en) | 2013-12-18 | 2013-12-18 | Signal amplitude detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320838101.7U CN203813748U (en) | 2013-12-18 | 2013-12-18 | Signal amplitude detection circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203813748U true CN203813748U (en) | 2014-09-03 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN201320838101.7U Withdrawn - After Issue CN203813748U (en) | 2013-12-18 | 2013-12-18 | Signal amplitude detection circuit |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103675474A (en) * | 2013-12-18 | 2014-03-26 | 四川和芯微电子股份有限公司 | Signal amplitude detection circuit |
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2013
- 2013-12-18 CN CN201320838101.7U patent/CN203813748U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103675474A (en) * | 2013-12-18 | 2014-03-26 | 四川和芯微电子股份有限公司 | Signal amplitude detection circuit |
| CN103675474B (en) * | 2013-12-18 | 2016-04-13 | 四川和芯微电子股份有限公司 | Signal amplitude detection circuit |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140903 Effective date of abandoning: 20160413 |
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| C25 | Abandonment of patent right or utility model to avoid double patenting |