CN203798978U - Apparatus for accurately measuring and reporting sequential relationship between two kinds of signals in chip - Google Patents
Apparatus for accurately measuring and reporting sequential relationship between two kinds of signals in chip Download PDFInfo
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- CN203798978U CN203798978U CN201420152874.4U CN201420152874U CN203798978U CN 203798978 U CN203798978 U CN 203798978U CN 201420152874 U CN201420152874 U CN 201420152874U CN 203798978 U CN203798978 U CN 203798978U
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Abstract
The utility model discloses an apparatus for accurately measuring and reporting the sequential relationship between two kinds of signals in a chip. The input end of a pulse generation circuit of delay time pulse width is connected with a digital signal line to be measured and a reference signal line; the output end of the pulse generation circuit of delay time pulse width is divided into two paths, wherein one path is connected with a first time voltage conversion circuit through a pulse generation circuit of periodic pulse width, and the other path is directly connected with a second time voltage conversion circuit; the input end of the pulse generation circuit of periodic pulse width is connected with the output end of the pulse generation circuit of delay time pulse width and the reference signal line; and the output end of the pulse generation circuit of periodic pulse width is connected with the first time voltage conversion circuit. According to the apparatus for accurately measuring and reporting the sequential relationship between the two kinds of signals in the chip, the time interval between the edges of the two kinds of the signals is converted into analog voltage, so that the sequential relationship between the two kinds of the signals can be measured, and the sequential relationship of the edges of two groups of inner signals in an integrated circuit can be detected conveniently; and the analog voltage and delay time between the edges are in direct proportion, and therefore, voltage computation delay time can be read.
Description
[technical field]
The utility model belongs to technical field of integrated circuits, particularly a kind of detection implement device of sequential relationship.
[background technology]
At present, have a lot of methods to can be used to measure signal in chip, but they but all have significant limitation:
A) use custom-designed interface that a large amount of inner signal of interests are sent to integrated circuit pin, then use standard automatic test equipment (ATE) to carry out signal measurement.
In general, need to, under specific operational mode (test pattern), signal specific is sent to special pin, and the function of this pin be different under normal manipulation mode from it.
The weak point of this mode: for signal is sent to pin, need extra cabling and circuit to connect, if while especially needing a large amount of signals to monitor, cost will be very large, also can affect other circuit under normal manipulation mode.
In addition, signal being sent to pin (with respect to die size, sometimes belonging to long Distance Transmission) means at pin place and can be observed signal delay.If in the time of particularly must measuring the sequential relationship between two kinds of signals, by by driving on an equal basis intensity to drive signal and these signals transmit by pre-determined route, make signal delay coupling.But this process be but difficult to realize, and require a high expenditure of energy and carry out chip layout's wiring and design.
B) utilize fine-tuning delay element to change inner sequential, until by or Failure Boundaries value be detected
The method need to be inserted signal path by delay element, and delay element can be finely tuned under test pattern.In order to detect two kinds of sequential relationships between signal, the signal delay producing is carried out to diversified facilities, and carry out functional test by delay element.Delay element setting for different, repeats functional test, until test failure.By or the difference of Failure Boundaries value and default settings be the time sequence allowance of these two kinds of signals.
Use the method, can only detect time sequence allowance by indirect approach, before test crash, just can determine that the change of much degree can occur two kinds of sequential relationships between signal, but but cannot determine absolute timing off-set between two kinds of signals is how many and (that is to say, for equipment is normally moved, before signal B, cannot determine that signal A need to transmit 50ps or 500ps).
And, because delay element area is larger, so can only be a few local use.Even if selected zero-lag, the original signal transmission speed that also can slow down (because this signal has additional load, and for connection delay element, wiring also can be longer).
C) acquisition of signal
There is several different methods to can be used to survey internal signal.
The most frequently used method is that microprobe is surveyed, and the method need to be connected to a microprobe on the circuit of chip surface distribution.This probe is connected with amplifier, can be used for measuring the signal on the circuit being connected to, and the method can be used for connecting the circuit of sub-micron, measures the signal of several GHz frequencies.
The weak point of this method: chip surface must be in naked state (because need to insert probe on wafer, need the encapsulation that must open chip, and remove passivation layer), and probe can only touch top-level metallic, and (chip designer must guarantee that signal of interest can be connected to top-level metallic, or a test point is set on top layer, and is connected on the circuit of low layer metal level).In addition, although the method is very useful when analyzing one single chip, in product test, but cannot detect each chip on every production line, because this method needs manually to arrange and spended time is grown (being generally several hours).
Another similar method is electron beam probing.The method is used is not probe but focused beam.Electron beam direct projection is to metal cords to be detected, and the electronics being then reflected by measurement calculates the electromotive force of metal cords.Survey and compare with microprobe, the advantage of electron beam probing is: without the passivation layer of removing chip surface, and without insert mechanical part (probe) on chip, so measure more fast reliable.But this kind equipment very expensive (millions of dollars), can only detect a device, but also can not be for the production of X-ray inspection X at every turn.
[utility model content]
The purpose of this utility model is to provide the device of the sequential relationship of two kinds of signals in a kind of accurate measurement and report chip, to solve the problems of the technologies described above.
To achieve these goals, the utility model adopts following technical scheme:
In accurate measurement and report chip, a device for the sequential relationship of two kinds of signals, comprises some test storage unit and common circuit; All test storage unit is all connected to common circuit;
Test storage unit comprises the pulse-generating circuit of pulsewidth time delay and the pulse-generating circuit of cycle pulsewidth; Common circuit comprises very first time voltage conversion circuit and the second time voltage change-over circuit;
Time delay, the input end of pulse-generating circuit of pulsewidth connected digital signal line to be measured and reference signal line, time delay, the pulse-generating circuit output terminal of pulsewidth was divided into two-way, the pulse-generating circuit of cycle pulsewidth of leading up to connects very first time voltage conversion circuit, and another road directly connects the second time voltage change-over circuit;
Pulse-generating circuit output terminal and the reference signal line of the input end connection delay time pulsewidth of the pulse-generating circuit of cycle pulsewidth, the output terminal of the pulse-generating circuit of cycle pulsewidth connects very first time voltage conversion circuit.
The utility model further improves and is: time delay, the pulse-generating circuit of pulsewidth was associated for the digital signal to be measured of measurement digital signal line and reference signal line input and reference signal are carried out, output pulse signal t
sIG, pulse signal t
sIGpulsewidth equal the difference of injection time of digital signal to be measured and reference signal.
The utility model further improves and is: the pulse signal t of very first time voltage conversion circuit for the pulse-generating circuit of cycle pulsewidth is exported
cLKbe converted to reference voltage signal; The second time voltage change-over circuit is used for pulse signal t
sIGbe converted to the relevant voltage signal of difference of injection time of digital signal to be measured and reference signal.
The utility model further improves and is: pulse signal t
cLKpulsewidth equal a clock period.
The utility model further improves and is: very first time voltage conversion circuit and test storage units shared NMOS pipe N2, the second time voltage change-over circuit and test storage units shared NMOS pipe N1;
Very first time voltage conversion circuit comprises controllable current source I1, resistance R 1, resistance R 2, operational amplifier 201, resistance R 3 and capacitor C 1; The second time voltage change-over circuit comprises controllable current source I2, resistance R 4 and capacitor C 1; Controllable current source I1 is identical with controllable current source I2 parameter, and resistance R 3 is identical with resistance R 4 parameters, and capacitor C 1 is identical with capacitor C 2 parameters; One end of controllable current source I1 connects high level voltage VDD, other end contact resistance R3 one end, and resistance R 3 other ends connect capacitor C 1 one end, the NMOS pipe drain electrode of N2 and the negative pole of operational amplifier 201, capacitor C 1 other end ground connection; One end of controllable current source I2 connects high level voltage VDD, other end contact resistance R4 one end, and resistance R 4 other ends connect drain electrode and the check point 301 of capacitor C 2 one end, NMOS pipe N1, capacitor C 2 other end ground connection; Resistance R 1 one end connects high level voltage VDD, the positive pole of other end contact resistance R2 one end and operational amplifier 201, resistance R 2 other end ground connection; Pulse signal t
sIGthe grid that connects NMOS pipe N1, the source ground of NMOS pipe N1; Pulse signal t
cLKthe grid that connects NMOS pipe N2, the source ground of NMOS pipe N2.
The utility model further improves and is: the drain voltage of NMOS pipe N2 is Vdd – R1/ (R1+R2) * Vdd, and the drain voltage of NMOS pipe N1 is Vdd – R1/ (R1+R2) * Vdd * t
sIG/ t
cLK.
The device of the sequential relationship of two kinds of signals in chip is accurately measured and report to the utility model, during work, comprises the following steps:
Time delay pulsewidth pulse-generating circuit digital signal to be measured and reference signal are carried out associated, output pulse signal t
sIG, pulse signal t
sIGpulsewidth equal the difference of injection time of digital signal to be measured and reference signal;
The pulse-generating circuit output pulse signal t of cycle pulsewidth
cLK, pulse signal t
cLKpulsewidth equal a clock period;
Very first time voltage conversion circuit is by pulse signal t
cLKbe converted to reference voltage signal; The second time voltage change-over circuit is by pulse signal t
sIGbe converted to the difference of injection time voltage signal of digital signal to be measured and reference signal.
The utility model further improves and is: before measurement, by operational amplifier, regulate controllable current source I1 and controllable current source I2, making the drain voltage of NMOS pipe N2 is Vdd – R1/ (R1+R2) * Vdd, and the drain voltage of NMOS pipe N1 is Vdd – R1/ (R1+R2) * Vdd * t
sIG/ t
cLK.
Accurately measure and report the method for the sequential relationship of two kinds of signals in chip, use switched capacitor network that the difference of injection time between the digital signal to be measured obtaining by duplicate measurements and reference signal is converted to analog voltage.
The utility model further improves and is: the pulse of reference signal is known, and utilizing switched capacitor network is reference voltage with reference to the pulses switch of signal.
The utility model further improves and is: export described analog voltage to test point or pin, and by external measurement devices measuring voltage.
The utility model further improves and is: described analog voltage is delivered to analogue-to-digital converters (ADC), the digital signal finally obtaining as output valve or for chip internal used.
The utility model is a kind of device of the first analog voltage that difference of injection time between two kinds of signals that obtain by duplicate measurements (being uniformly distributed in time) turned and is changed to by switched capacitor network.
System clock) and produce frequency as hereinbefore said apparatus, the second basic pulse pulsewidth of device is known (for example:, utilize switched capacitor network that the second basic pulse is converted to the second analog voltage.
Said apparatus, measure analog voltage, and by itself and reference voltage comparison, the current source of by-pass cock capacitor network, until its voltage mates with reference voltage.
Export the first analog voltage to test point or pin, and by external measurement devices measuring voltage.
Aforementioned means, is delivered to analogue-to-digital converters (ADC) by the first analog voltage, and the digital signal finally obtaining is as output valve or be chip internal (for example: as the input value of adjusting fuse) used.
Aforementioned means, a large amount of test cells share identical simulation benchmark circuit, but only need be to be the regulating circuit measurement that is equipped with of benchmark circuit and test point once (line or configuration).In this case, test cell is provided with enable signal, to accurately select to activate which test storage unit in any given time, and other test cells can not produce driving effect to analog line.
Time Created by the preferred version shown in Fig. 1 for measuring SIG signal, and compared the Time Created of SIG signal with the clock CLK constantly setting out Time Created.
By the delay element removing in the preferred version shown in Fig. 1, circuit is simplified, and reached same carryover effects by the suitable wiring on chip.
In the preferred version shown in Fig. 1, SIG continuous trigger CLK1, and also CLK is also the CLK of second continuous trigger.Removing after three triggers, is the constant driving of n-fet of second benchmark line discharge.
Preferred version shown in Fig. 1 just can be for the delay relation between measuring-signal SIG1 and SIG2 through improving.Using SIG1 as input signal, SIG2 is input to second pulse producer (being before connected with CLK) and system clock CLK as the input of trigger.
In the preferred version shown in Fig. 1, extra marginal detector be arranged on SIG and CLK input end before.Only in two kinds of specific time windows of signal, edge value detected, marginal detector could filter SIG and CLK signal, and enables test cell.In other cases, cannot enable test cell.Extra circuit can be used to measure and both under stable condition, did not have the signal at edge, and (for example: data stream 000011110000 relative 000000001111 contrasts; Only have and assess being positioned at a kind of common translative mode of data bit 8 two kinds of data stream afterwards).
With respect to prior art, the utility model has the advantages that:
The method the utility model proposes can be by being converted into analog voltage by the time interval between two kinds of signal edges, measure two kinds of sequential relationships between signal, can easy detection integrated circuit in the sequential relationship at two groups of internal signals (signal that cannot observe from integrated circuit outside) edge.Analog voltage was directly proportional to the time delay between edge, therefore, can calculate time delay by the voltage of reading.Be positioned near the small-sized measurement module piece of circuit and can produce local voltage, and have measured signal in this circuit.Voltage is transferred to signal bus.Whenever, only some measurement pieces need to be connected with signal bus, all (quantity is not limit) measurement pieces just can share identical signal bus.Afterwards, analog voltage is distributed to test point by chip, so just can use external test facility to measure.Or voltage is transferred to the analogue-to-digital converters (ADC) that are positioned on chip, utilizes ADC measuring voltage, and be digital signal by voltage transitions.Digital signal can be exported, or is stored on chip, for finely tuning setting.
At design verification stage (whether verification design is accurately with firm), sequential relationship detects and time sequence allowance assessment for example, is very important to failure analysis (: understand user between the operating period reason that certain particular device breaks down) and velocity stages (determining that can equipment be classified as higher speed class).
[accompanying drawing explanation]
Fig. 1 is that the schematic diagram of the device of the sequential relationship of two kinds of signals in chip is accurately measured and report to the utility model.
[embodiment]
Below in conjunction with accompanying drawing, embodiment of the present utility model is described further.
The utility model can, by the time interval between two kinds of signal edges is converted into analog voltage, be measured two kinds of sequential relationships between signal.Analog voltage was directly proportional to the time delay between edge, therefore, can calculate time delay by the voltage of reading.
Be positioned near the small-sized measurement module of circuit and can produce local voltage, and have measured signal in this circuit.Voltage is transferred to signal bus.Whenever, only some measurement pieces need to be connected with signal bus, all (quantity is not limit) measurement pieces just can share identical signal bus.Afterwards, analog voltage is distributed to test point by chip, so just can use external test facility to measure.Or voltage is transferred to the analogue-to-digital converters (ADC) that are positioned on chip, utilizes ADC measuring voltage, and be digital signal by voltage transitions.Digital signal can be exported, or is stored on chip, for finely tuning setting.
To introduce in detail a preferred version of the present utility model below.Please note that the method for introducing is in numerous methods, and only at this, is illustrated in order to introduce better the utility model.
Fig. 1 has shown that the utility model is accurately measured and the preferred version of the device of the sequential relationship of the interior two kinds of signals of report chip is simplified wiring diagram.Dotted line inner region represents a local test unit 100.On any one chip, can there is the test storage unit 100(of any amount as shown in Figure 1, a test storage unit 100 is stacked in above another).
Dotted line external circuit is shared by all test cells, and test cell 100 is for example connected to, on this circuit, by " line ": two analog voltage link testers are crossed common circuit and are connected on two test cells 100.Common circuit is analog voltage line charging, and test storage unit 100(is any time, only has a test cell in state of activation) electric discharge.
In a kind of accurate measurement of the utility model and report chip, the device of the sequential relationship of two kinds of signals, comprises a plurality of test storage unit 100 and common circuit; All test storage unit 100 is all connected to common circuit, but while testing, only has a test storage unit 100 in state of activation.Test storage unit 100 comprises the pulse-generating circuit 101 of pulsewidth time delay and the pulse-generating circuit 102 of cycle pulsewidth; Common circuit comprises the very first time (tCLK) voltage conversion circuit 200 and the second time (tSIG) voltage conversion circuit 300.
Time delay, the pulse-generating circuit 101 of pulsewidth connected digital signal SIG to be measured and reference clock signal CLK, associated for digital signal SIG to be measured and reference clock signal CLK are carried out, output pulse signal t
sIG, pulse signal t
sIGpulsewidth equal the difference of injection time of digital signal SIG to be measured and reference clock signal CLK.Time delay pulsewidth the output pulse signal t of pulse-generating circuit 101
sIGbe divided into two-way, the pulse-generating circuit 102 of cycle pulsewidth of leading up to connects the very first time (tCLK) voltage conversion circuits 200, and another road directly connects the second time (tSIG) voltage conversion circuit 300.
The input end of the pulse-generating circuit 102 of cycle pulsewidth connects pulse signal t
sIGwith reference clock signal CLK, output pulse signal t
cLK, pulse signal t
cLKpulsewidth equal a clock period.
The very first time (tCLK) voltage conversion circuit 200 is for by pulse signal t
cLKbe converted to reference voltage signal; The second time (tSIG) voltage conversion circuit 300 is for by pulse signal t
sIGbe converted to the voltage signal that digital signal SIG to be measured is relevant with the difference of injection time of reference clock signal CLK.
The very first time (tCLK) voltage conversion circuit 200 and test storage unit 100 share NMOS pipe N2, and the second time (tSIG) voltage conversion circuit 300 and test storage unit 100 share NMOS pipe N1.
The very first time (tCLK) voltage conversion circuit 200 comprises controllable current source I1, resistance R 1, resistance R 2, operational amplifier 201, resistance R 3 and capacitor C 1; The second time (tSIG) voltage conversion circuit 300 comprises controllable current source I2, resistance R 4 and capacitor C 1; Controllable current source I1 is identical with controllable current source I2 parameter, and resistance R 3 is identical with resistance R 4 parameters, and capacitor C 1 is identical with capacitor C 2 parameters.One end of controllable current source I1 connects high level voltage VDD, other end contact resistance R3 one end, and resistance R 3 other ends connect capacitor C 1 one end, the NMOS pipe drain electrode of N2 and the negative pole of operational amplifier 201, capacitor C 1 other end ground connection; One end of controllable current source I2 connects high level voltage VDD, other end contact resistance R4 one end, and resistance R 4 other ends connect drain electrode and the check point 301 of capacitor C 2 one end, NMOS pipe N1, capacitor C 2 other end ground connection; Resistance R 1 one end connects high level voltage VDD, the positive pole of other end contact resistance R2 one end and operational amplifier 201, resistance R 2 other end ground connection.Pulse signal t
sIGthe grid that connects NMOS pipe N1, the source ground of NMOS pipe N1.Pulse signal t
cLKthe grid that connects NMOS pipe N2, the source ground of NMOS pipe N2; The output terminal of operational amplifier 201 connects controllable current source I1 and controllable current source I2.
The test cell 100 that Fig. 1 shows is for measuring digital signal SIG with respect to the Time Created of CLK.Suppose that CLK is always in switching state, and only just conversion within some cycle of SIG keeps constant within other cycles.Due to SIG conversion, pulse producer can be used for sending the pulse with fixed pulse width.Control signal SEL_RISE_EDGE and SEL_FALL_EDGE only change at rising edge or the negative edge of SIG for selecting.If two kinds of signals are not all set up, cannot activate test cell 100.Through delay matching, this pulse can be used for arranging RS latch 1012.
CLK signal transmits by being similar to the device of pulse producer.Here, only the rising edge by CLK signal produces pulse, and negative edge is not considered, and then, the pulse of generation is reset to (identical with SIG pulse width) RS latch.Attention: delay element 1011 shown here is used for mating the delay on two paths, then regulates respectively negative edge and rise edge delay.According to the actual design/domain of element, also may not need these delay elements.
With respect to the signalization of latch, the reset signal of latch designs byer force.The width of the pulse of RS latch output is corresponding to setting interval of SLK with SIG.
In theory, this signal can directly export the pin of device to, but because signal is again driven and repeatedly amplifies, so be actual like this.If pulse is very narrow, just likely disappear.Otherwise, pulse width just likely changes, so, the relation of the extraneous pulse finally obtaining and the intensity of (technique change) P-channel field-effect transistor (PEFT) transistor (p-fet) on device and N slot field-effect transistor (n-fet) compare with circuit on the relation of width of the initial spike that produces closer.
In order to overcome the restriction of this respect, it is an electric discharge in two analog lines that the utility model is controlled transistor (n-fet) with pulse.The d/d quantity of electric charge is directly proportional to the length of pulse.
The pulse of RS latch output also can be used to produce second level signal, and the width of this pulse is identical with a clock period of CLK signal, and this process completes by 3 triggers, as shown in Figure 1.Attention: only have when RS latch state changes, can produce second level signal, be i.e. the generation of this pulse consistent with discharge pulse originally (Time Created of SIG to CLK).This second level signal is for controlling the n-fet that is responsible for the electric discharge of second analog line.And the d/d quantity of electric charge is directly proportional to the length of pulse, in this case, what we referred to is also a clock period.
Analog line continues charging by adjustable current source.If under enough high-frequencies, electric discharge repeats to occur, and just can measure (approaching) constant voltage on these circuits.
Now, can export two analog voltages on circuit by pin, then user can measure and compare it, and calculates the ratio of pulse length.But, for the quantity of the external pin of use is reduced to one, and amplifying signal, need an extra regulator: the magnitude of voltage that uses operational amplifier (OP-amp) measure analog circuit, this mimic channel is discharged by CLK signal, then itself and R2/ (R1+R2) * Vdd reference value is compared.In addition, OP-amp also can be used to be adjusted to two controllable current sources (I1, I2) of two mimic channel line chargings.
After regulating, once reach equilibrium state, the voltage 103 of clock mimic channel is Vdd – R1/ (R1+R2) * Vdd, and the voltage 104 of second circuit is Vdd – R1/ (R1+R2) * Vdd * t
sIG/ t
cLK.Only have after this magnitude of voltage output, could adopt the external test arrangements measuring voltage at device pin.
The fundamental mechanism that note that this theory is switched capacitor network.While only having the reignition of generation and discharge frequency higher than the time constant of charge path and regulating circuit, this mechanism just works.And during measuring, discharge frequency must remain unchanged.So this is a weak point of the method, it is also a problem of the most easily encountering while adopting repeated test proceeding measurement.If cannot simulate particular electrical circuit to be measured by external testing order, produce repeating signal, just a measurement circuit need to be installed in inside, to produce applicable vector.
Another one weak point is the detected value mean value that always repeated detection draws.Like this, on the one hand, the jitter transfer situation detecting between randomized jitter or two kinds of signals is unlikely, on the other hand, and can be by changing driving factors and carrying out repeated detection and determine the deterministic jitter transfer situation being caused by factors such as different mode and data topology structures.
The preferred version of showing herein has a precondition, that is: SIG signal is (discontinuous switching), for the CLK signal that can switch continuously.
However, the utility model is not limited to the preferred version of introducing herein.
If a) need to compare two kinds of difference of injection time between CLK signal, remove trigger, the circuit in Fig. 1 is just simplified, and this circuit is responsible for second analog line electric discharge (in order to cancel selected test storage unit, still needing enable signal).Because we are two clock signals relatively, will obtain tCLK pulse in each clock period.So, basic pulse is by the tCLK pulse that is each cycle, and in other words, basic pulse is by the pulse signal of constant drive.
B) when more not by the continuous two kinds of signals that switch of clock, circuit shown in Fig. 1 is applicable too, but these two kinds of signal transfer lags are predictable, and afterwards in service, keeps constant (for example: comparison signal by delay situation before circuit block and afterwards) time delay.Like this, a kind of signal just can be used for arranging RS latch, and another kind ofly just can be used for resetting RS latch, and meanwhile, chip CLK is used for producing desired reference value as the third input.These two kinds of signals all can generation state conversion/edge, and this point is very important.If only have a kind of signal can produce an edge, and another kind of signal remains unchanged, and just cannot correctly arrange or reset RS latch, detect so also meaningless.
C) if must two kinds of signals be compared, but but cannot guarantee that these two kinds of signals (for example: SIG1 has changed, and SIG2 is also keeping its polarity all can produce edge; Or SIG1 changed, and SIG2 is the CLK signal that can end), circuit shown in Fig. 1, after improving, can also be used.In this case, if this condition is met, just need to detect the triggering in the cycle and be only used for enabling the situation of RS latch at certain hour of two kinds of signals.From any one edge of signal 1, produce pulse, and produce another pulse from the edge of signal 2, just can complete aforesaid operations.Only have and occur that when overlapping, RS latch just can be enabled, and then utilizes identical inhibit signal to arrange or reset latch when two pulses.
, there is other implementation methods in the signal according to measuring, but please notes that all circuit all can share same analog line, charging circuit and regulator, and only need an external testing pin just can carry out all testings of requirement.
Claims (5)
1. accurately measure and report a device for the sequential relationship of two kinds of signals in chip, it is characterized in that, comprise some test storage unit (100) and common circuit; All test storage unit (100) is all connected to common circuit;
Test storage unit (100) comprises the pulse-generating circuit (101) of pulsewidth time delay and the pulse-generating circuit (102) of cycle pulsewidth; Common circuit comprises very first time voltage conversion circuit (200) and the second time voltage change-over circuit (300);
Time delay, the input end of pulse-generating circuit (101) of pulsewidth connected digital signal line to be measured (SIG) and reference signal line (CLK), time delay, pulse-generating circuit (101) output terminal of pulsewidth was divided into two-way, the pulse-generating circuit (102) of cycle pulsewidth of leading up to connects very first time voltage conversion circuit (200), and another road directly connects the second time voltage change-over circuit (300);
Pulse-generating circuit (101) output terminal of the input end connection delay time pulsewidth of the pulse-generating circuit of cycle pulsewidth (102) and reference signal line (CLK), the output terminal of the pulse-generating circuit of cycle pulsewidth (102) connects very first time voltage conversion circuit (200).
2. the device of sequential relationship of two kinds of signals in accurate measurement according to claim 1 and report chip, it is characterized in that, time delay, the pulse-generating circuit (101) of pulsewidth was associated for the digital signal to be measured of measuring the input of digital signal line (SIG) and reference signal line (CLK) and reference signal are carried out, output pulse signal t
sIG, pulse signal t
sIGpulsewidth equal the difference of injection time of digital signal to be measured and reference signal.
3. the device of the sequential relationship of two kinds of signals in accurate measurement according to claim 2 and report chip, is characterized in that the pulse signal t of very first time voltage conversion circuit (200) for the pulse-generating circuit of cycle pulsewidth (102) is exported
cLKbe converted to reference voltage signal; The second time voltage change-over circuit (300) is for by pulse signal t
sIGbe converted to the relevant voltage signal of difference of injection time of digital signal to be measured and reference signal.
4. the device of the sequential relationship of two kinds of signals in accurate measurement according to claim 2 and report chip, is characterized in that pulse signal t
cLKpulsewidth equal a clock period.
5. the device of sequential relationship of two kinds of signals in accurate measurement according to claim 1 and report chip, it is characterized in that, very first time voltage conversion circuit (200) and test storage unit (100) share NMOS pipe N2, and the second time voltage change-over circuit (300) and test storage unit (100) share NMOS pipe N1;
Very first time voltage conversion circuit (200) comprises controllable current source I1, resistance R 1, resistance R 2, operational amplifier 201, resistance R 3 and capacitor C 1; The second time voltage change-over circuit (300) comprises controllable current source I2, resistance R 4 and capacitor C 1; Controllable current source I1 is identical with controllable current source I2 parameter, and resistance R 3 is identical with resistance R 4 parameters, and capacitor C 1 is identical with capacitor C 2 parameters; One end of controllable current source I1 connects high level voltage VDD, other end contact resistance R3 one end, and resistance R 3 other ends connect capacitor C 1 one end, the NMOS pipe drain electrode of N2 and the negative pole of operational amplifier 201, capacitor C 1 other end ground connection; One end of controllable current source I2 connects high level voltage VDD, other end contact resistance R4 one end, and resistance R 4 other ends connect drain electrode and the check point 301 of capacitor C 2 one end, NMOS pipe N1, capacitor C 2 other end ground connection; Resistance R 1 one end connects high level voltage VDD, the positive pole of other end contact resistance R2 one end and operational amplifier 201, resistance R 2 other end ground connection; Pulse signal t
sIGthe grid that connects NMOS pipe N1, the source ground of NMOS pipe N1; Pulse signal tCLK connects the grid of NMOS pipe N2, the source ground of NMOS pipe N2.
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| WO2020042695A1 (en) * | 2018-08-29 | 2020-03-05 | 郑州云海信息技术有限公司 | Timing test method and device, and vr chip |
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| WO2020042695A1 (en) * | 2018-08-29 | 2020-03-05 | 郑州云海信息技术有限公司 | Timing test method and device, and vr chip |
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