CN203773912U - Gate driving circuit, array substrate row driving circuit and display device - Google Patents
Gate driving circuit, array substrate row driving circuit and display device Download PDFInfo
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- CN203773912U CN203773912U CN201420188070.XU CN201420188070U CN203773912U CN 203773912 U CN203773912 U CN 203773912U CN 201420188070 U CN201420188070 U CN 201420188070U CN 203773912 U CN203773912 U CN 203773912U
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Abstract
The utility model provides a gate driving circuit, an array substrate row driving circuit and a display device. The gate driving circuit is used in a display panel and comprises a driving signal output unit, a driving control unit and a compensation unit. The driving signal output unit is provided with a storage capacitor. The driving control unit is used for sampling an input signal in the first stage of each scanning cycle, causing the driving signal output unit to output a first gate driving signal used for switching on a TFT in the display panel in the second stage of each scanning cycle, and causing the driving signal output unit to use the storage capacitor of which the voltage difference of the two ends is within a predetermined range so as to output a second gate driving signal used for switching off the TFT in the display panel in the third stage of each scanning cycle, and the driving control unit is connected with the driving signal output unit. The compensation unit is used for keeping the voltage difference of the two ends of the storage capacitor within the predetermined range in the third stage of each scanning cycle, and is connected with the driving signal output unit. According to the utility model, key paths which may produce leakage can be inhibited.
Description
Technical field
The utility model relates to display technique field, relates in particular to a kind of gate driver circuit, array base palte horizontal drive circuit and display device.
Background technology
For AMOLED(Active Matrix/Organic Light Emitting Diode, active matrix organic light-emitting diode) the array base palte horizontal drive circuit of display is mainly for generation of pixel circuit row gating signal, this array base palte horizontal drive circuit is in series by multistage gate driver circuit, so the design of gate driver circuit is directly connected to the performance of gate drive signal.For the back plane circuitry that adopts low temperature polycrystalline silicon technology, need to consider the transistorized leakage problem of low temperature polycrystalline silicon, therefore for array base palte horizontal drive circuit, guarantee the voltage of key node, the critical path that may produce electric leakage for inhibition is the important consideration of circuit design.
Utility model content
Fundamental purpose of the present utility model is to provide a kind of gate driver circuit, array base palte horizontal drive circuit and display device, to suppress to produce the critical path of electric leakage.
In order to achieve the above object, the utility model provides a kind of gate driver circuit, for a display panel, comprising:
Be provided with the driving signal output unit of memory capacitance;
Be used at the first stage of each scan period sampled input signal, subordinate phase in each scan period is controlled described driving signal output unit output for the first grid driving signal of the TFT of display panel described in conducting, phase III in each scan period is controlled described driving signal output unit and utilizes the described memory capacitance of both end voltage difference in preset range with output, for closing the second grid of the TFT of described display panel, to drive the driving control unit of signal, is connected with described driving signal output unit;
And the compensating unit of the both end voltage difference that maintains described memory capacitance for the phase III in each scan period in described preset range, is connected with described driving signal output unit.
During enforcement, described first grid drives signal and described second grid to drive signal to export by gate drive signal output terminal;
Described driving control unit is connected with described driving signal output unit with Section Point by first node;
Described memory capacitance, is connected between described first node and described gate drive signal output terminal;
Described driving signal output unit also comprises:
The first output transistor, grid is connected with first node, and first utmost point is connected with first signal output terminal, and second utmost point is connected with described gate drive signal output terminal;
And, the second output transistor, grid is connected with Section Point, and first utmost point is connected with described gate drive signal output terminal, and second utmost point is connected with secondary signal output terminal.
During enforcement, described compensating unit comprises:
The first compensation transistor, grid incoming control signal, first utmost point is connected with described gate drive signal output terminal; Described control signal is controlled the phase III conducting of described the first compensation transistor in each scan period, or described control signal is controlled the phase III of described the first compensation transistor in each scan period every schedule time conducting;
And, the second compensation transistor, grid is connected with described gate drive signal output terminal, and first utmost point is connected with second utmost point of described the first compensation transistor, and second utmost point is connected with described first node.
During enforcement, described driving control unit comprises:
Input transistors, grid accesses the first clock signal, and first utmost point accesses described input signal, and second utmost point is connected with described first node;
The first drive control transistor, grid and first utmost point access described the first clock signal, and second utmost point is connected with described Section Point;
And, the second drive control transistor, grid is connected with described first node, and first utmost point is connected with described Section Point, and second utmost point accesses described the first clock signal.
During enforcement, gate driver circuit described in the utility model also comprises:
Current potential maintains electric capacity, is connected between described Section Point and described secondary signal output terminal, maintains the current potential of described Section Point for the phase III in each scan period.
The utility model also provides a kind of array base palte horizontal drive circuit, comprises multistage above-mentioned gate driver circuit;
Except first order driving circuit, each stage drive circuit for receiving the input end of input signal and the gate drive signal output terminal of adjacent upper level driving circuit is connected.
The utility model also provides a kind of display device, comprises above-mentioned array base palte horizontal drive circuit.
During enforcement, described display device is active matrix organic light-emitting diode AMOLED display device.
Compared with prior art, gate driver circuit described in the utility model, array base palte horizontal drive circuit and display device have adopted compensating unit, voltage difference with the phase III by each scan period by maintaining memory capacitance two ends is in preset range, so that drive signal output unit output to drive signal for closing the second grid of the TFT of described display panel, thereby reduced the impact of electric leakage.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the first embodiment of gate driver circuit described in the utility model;
Fig. 2 is the structural representation of the second embodiment of gate driver circuit described in the utility model;
Fig. 3 is the structural representation of the 3rd embodiment of gate driver circuit described in the utility model;
Fig. 4 is the circuit diagram of the 4th embodiment of gate driver circuit described in the utility model;
Fig. 5 is the circuit diagram of the 5th embodiment of gate driver circuit described in the utility model;
Fig. 6 is the working timing figure of the 5th embodiment of gate driver circuit described in the utility model;
Fig. 7 is the structured flowchart of the array base palte horizontal drive circuit described in the utility model embodiment.
Embodiment
As shown in Figure 1, the first embodiment of gate driver circuit described in the utility model, comprising:
Be provided with the driving signal output unit 11 of memory capacitance (not showing in Fig. 1);
Driving control unit 12, be used at the first stage of each scan period sampled input signal, subordinate phase in each scan period is controlled described driving signal output unit 11 outputs for the first grid driving signal of the TFT of display panel described in conducting, and the phase III in each scan period is controlled described driving signal output unit 11 and utilizes the described memory capacitance of both end voltage difference in preset range for closing the second grid of the TFT of described display panel, to drive signal with output;
And, compensating unit 13, the both end voltage difference that is used for maintaining described memory capacitance in the phase III of each scan period is in described preset range, so that described driving signal output unit 11 keeps output to drive signal for closing the second grid of the TFT of described display panel.
The first embodiment of gate driver circuit described in the utility model has adopted compensating unit 13, voltage difference with the phase III by each scan period by maintaining memory capacitance two ends is in preset range, so that drive signal output unit 11 outputs to drive signal for closing the second grid of the TFT of described display panel, thereby reduced the impact of electric leakage.
In the utility model embodiment, first stage is the input sample stage, subordinate phase is output stage, phase III comprise reseting stage in each scan period and the reseting stage in each scan period to the input sample in adjacent next scan period the time period between the stage, the compensating unit of not sampling in the prior art, can produce because electric leakage makes to drive signal can not guarantee to close the situation of the TFT in described display panel at described phase III second grid, the utility model embodiment has designed this compensating unit thus, with the impact of avoiding electric leakage to produce.
The transistor adopting in all embodiment of the utility model can be all thin film transistor (TFT) or field effect transistor or the identical device of other characteristics.In the utility model embodiment, for distinguishing transistor the two poles of the earth except grid, wherein a utmost point is called source electrode, and another utmost point is called drain electrode.In addition, according to transistorized characteristic, distinguish and transistor can be divided into N-shaped transistor or p-type transistor.In the driving circuit providing at the utility model embodiment; concrete is that those skilled in the art can expect easily not making under creative work prerequisite while adopting N-shaped transistor or p-type transistor to realize, therefore also in embodiment protection domain of the present utility model.
In the driving circuit providing at the utility model embodiment, N-shaped transistorized first can be extremely source electrode, and N-shaped transistorized second can be extremely drain electrode; P-type transistorized first can be extremely drain electrode, and p-type transistorized second can be extremely source electrode.
First embodiment of the second embodiment of gate driver circuit described in the utility model based on gate driver circuit described in the utility model.As shown in Figure 2, concrete, in the second embodiment of gate driver circuit described in the utility model,
Described first grid drives signal and described second grid to drive signal by gate drive signal output terminal G[n] output;
Described driving control unit 12 is connected with described driving signal output unit 11 with Section Point N2 by first node N1;
Described driving signal output unit 11 comprises:
Memory capacitance C1, is connected in described first node N1 and described gate drive signal output terminal G[n] between;
The first output transistor T1, grid is connected with first node N1, first utmost point is connected with first signal output terminal V1, second utmost point and described gate drive signal output terminal G[n] be connected;
And, the second output transistor T2, grid is connected with Section Point N2, first utmost point and described gate drive signal output terminal G[n] be connected, second utmost point is connected with secondary signal output terminal V2.
In the second embodiment of gate driver circuit described in the utility model as shown in Figure 2, T1 and T2 adopt p-type TFT.
Second embodiment of the 3rd embodiment of gate driver circuit described in the utility model based on gate driver circuit described in the utility model, in the specific implementation, in the 3rd embodiment of gate driver circuit described in the utility model, as shown in Figure 3, described compensating unit 13 comprises:
The first compensation transistor TC1, grid incoming control signal Ctrl, first utmost point and described gate drive signal output terminal G[n] be connected; Described control signal Ctrl controls the phase III conducting of described the first compensation transistor TC1 in each scan period, or described control signal Ctrl controls the described phase III of the first compensation transistor TC1 in each scan period every schedule time conducting;
And, the second compensation transistor TC2, grid and described gate drive signal output terminal G[n] be connected, first utmost point is connected with second utmost point of described the first compensation transistor TC1, and second utmost point is connected with described first node N1.
When gate driver circuit is as shown in Figure 3 during in work, TC1 and TC2 can realize the phase III in each scan period, G[n] gate drive signal of output unidirectional anti-shake.
Three embodiment of the 4th embodiment of gate driver circuit described in the utility model based on gate driver circuit described in the utility model.In the specific implementation, in the 4th embodiment of gate driver circuit described in the utility model, as shown in Figure 4, described driving control unit comprises:
Input transistors TI, grid accesses the first clock signal clk, and first utmost point accesses described input signal, and second utmost point is connected with described first node N1;
Described input signal is inputted by input end INPUT;
The first drive control transistor TD1, grid and first utmost point access described the first clock signal clk, and second utmost point is connected with described Section Point;
And, the second drive control transistor TD2, grid is connected with described first node N1, and first utmost point is connected with described Section Point N2, and second utmost point accesses described the first clock signal clk.
Preferably, as shown in Figure 4, the 4th embodiment of gate driver circuit described in the utility model also comprises:
Current potential maintains capacitor C 2, is connected between described Section Point N2 and described secondary signal output terminal V2, maintains the current potential of described Section Point N2 for the phase III in each scan period.
Four embodiment of the 5th embodiment of gate driver circuit described in the utility model based on gate driver circuit described in the utility model, as shown in Figure 5, in the 5th embodiment of gate driver circuit described in the utility model,
Described first signal output terminal V1 output second clock signal CLKB;
Described second clock signal CLKB and described the first clock signal clk are anti-phase;
Described secondary signal output terminal V2 output high level VGH;
Described control signal Ctrl is the first clock signal clk;
Described input end INPUT and adjacent upper level gate driver circuit gate drive signal output terminal G[n-1] be connected.
Fig. 6 is the working timing figure of the 5th embodiment of gate driver circuit described in the utility model.
As shown in Figure 6, in the input sample stage, INPUT output low level, CLK is that potential value is the low level signal of VGL, CLKB is that potential value is the high level signal of VGH, input transistors TI conducting, the level that now N1 is ordered is pulled down to VGL+ ∣ Vthp ∣ (Vthp is the threshold voltage of p-type TFT) accordingly; Now, the equal conducting of TD1 and TD2, N2 point current potential is low level, so T2 conducting, G[n] output high level VGH.And now because N1 point current potential is low level, T1 conducting, CLKB is also high level signal, thereby has guaranteed G[n] output high level.Now C1 is recharged, and input signal is sampled, and the voltage difference at C1 two ends is VGH – VGL-∣ Vthp ∣.
At output stage, INPUT output low level VGL, CLK is that potential value is the high level signal of VGH, TI is due to the boot strap of memory capacitance C1, N1 point can be dragged down to the ∣ into 2VGL+ ∣ Vthp, therefore T2 conducting, CLKB is that potential value is the low level signal of VGL, now G[n] output low level VGL, the low level that now N1 is ordered has been guaranteed TD2 conducting, N2 point is high level by set again, and T2 also closes, can be to output G[n] exert an influence.
Stage within reseting stage and this scan period after reseting stage (from reseting stage until next time INPUT become the stage between low level signal): CLK is that potential value is the low level signal of VGL, T2 conducting, INPUT is high level signal, the current potential that corresponding N1 is ordered will be drawn high as high level, TD2 closes, CLK is low level signal simultaneously, TD1 conducting, the current potential that N2 is ordered is dragged down, T2 conducting, G[n] gate drive signal of output drawn high again as high level, realizes the reset of output; At this stage C2, having kept the current potential that N2 is ordered is low level, thereby has guaranteed T1 conducting, makes G[n] output gate drive signal remain high level, increased the stability of gate drive signal; TC1 and TC2 realize G[n] gate drive signal unidirectional anti-shake of output.
TC1 and TC2 realize G[n] the unidirectional anti-shake concrete implementation of gate drive signal of output is as follows: the stage within reseting stage and this scan period after reseting stage, if G[n] output gate drive signal because N1 point current potential by path, leak electricity and can not remain on noble potential VGH, for TC1, the poor Vgs of gate source voltage (TC1)=V (CLK)-V of TC1 (G[n]), at the current potential of CLK when being low level, the situation that may occur TC1 conducting, its drain voltage is Vd (TC1)=G[n] ', G[n] ' with respect to G[n] there is certain time delay.Now the grid of TD1 and source class are connected respectively to G[n] and G[n] ', transistor T D1 also there will be situation about being switched on, and high potential signal can be write node N1 again, refreshes the duty of T1, reduces the impact of electric leakage.In order to improve the sensitivity of circuit, the breadth length ratio of the breadth length ratio of the raceway groove of transistor T D1 and the raceway groove of TD2 will design by calculating accurately, very little to guarantee the threshold voltage of TD1 and TD2.
As shown in Figure 7, the utility model also provides a kind of array base palte horizontal drive circuit, comprises multistage above-mentioned gate driver circuit;
Except first order driving circuit, each stage drive circuit for receiving the input end INPUT of input signal and the gate drive signal output terminal of adjacent upper level driving circuit is connected;
The input end INPUT access start signal STV of first order gate driver circuit STAGE_1;
In Fig. 7, STAGE_1 indication first order gate driver circuit, STAGE_2 indication second level gate driver circuit, STAGE_3 indication third level gate driver circuit, STAGE_N indicates N level gate driver circuit, STAGE_N-1 indicates N-1 level gate driver circuit, wherein N is greater than 4 integer, G[1] be the gate drive signal output terminal of STAGE_1, G[2] be the gate drive signal output terminal of STAGE_2, G[3] be the gate drive signal output terminal of STAGE_3, G[N-1] be the gate drive signal output terminal of STAGE_N-1, G[N] be the gate drive signal output terminal of STAGE_N.
The utility model also provides a kind of display device, comprises above-mentioned array base palte horizontal drive circuit.
Preferably, described display device is AMOLED display device.
More than illustrate the utility model just illustrative; and it is nonrestrictive; those of ordinary skills understand; in the situation that do not depart from the spirit and scope that claims limit; can make many modifications, variation or equivalence, but all will fall in protection domain of the present utility model.
Claims (8)
1. a gate driver circuit, is characterized in that, comprising:
Be provided with the driving signal output unit of memory capacitance;
Be used at the first stage of each scan period sampled input signal, subordinate phase in each scan period is controlled described driving signal output unit output for the first grid driving signal of the TFT of display panel described in conducting, phase III in each scan period is controlled described driving signal output unit and utilizes the described memory capacitance of both end voltage difference in preset range with output, for closing the second grid of the TFT of described display panel, to drive the driving control unit of signal, is connected with described driving signal output unit;
And the compensating unit of the both end voltage difference that maintains described memory capacitance for the phase III in each scan period in described preset range, is connected with described driving signal output unit.
2. gate driver circuit as claimed in claim 1, is characterized in that,
Described first grid drives signal and described second grid to drive signal to export by gate drive signal output terminal;
Described driving control unit is connected with described driving signal output unit with Section Point by first node;
Described memory capacitance, is connected between described first node and described gate drive signal output terminal;
Described driving signal output unit also comprises:
The first output transistor, grid is connected with first node, and first utmost point is connected with first signal output terminal, and second utmost point is connected with described gate drive signal output terminal;
And, the second output transistor, grid is connected with Section Point, and first utmost point is connected with described gate drive signal output terminal, and second utmost point is connected with secondary signal output terminal.
3. gate driver circuit as claimed in claim 2, is characterized in that, described compensating unit comprises:
The first compensation transistor, grid incoming control signal, first utmost point is connected with described gate drive signal output terminal; Described control signal is controlled the phase III conducting of described the first compensation transistor in each scan period, or described control signal is controlled the phase III of described the first compensation transistor in each scan period every schedule time conducting;
And, the second compensation transistor, grid is connected with described gate drive signal output terminal, and first utmost point is connected with second utmost point of described the first compensation transistor, and second utmost point is connected with described first node.
4. gate driver circuit as claimed in claim 2 or claim 3, is characterized in that, described driving control unit comprises:
Input transistors, grid accesses the first clock signal, and first utmost point accesses described input signal, and second utmost point is connected with described first node;
The first drive control transistor, grid and first utmost point access described the first clock signal, and second utmost point is connected with described Section Point;
And, the second drive control transistor, grid is connected with described first node, and first utmost point is connected with described Section Point, and second utmost point accesses described the first clock signal.
5. gate driver circuit as claimed in claim 4, is characterized in that, also comprises:
Current potential maintains electric capacity, is connected between described Section Point and described secondary signal output terminal, maintains the current potential of described Section Point for the phase III in each scan period.
6. an array base palte horizontal drive circuit, is characterized in that, comprises multistage gate driver circuit as described in arbitrary claim in claim 1 to 5;
Except first order driving circuit, each stage drive circuit for receiving the input end of input signal and the gate drive signal output terminal of adjacent upper level driving circuit is connected.
7. a display device, is characterized in that, comprises array base palte horizontal drive circuit as claimed in claim 6.
8. display device as claimed in claim 7, is characterized in that, described display device is active matrix organic light-emitting diode AMOLED display device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420188070.XU CN203773912U (en) | 2014-04-17 | 2014-04-17 | Gate driving circuit, array substrate row driving circuit and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420188070.XU CN203773912U (en) | 2014-04-17 | 2014-04-17 | Gate driving circuit, array substrate row driving circuit and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203773912U true CN203773912U (en) | 2014-08-13 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201420188070.XU Withdrawn - After Issue CN203773912U (en) | 2014-04-17 | 2014-04-17 | Gate driving circuit, array substrate row driving circuit and display device |
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| CN (1) | CN203773912U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015158101A1 (en) * | 2014-04-17 | 2015-10-22 | 京东方科技集团股份有限公司 | Gate driving circuit and method, array substrate row driving circuit and display device |
-
2014
- 2014-04-17 CN CN201420188070.XU patent/CN203773912U/en not_active Withdrawn - After Issue
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015158101A1 (en) * | 2014-04-17 | 2015-10-22 | 京东方科技集团股份有限公司 | Gate driving circuit and method, array substrate row driving circuit and display device |
| US9489896B2 (en) | 2014-04-17 | 2016-11-08 | Boe Technology Group Co., Ltd. | Gate driving circuit and gate driving method, gate driver on array (GOA) and display device |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20140813 Effective date of abandoning: 20170329 |
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| AV01 | Patent right actively abandoned |