CN203747906U - Signal conversion device - Google Patents
Signal conversion device Download PDFInfo
- Publication number
- CN203747906U CN203747906U CN201320345824.3U CN201320345824U CN203747906U CN 203747906 U CN203747906 U CN 203747906U CN 201320345824 U CN201320345824 U CN 201320345824U CN 203747906 U CN203747906 U CN 203747906U
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- Prior art keywords
- data
- chromacoder
- fpga
- view data
- chip
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- Expired - Lifetime
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Abstract
The utility model belongs to a conversion device, and specifically relates to a signal conversion device. The device comprises an FPGA serving as the core of the device. The device also comprises an image data receiving end for receiving one-way LVDS image data, and a data transmitting end for transmitting camera-link protocol data. The FPGA receives data from the image data receiving end, and transmits the converted signal to the image data transmitting end. The device also comprises a double-port RAM which is in signal connection with the image data receiving end and the FPGA. The device also comprises a power supply which supplies power to all electric equipment. The beneficial effects of the utility model are that the device can convert the one-way LVDS image data into the camera-link protocol image data; and the device is simple in structure, is low in energy consumption, and is convenient for maintenance.
Description
Technical field
This novel conversion equipment that belongs to, is specifically related to a kind of chromacoder.
Background technology
Along with the increase of amount of image information, the rate requirement of image transmitting storage is more and more faster.Camera-link agreement is born on this basis, and its message transmission rate can reach 2.83Gbps.Image capture device based on camera-link agreement is also more and more applied.But generally single channel LVDS video transmission protocol and the camera-link agreement of application are all incompatible from hardware interface or communications protocol before, bring problem to IMAQ and NETD test etc.
In prior art, there is no the conversion equipment that single channel LVDS video transmission protocol is mated with camera-link agreement.
Summary of the invention
This novel object is the defect for prior art, and a kind of chromacoder is provided.
This is novel is achieved in that a kind of chromacoder, comprise the FPGA as chromacoder core, for receiving the view data receiving terminal of single channel LVDS view data and for transmitting the data sending terminal of camera-link protocol data, FPGA receives data from view data receiving terminal, and FPGA sends to view data transmitting terminal by the signal of having changed; This device also comprises dual port RAM, and dual port RAM is connected with the equal signal of FPGA with view data receiving terminal, and chromacoder also comprises power supply, and power supply is all power consumption equipment power supplies.
A kind of chromacoder as above, wherein, described view data receiving terminal comprises for receiving the socket of data, the data receiver chip being connected with socket.
A kind of chromacoder as above, wherein, what data receiver chip was selected is the MAX9248 chip of Maxim.
A kind of chromacoder as above, wherein, described view data transmitting terminal comprises data pio chip, with the socket being connected with data pio chip.
A kind of chromacoder as above, wherein, what described data pio chip was selected is the DS90CR287 chip that National Semiconductor produces.
This novel beneficial effect is: with the application's device, the view data of single channel LVDS agreement can be converted to the view data of camera-link agreement, and the application is simple in structure, power consumption is few, maintains easily.
Accompanying drawing explanation
Fig. 1 is the hardware structure diagram of a kind of chromacoder of providing of the application.
Embodiment
As shown in Figure 1, a kind of chromacoder, comprise the FPGA as chromacoder core, for receiving the view data receiving terminal of single channel LVDS view data and for transmitting the data sending terminal of camera-link protocol data, FPGA receives data from view data receiving terminal, and FPGA sends to view data transmitting terminal by the signal of having changed; This device also comprises dual port RAM, and dual port RAM is connected with the equal signal of FPGA with view data receiving terminal, and chromacoder also comprises power supply, and power supply is all power consumption equipment power supplies.
Described view data receiving terminal comprises for receiving the socket of data, the data receiver chip being connected with socket.
What data receiver chip was selected is the MAX9248 chip of Maxim.
Described view data transmitting terminal comprises data pio chip, with the socket being connected with data pio chip.
What described data pio chip was selected is the DS90CR287 chip that National Semiconductor produces.
The object that the application arranges dual port RAM is, in order to solve single channel LVDS video transmission protocol and the unmatched problem of camera-link agreement clock.While occurring that in data conversion process unmatched situation occurs, data are just carried out buffer memory by dual port RAM, thereby have solved the unmatched problem of clock.
Claims (5)
1. a chromacoder, it is characterized in that: comprise the FPGA as chromacoder core, for receiving the view data receiving terminal of single channel LVDS view data and for transmitting the data sending terminal of camera-link protocol data, FPGA receives data from view data receiving terminal, and FPGA sends to view data transmitting terminal by the signal of having changed; This device also comprises dual port RAM, and dual port RAM is connected with the equal signal of FPGA with view data receiving terminal, and chromacoder also comprises power supply, and power supply is all power consumption equipment power supplies.
2. a kind of chromacoder as claimed in claim 1, is characterized in that: described view data receiving terminal comprises for receiving the socket of data, the data receiver chip being connected with socket.
3. a kind of chromacoder as claimed in claim 2, is characterized in that: what data receiver chip was selected is the MAX9248 chip of Maxim.
4. a kind of chromacoder as claimed in claim 3, is characterized in that: described view data transmitting terminal comprises data pio chip, with the socket being connected with data pio chip.
5. a kind of chromacoder as claimed in claim 4, is characterized in that: what described data pio chip was selected is the DS90CR287 chip that National Semiconductor produces.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320345824.3U CN203747906U (en) | 2013-06-17 | 2013-06-17 | Signal conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320345824.3U CN203747906U (en) | 2013-06-17 | 2013-06-17 | Signal conversion device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203747906U true CN203747906U (en) | 2014-07-30 |
Family
ID=51347653
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320345824.3U Expired - Lifetime CN203747906U (en) | 2013-06-17 | 2013-06-17 | Signal conversion device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203747906U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107197120A (en) * | 2017-05-27 | 2017-09-22 | 电子科技大学 | Image source compatibility testing method and system |
-
2013
- 2013-06-17 CN CN201320345824.3U patent/CN203747906U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107197120A (en) * | 2017-05-27 | 2017-09-22 | 电子科技大学 | Image source compatibility testing method and system |
| CN107197120B (en) * | 2017-05-27 | 2019-08-13 | 电子科技大学 | Image source compatibility testing method and system |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140730 |