CN203747769U - Quick comparison circuit - Google Patents

Abstract

The utility model discloses a quick comparison circuit, which comprises N levels of cascaded operational amplifiers, a latch, a biasing circuit and a control signal generating circuit, wherein N is greater than or equal to two. Two differential signals requiring to be compared are inputted into the input end of the first level operational amplifier, the output end of the Nth level operational amplifier is connected with the input end of the latch, the biasing circuit provides bias current for the amplifiers, the control signal producing circuit is connected with the N levels of operational amplifiers and the latch and provides an operation time sequence and rest control signals for the N levels of operational amplifiers and the latch, and the operational amplifiers are identical in structure feature. The quick comparison circuit disclosed by the utility model not only ensures high gain, but also improves the comparison speed.

Description

Quick comparison circuit

Technical field

The utility model relates to integrated circuit fields, relates more specifically to a kind of quick comparison circuit.

Background technology

Comparison circuit is widely used in analog signal in the transfer process of digital signal, and in analog-to-digital conversion, in process, the signal process operational amplifier after being sampled or comparator are to determine the digital value of analog signal.And operational amplifier mostly adopts open loop mode, this pattern needn't compensate operational amplifier, makes the operational amplifier of not compensated can obtain larger bandwidth and higher frequency response.Yet notoriously, conditioning each other between the gain of amplifier and speed, makes to realize high speed and high accuracy under certain process conditions more difficult simultaneously.

Therefore, be necessary to provide improved quick comparison circuit to overcome above-mentioned defect.

Utility model content

The purpose of this utility model is to provide a kind of quick comparison circuit, and quick comparison circuit of the present utility model has not only guaranteed high-gain, and has improved relatively speed.

For achieving the above object, the utility model provides a kind of quick comparison circuit, it comprises the N level operational amplifier of cascade, latch, biasing circuit and control signal produce circuit, N >=2, need the input of two differential signal input first order operational amplifiers relatively, the output of N level operational amplifier is connected with the input of described latch, described biasing circuit provides bias current for operational amplifiers at different levels and described control signal produce circuit, described control signal produces circuit and is connected with N level operational amplifier and latch respectively, described control signal produces circuit and provides work schedule and reseting controling signal for described N level operational amplifier and latch, wherein, operational amplifiers at different levels have identical architectural feature, and operational amplifiers at different levels include the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor and the 8th field effect transistor, a differential signal is inputted the grid of described the first field effect transistor, another differential signal is inputted the grid of described the second field effect transistor, the grid of the drain electrode of described the first field effect transistor and described the 3rd field effect transistor, the drain electrode of drain electrode and described the 5th field effect transistor connects, and output is by a differential signal after amplifying when prime operational amplifier, the grid of the drain electrode of described the second field effect transistor and described the 6th field effect transistor, the drain electrode of drain electrode and described the 4th field effect transistor connects, and output is by another differential signal after amplifying when prime operational amplifier, described the first field effect transistor is jointly connected and is connected with described biasing circuit with the source electrode of the second field effect transistor, described the 3rd field effect transistor, the 4th field effect transistor, the source electrode of the 5th field effect transistor and the 6th field effect transistor is all connected with external power source, the grid of described the 3rd field effect transistor is connected with the grid level of described the 4th field effect transistor, the grid of described the 5th field effect transistor is connected with the grid of described the 6th field effect transistor, the source electrode of described the 7th field effect transistor, the grid of the 8th field effect transistor, drain electrode is all connected with the drain electrode of described the first field effect transistor, the source electrode of described the 8th field effect transistor, the grid of the 7th field effect transistor, drain electrode is all connected with the drain electrode of described the second field effect transistor.

Preferably, operational amplifiers at different levels all also comprise reset switch, one end of described reset switch is connected with the drain electrode of described the first field effect transistor, and the other end is connected with the drain electrode of described the second field effect transistor, and the control end of described reset switch is connected with described control signal generation circuit.

Preferably, described reset switch is closed when the voltage of its control end is high level, during low level, disconnects.

Preferably, described the 4th field effect transistor has identical breadth length ratio with the 5th field effect transistor.

Preferably, described the 7th field effect transistor has identical breadth length ratio with the 8th field effect transistor.

Compared with prior art, amplifier circuit of the present utility model, by described the 4th field effect transistor and the 5th field effect transistor, can make voltage fast rise or the fast-descending when two differential signals of prime operational amplifier output, accelerate the amplification speed to input differential signal, also improved relatively speed; The diode connected mode that described the 7th field effect transistor and the 8th field effect transistor form, carries out clamper to the differential signal of amplifier outputs at different levels, has limited the amplitude of oscillation of output difference sub-signal, has further improved relatively speed.

By following description also by reference to the accompanying drawings, it is more clear that the utility model will become, and these accompanying drawings are used for explaining the utility model.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of the quick amplifying circuit of the utility model.

Fig. 2 is the circuit structure diagram of operational amplifiers at different levels shown in Fig. 1.

Embodiment

With reference now to accompanying drawing, describe embodiment of the present utility model, in accompanying drawing, similarly element numbers represents similar element.As mentioned above, the utility model provides a kind of quick comparison circuit, and quick comparison circuit of the present utility model has not only guaranteed high-gain, and has improved relatively speed.

Please refer to Fig. 1, Fig. 1 is the structured flowchart of the quick amplifying circuit of the utility model.As shown in the figure, quick comparison circuit of the present utility model comprises the N level operational amplifier of cascade, latch, biasing circuit and control signal produce circuit, N >=2, need two differential signal VP relatively, the input of VN input first order operational amplifier, the output of described first order operational amplifier is connected with the input of described second level operational amplifier, the output of described second level operational amplifier is connected with the input of described third level operational amplifier, the rest may be inferred, until the output of described N-1 level operational amplifier is connected with the input of described N level operational amplifier, thereby the large devices of computing of putting at different levels amplify successively to two differential signal VP, the VN of input, be amplified to the size that described latch can be identified, thereby in actual use, can be according to the input size of two differential signal VP, VN and the discernible size of latch and the progression of relative set operational amplifier, the concrete value of N is also set, the output of described N level operational amplifier is connected with the input of described latch, and described latch compares and export comparison value VOUT fast to two differential signals of N level operational amplifier output, described biasing circuit produces circuit with operational amplifiers at different levels and described control signal and is connected, think that operational amplifiers at different levels and described control signal produce circuit bias current is provided, thereby guarantee the normal work that operational amplifiers at different levels and described control signal produce circuit, described control signal produces circuit and is connected with N level operational amplifier and latch respectively, described control signal produces circuit and provides work schedule and reseting controling signal for described N level operational amplifier and latch, thereby described control signal produces work and the reset of circuit control described operational amplifiers at different levels and latch.

Particularly, please again in conjunction with reference to figure 2.In the utility model, operational amplifiers at different levels all have identical architectural feature.Wherein, operational amplifiers at different levels have identical architectural feature, and operational amplifier at different levels includes the first field effect transistor M1, the second field effect transistor M2, the 3rd field effect transistor M3, the 4th field effect transistor M4, the 5th field effect transistor M5, the 6th field effect transistor M6, the 7th field effect transistor M7 and the 8th field effect transistor M8.A differential signal Vinp(is when this grade of operational amplifier is first order operational amplifier, described differential signal Vinp is input differential signal VP, when this grade of operational amplifier is other grade of operational amplifier, the signal of the described differential signal Vinp output after previous stage operational amplifier amplifies that is input differential signal VP) input the grid of described the first field effect transistor M1, another differential signal Vinn(is when this grade of operational amplifier is first order operational amplifier, described differential signal Vinn is input differential signal VN, when this grade of operational amplifier is other grade of operational amplifier, the signal of the described differential signal Vinn output after previous stage operational amplifier amplifies that is input differential signal VN) input the grid of described the second field effect transistor M2, thereby differential signal Vinp and Vinn input this grade of operational amplifier by described the first field effect transistor M1 and the second field effect transistor M2 respectively, the drain electrode of described the first field effect transistor M1 is connected with grid, the drain electrode of the 3rd field effect transistor M3, and output is by a differential signal Voutn after amplifying when prime operational amplifier, the drain electrode of described the second field effect transistor M2 is connected with grid, the drain electrode of the 6th field effect transistor M6, and output is by another differential signal Voutp after amplifying when prime operational amplifier, described the first field effect transistor M1 is jointly connected and is connected with described biasing circuit with the source electrode of the second field effect transistor M2, thereby described biasing circuit provides bias current by described the first field effect transistor M1 and the second field effect transistor M2 for this grade of operational amplifier, described the 3rd field effect transistor M3, the 4th field effect transistor M4, the source electrode of the 5th field effect transistor M5 and the 6th field effect transistor M6 is all connected with external power source AVD, the grid of described the 3rd field effect transistor M3 is connected with the grid level of described the 4th field effect transistor M4, the drain electrode of described the 4th field effect transistor M4 is connected with the grid of described the 6th field effect transistor M6, the grid of described the 5th field effect transistor M5 is connected with the grid of described the 6th field effect transistor M6, the source electrode of described the 7th field effect transistor M7, the grid of the 8th field effect transistor M8, drain electrode is all connected with the drain electrode of described the first field effect transistor M1, the source electrode of described the 8th field effect transistor M8, the grid of the 7th field effect transistor M7, drain electrode is all connected with the drain electrode of described the second field effect transistor M2.In preferred implementation of the present utility model, operational amplifiers at different levels all also comprise reset switch S1, one end of described reset switch S1 is connected with the drain electrode of described the first field effect transistor M1, the other end is connected with the drain electrode of described the second field effect transistor M2, and the control end a of described reset switch S1 produces circuit with described control signal and is connected, thereby described control signal produces closure and disconnection that the level of circuit output is controlled described reset switch S1; Wherein, described reset switch S1 is closed when the voltage of its control end a is high level, during low level, disconnects, and when described reset switch S1 is closed, make to reset when prime amplifier amplifier, during disconnection, to being input to the differential signal of this grade of operational amplifier, amplify; Thereby operational amplifiers at different levels amplify successively to differential signal VP and the VN of input.

Please combination, with reference to figure 1 and Fig. 2, is described the operation principle of the quick comparison circuit of the utility model again:

In the utility model, N level operational amplifier need to be amplified to the size that latch can be identified by the differential signal VP of input and VN, thereby can carry out design comparison device by operational amplifier.As stated in the Background Art, the operational amplifier in comparator circuit is generally operational in open loop mode, need to consider bandwidth and the gain of operational amplifier during design, but without the more complicated factors such as the linearity, stability of considering operational amplifier.The N level operational amplifier of quick amplifying circuit of the present utility model is first order pole operational amplifier, and N level operational amplifier cascade composition comparator, and overall gain A is (N is greater than 1 positive integer)

$A=\underset{i=1}{\overset{N}{\mathrm{\Π}}}{A}_i---\left(1\right)$

A wherein _iit is the gain of i level operational amplifier.

Constant settling time of the comparator that the cascade of N level operational amplifier forms is

$\mathrm{\τ}=\underset{i=1}{\overset{N}{\mathrm{\Σ}}}\frac{A_i}{{\mathrm{\ω}}_{\mathrm{ui}}}---\left(2\right)$

ω _uithe unity gain bandwidth that is i level operational amplifier is long-pending.

Reach the overall gain shown in (1) formula, if only adopt one-level operational amplifier, be its settling time so

${\mathrm{\τ}}^{\′}=\frac{\underset{i=1}{\overset{N}{\mathrm{\Π}}}{A}_i}{{\mathrm{\ω}}_u}---\left(3\right)$

ω _ufor the unity gain bandwidth of the one-level operational amplifier of hypothesis long-pending.By (2) (3) formula, relatively can find out τ ' > > τ, therefore adopt multi-stage cascade operational amplifier can greatly reduce amplification, time relatively.

There is negative exponent response characteristic the settling time of N level operational amplifier cascade, but in the utility model, owing to also having connected latch after N level operational amplifier, and have positive exponent response characteristic the settling time of latch, thereby the characteristic of latch positive exponent response can be accelerated the speed of comparison greatly; In addition, when the differential signal VP of input and the difference of VN very hour, it is not enough that described latch also can make up the gain of preposition N level operational amplifier, though make the differential signal VP of input and the difference of VN little, the amplitude that also can be amplified to fast digital circuit and identify.

The structure of every grade of operational amplifier in the N level operational amplifier of the quick amplifying circuit of the utility model is identical, as shown in Figure 2.Wherein Vinp, Vinn are the comparison signal that is loaded into differential input end, Voutn, Voutp are differential output signal, the first field effect transistor M1 and the second field effect transistor M2 are differential pair tube, breadth length ratio is identical, the 3rd field effect transistor M3 to the six field effect transistor M6 form the load with weak positive feedback structure, the 3rd field effect transistor M3 and the 6th field effect transistor M6 breadth length ratio S _3,6identical, the 4th field effect transistor M4 and the 5th field effect transistor M5 breadth length ratio S _4,5identical, and S _3,6> S _4,5; During reset switch S1 high level, switch is closed, to resetting when prime operational amplifier, during low level, disconnects, and makes when prime operational amplifier, the differential signal of input to be amplified; The 7th field effect transistor M7 is connected with diode connected mode with the 8th field effect transistor M8, makes voltage difference clamper between amplifier difference output Voutp, Voutn two ends below the conducting voltage of diode, | Voutp-Voutn|≤V _th(V _thturn-on voltage for diode), restriction output voltage swing, has accelerated relatively speed; And the 7th field effect transistor M7 is identical with the breadth length ratio of the 8th field effect transistor M8, thereby make its conducting voltage identical, the voltage of its clamper is also identical.Particularly: if the signal Vinp>Vinn of difference input, the electric current that the first field effect transistor M1 flows through so strengthens, the electric current that the second field effect transistor M2 flows through reduces, the grid voltage of the 3rd field effect transistor M3 and the 4th field effect transistor M4 reduces, the 5th field effect transistor M5 and the 6th field effect transistor M6 grid voltage raise, now Voutn voltage reduces gradually, Voutp raises gradually, because the 4th field effect transistor M4 grid voltage reduces, the voltage of the 5th field effect transistor M5 raises, so flowing through the electric current of the 4th field effect transistor M4 increases, the electric current of the 5th field effect transistor M5 reduces, thereby the voltage drop speed of Voutn and the rising speed of Voutp have further been accelerated, accelerated when the amplification speed of prime operational amplifier to the differential signal of input.The gain of this operational amplifier is

$\mathrm{Avl}=\frac{g_{m\mathrm{1,2}}}{g_{m\mathrm{3,6}}-g_{m\mathrm{4,5}}}---\left(4\right)$

G in above formula _mrepresent the mutual conductance of field effect transistor, when can find out that by (4) formula the structure adopting with the load of weak positive feedback has improved the gain of operational amplifier, also improved relatively speed.

Reset switch S1 in circuit and the clamp diode consisting of the 7th field effect transistor M7 and the 8th field effect transistor M8 have further improved relatively speed.When reset switch S1 is closed, be to reset, reset switch S1 amplifies, and by before amplification, operational amplifier is resetted at every turn, the state that can remove before amplification improves amplification speed next time.By at two diodes of difference output end clamper, be used for controlling the voltage difference of differential output signal simultaneously.If the difference of the differential output signal after amplifying last is excessive, and when after amplifying, difference output difference sub-signal need to overturn next time, excessive signal upset meeting declines because Slew Rate problem makes reversal rate, has reduced amplification speed.Add after two clamp diodes, limited the amplitude of oscillation of differential output signal, the signal after amplifying makes the difference output end of amplifier | Voup-Voutn| < V _th(V _thbe the threshold voltage of the 7th field effect transistor M7 or the 8th field effect transistor M8, the conducting voltage equally also connecting for diode), now not conducting of diode, does not participate in amplification process; Differential signal after amplifying makes the difference output end of amplifier | Voup-Voutn| > V _thtime, now diode current flow, exports and carries out clamper difference, i.e. signal after amplification | Voup-Voutn|=V _th, by conducting voltage V is rationally set _th, can limit the amplitude of oscillation of output signal, further improve relatively speed.

Above combination most preferred embodiment is described the utility model, but the utility model is not limited to the embodiment of above announcement, and should contain the various modifications of carrying out according to essence of the present utility model, equivalent combinations.

Claims (5)

1. a quick comparison circuit, the N level operational amplifier that comprises cascade, latch, biasing circuit and control signal produce circuit, N >=2, need the input of two differential signal input first order operational amplifiers relatively, the output of N level operational amplifier is connected with the input of described latch, described biasing circuit provides bias current for operational amplifiers at different levels and described control signal produce circuit, described control signal produces circuit and is connected with N level operational amplifier and latch respectively, described control signal produces circuit and provides work schedule and reseting controling signal for described N level operational amplifier and latch, it is characterized in that, operational amplifiers at different levels have identical architectural feature, and operational amplifiers at different levels include the first field effect transistor, the second field effect transistor, the 3rd field effect transistor, the 4th field effect transistor, the 5th field effect transistor, the 6th field effect transistor, the 7th field effect transistor and the 8th field effect transistor, a differential signal is inputted the grid of described the first field effect transistor, another differential signal is inputted the grid of described the second field effect transistor, the grid of the drain electrode of described the first field effect transistor and the 3rd field effect transistor, drain electrode connects, and output is by a differential signal after amplifying when prime operational amplifier, the grid of the drain electrode of described the second field effect transistor and the 6th field effect transistor, drain electrode connects, and output is by another differential signal after amplifying when prime operational amplifier, described the first field effect transistor is jointly connected and is connected with described biasing circuit with the source electrode of the second field effect transistor, described the 3rd field effect transistor, the 4th field effect transistor, the source electrode of the 5th field effect transistor and the 6th field effect transistor is all connected with external power source, the grid of described the 3rd field effect transistor is connected with the grid level of described the 4th field effect transistor, the drain electrode of described the 4th field effect transistor is connected with the grid of described the 6th field effect transistor, the grid of described the 5th field effect transistor is connected with the grid of described the 6th field effect transistor, the source electrode of described the 7th field effect transistor, the grid of the 8th field effect transistor, drain electrode is all connected with the drain electrode of described the first field effect transistor, the source electrode of described the 8th field effect transistor, the grid of the 7th field effect transistor, drain electrode is all connected with the drain electrode of described the second field effect transistor.

2. quick comparison circuit as claimed in claim 1, it is characterized in that, operational amplifiers at different levels all also comprise reset switch, one end of described reset switch is connected with the drain electrode of described the first field effect transistor, the other end is connected with the drain electrode of described the second field effect transistor, and the control end of described reset switch is connected with described control signal generation circuit.

3. quick comparison circuit as claimed in claim 2, is characterized in that, described reset switch is closed when the voltage of its control end is high level, during low level, disconnects.

4. quick comparison circuit as claimed in claim 2, is characterized in that, described the 4th field effect transistor has identical breadth length ratio with the 5th field effect transistor.

5. quick comparison circuit as claimed in claim 2, is characterized in that, described the 7th field effect transistor has identical breadth length ratio with the 8th field effect transistor.