CN203746826U - Chip packaging structure - Google Patents
Chip packaging structure Download PDFInfo
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- CN203746826U CN203746826U CN201420027332.4U CN201420027332U CN203746826U CN 203746826 U CN203746826 U CN 203746826U CN 201420027332 U CN201420027332 U CN 201420027332U CN 203746826 U CN203746826 U CN 203746826U
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- chip
- pad
- insulating barrier
- pads
- packaging structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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Abstract
The utility model relates to a chip packaging structure. The chip packaging structure comprises a first chip, a second chip and a first insulating layer, wherein the surface of the first chip is provided with a plurality of first bonding pads; the area of the second chip is smaller than the area of the first chip, the surface of the second chip is provided with a plurality of second bonding pads, the plurality of second bonding pads correspond to the plurality of first bonding pads in position, and the plurality of second bonding pads on the surface of the second chip and the plurality of first bonding pads on the surface of the first chip are combined together; and the first insulating layer coats the second chip and is combined with the first chip. The chip packaging structure provided by the utility model is high in reliability.
Description
Technical field
The utility model relates to technical field of semiconductors, relates in particular to a kind of chip-packaging structure.
Background technology
Along with the continuous progress of semiconductor chip manufacture, integrated and encapsulation technology, that electronic system shows is gradually multi-functional, the development trend of high-performance and high reliability.For by multiple active block and passive blocks with difference in functionality, and other elements combinations such as MEMS (micro electro mechanical system) (MEMS), optics (Optics) element at same packaging body, become of several functions system or subsystem can be provided, industry has proposed system in package technology.
System in package can be used as a standard cell and assembles for PCB, can be also final electronic product.Different from traditional chip package, system in package not only can be applied to digital system, can also be applied to the fields such as optical communication, transducer and MEMS, and therefore, in fields such as computer, automation, communications industrys, system in package is widely used.
Existing system in package adopts metal lead wire technique, and the pad of chip and chip chamber is carried out to Bonding with metal wire, plays the effect that electricity connects; In addition, existing system in package also adopts and relatively after laminating, uses insulating cement to carry out bonding packaged type the pad of two chips, and still, the encapsulating structure reliability that above-mentioned method for packing forms is poor.
Utility model content
The problem that the utility model solves is prior art chip-packaging structure poor reliability.
For addressing the above problem, the utility model provides a kind of chip-packaging structure, comprising: the first chip, and the surface of described the first chip has multiple the first pads; The second chip, the area of described the second chip is less than the area of described the first chip, the surface of described the second chip has multiple the second pads, described multiple the second pad is corresponding with the position of described multiple the first pads, and corresponding the combining of multiple the first pads of multiple second pads of described the second chip surface and described the first chip surface; The first insulating barrier, described the first insulating barrier by described the second chip coated and with described the first chips incorporate.
Optionally, also comprise: insulation glue-line, between described the first chip surface and described the second chip surface.
Optionally, the area of described the first insulating barrier and described insulation glue-line and described the first chips incorporate face is greater than the area of described the second chip.
Optionally, also comprise: be positioned at multiple the 3rd pads of described the first chip surface, described multiple the 3rd pads are positioned at the part of described the second chip outside the view field of described the first chip surface.
Optionally, also comprise: multiple the first connectors, run through respectively described the first insulating barrier, and connect with the corresponding electricity of described multiple the 3rd pad; Multiple the first metal couplings, are positioned on described the first insulating barrier and with the corresponding electricity of described multiple the first connector and connect.
Optionally, described multiple the first metal coupling height is not less than the first insulating barrier top of coated described the second chip.
Optionally, described the 3rd pad is positioned at the region outside described the first chip surface being covered by described the first insulating barrier, and described the first insulating barrier is filled in the region between described the first chip and the second chip surface.
Optionally, also comprise: the second insulating barrier, cover described first insulating barrier cover described the first chip surface outside region; Multiple the second connectors, run through respectively described the second insulating barrier, and connect with the corresponding electricity of described multiple the 3rd pad respectively; Multiple the second metal couplings, be positioned on described the second insulating barrier and with the corresponding electrical connection of described multiple the second connector.
Optionally, described multiple the second metal coupling height is not less than the first insulating barrier top of coated described the second chip.
Optionally, also comprise: multiple the 3rd metal couplings, lay respectively between described multiple the first pad and described multiple the second pad.
Compared with prior art, technical solutions of the utility model have the following advantages:
In the chip-packaging structure of the utility model embodiment, comprise the first insulating barrier, described the first insulating barrier is coated and is bonded to described the first chip by described the second chip.Strengthen the structural strength of combination between the first chip and the second chip, made the second chip be not easy to come off from the first chip, strengthened the reliability of whole encapsulating structure.
Further, in the chip-packaging structure of the utility model embodiment, also comprise insulating barrier, connector, the 3rd pad being positioned on the first chip is caused on insulating barrier, make metal coupling higher than described the second chip, form perforate without extra on pcb board, and can directly by metal coupling, the encapsulating structure of the first chip and the second chip be bonded to pcb board, simplified technique.
Brief description of the drawings
Fig. 1 is the cross-sectional view of the chip-packaging structure of prior art;
Fig. 2 is the schematic flow sheet of the formation method 100 of the chip-packaging structure of the utility model one embodiment;
Fig. 3 to Fig. 9 is the generalized section of the formation method 100 of the chip-packaging structure shown in Fig. 2 intermediate structure in forming process;
Figure 10 is the schematic flow sheet of the formation method 200 of the chip-packaging structure of another embodiment of the utility model;
Figure 11 to Figure 17 is the generalized section of the formation method 200 of the chip-packaging structure shown in Figure 10 intermediate structure in forming process.
Embodiment
Normally, when two chips of different sizes are carried out to system in package, the connection area between large chip and little chip only has the size of little chip area.Please refer to Fig. 1, Fig. 1 is the cross-sectional view that in prior art, two chips that vary in size carry out system in package, comprising: the first chip 110, and the surface of described the first chip 110 has the first pad 111, the three pads 112; The second chip 120, the area of described the second chip 120 is less than described the first chip 110, the surface of described the second chip 120 has the second pad 121, second pad 121 on described the second chip 120 surfaces and described the first chip 110 surfaces first pad 111 is corresponding combines; Insulating cement 130, in the space between described the first chip 110 surfaces and the second chip 120 surfaces, for bonding described the first chip 110 and described the second chip 120; Tin ball 140, is positioned on described the 3rd pad 112, for being connected with external circuit (as pcb board) electricity.Because the area of described the second chip 120 is less than the area of described the first chip 110, the area of insulating cement 130 is only suitable with the area of described the second chip 120, cause the bonding force between described the first chip 110 and described the second chip 120 lower, the reliability of encapsulating structure reduces.Especially in fall-down test, the connection between the first chip 110 and the second chip 120 easily comes off.
Based on above research, the utility model proposes a kind of chip-packaging structure, can strengthen two bonding forces between chip.
For above-mentioned purpose of the present utility model, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, specific embodiment of the utility model is described in detail.
It should be noted that, the object that these accompanying drawings are provided is to contribute to understand embodiment of the present utility model, and should not be construed as restriction improperly of the present utility model.For the purpose of clearer, size shown in figure not drawn on scale, may make and amplify, dwindle or other changes.
Please refer to Fig. 2, Fig. 2 shows the schematic flow sheet of the formation method 100 of an embodiment chips encapsulating structure.The step of the formation method 100 below in conjunction with accompanying drawing to chip-packaging structure of the present utility model describes.
Step S101, with reference to figure 3, provides the first chip 210, and the surface of described the first chip 210 has multiple the first pads 211 and multiple the 3rd pad 212.The second chip 220 is provided, the surface of described the second chip 220 has multiple the second pads 221, described multiple the second pad 221 is corresponding with the position of described multiple the first pads 211, and the area of described the second chip 220 is less than the area of described the first chip 210.
Described the first chip 210 and described the second chip 220 can be monocrystalline silicon, SOI(silicon-on-insulator), SiGe or III-V compound material.Described the first chip 210 and described the second chip 220 comprise the semiconductor device, metal interconnect structure and other semiconductor structures that are made in wherein.The scope that described the first chip 210 and described the second chip 220 comprise a broad sense, comprise the integrated circuit (IC) chip such as such as processor, memory and controller, also comprise other sensor chips such as the such as optical sensor chip such as CCD, cmos image sensor or heat sensor chip, motion sensor chip, also comprise microcomputer electric component (MEMS) chip etc.Described the first pad 211, described the second pad 221 or described the 3rd pad 212 can be respectively the top-level metallic electrode of described the first chip 210 or the second chip 220, and described the first pad 211, the second pad 221 or described the 3rd pad 212 can also be redistributing layer (RDL).Described redistributing layer distributes interconnection line or electrode in the first chip 210 or in the second chip 220 on the surface of described the first chip 210 or the second chip 220 again, to meet the design rule of packaging technology.The material of described the first pad 211, the second pad 221 or the 3rd pad 212 can be gold, copper, aluminium or silver.The quantity of described the first pad 211, the second pad 221 or the 3rd pad 212 can be multiple.
In the present embodiment, described the second pad 221 is redistributing layer with described the first pad 211, so that described the second pad 221 is corresponding with the position of described the first pad 211.Described the 3rd pad 212 is positioned at first peripheral chip 210 surfaces of described the first pad 211, after by described the first pad 211 and the corresponding combination of the second pad 221, because the area of described the second chip 220 is less than the area of described the first chip 210, make described the 3rd pad 212 be positioned at the region of described the second chip 220 outside described the first chip 210 surface projection regions.
Step S102, with reference to figure 4, by multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding combines
In certain embodiments, by multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding combine before, also chip is carried out to reduction processing, to reduce the thickness of overall package structure.Described reduction processing is technique well-known to those skilled in the art, does not repeat them here.
In certain embodiments, by multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding combine before, also on first pad 211 on described the first chip 210 surfaces or on second pad 221 on described the second chip 220 surfaces, formed the 3rd metal coupling (not shown), described the 3rd metal coupling can be tin ball, copper post or principal column.Multiple second pads 221 on described the second chip 220 surfaces are comprised with the technique of multiple first pad 211 corresponding combinations on described the first chip 210 surfaces: the relative laminating in surface that first described the second chip 220 is there is to the surface of the second pad 221 and described the first chip 210 and have the first pad 211, because described multiple the second pads 221 are corresponding with the position of described multiple the first pads 211, can make described multiple the second pad 221 fit between two with described multiple the first pads 211; Then carry out high temperature melting step, make the metal coupling fusing on described the first pad 211 or described the second pad 221, cover the surface of described the first pad 211 and described the second pad 221, both are combined closely and electricity connection.
In certain embodiments, can also be by form anisotropy conductiving glue layer on the surface of described the second chip 220 or the first chip 210, for by multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding combines.Described anisotropy conductiving glue layer comprises conducting particles and insulating material, and conducting particles is dispersed in insulating material.Particularly, anisotropy conductiving glue laminating can be attached to the surface of described the second chip 220, after exactitude position, by the surperficial pressing of the surface of the second chip 220 and the first chip 210, after heating and pressurization, anisotropy conductiving glue layer be solidified.Described anisotropy conductiving glue layer can conduct electricity in the direction perpendicular to described the first chip 210 surfaces or described the second chip 220 surfaces, and it is non-conductive in the direction that is parallel to described the first chip 210 surfaces or described the second chip 220 surfaces, thereby electricity between described the first pad 211 and described the second pad 221 is connected, and can not make short circuit between different the first pads 211 or different the second pad 221.
Above-mentioned technique can be without adopting metal lead wire technique, pad between described the first chip 210 and described the second chip 220 is directly welded to electrical combination, thereby chip system grade package dimension is dwindled greatly, can enhance productivity, simplification of flowsheet.
Step S103 with reference to figure 5, fills insulation glue-line 230 between described the first chip 210 surfaces and described the second chip 220 surfaces.
In the present embodiment, described the first pad 211 protrudes from the surface of described the first chip 210, described the second pad 221 protrudes from the surface of described the second chip 220, and be formed with the 3rd metal coupling on described the first pad 211 or described the second pad 221, by multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding combine after, between described the first chip 210 surfaces and described the second chip 220 surfaces, there is space.Therefore, further, need between described the first chip 210 surfaces and described the second chip 220 surfaces, fill insulation glue-line 230.The material of described insulation glue-line 230 can be Silicon-On-Insulator glue, polyimides or BCB resin etc.Particularly, adopt gluing process, use point gum machine by a side or a few side of insulating cement material point void area between described the first chip 210 surfaces and described the second chip 220 surfaces, insulating cement material can lean on self mobility to flow to opposite side, and in flow process, fill up gradually space, form insulation glue-line 230.Described insulation glue-line 230, for bonding described the first chip 210 and the relative surf zone of described the second chip 220, strengthens adhesion between the two.
It should be noted that, when with anisotropy conductiving glue layer by multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding while combining, because described anisotropy conductiving glue layer has been filled between described the first chip 210 surfaces and described the second chip 220 surfaces, can not need to form again insulation glue-line bonding.
Step S104, with reference to figure 6, forms the first insulating barrier 240, coated described the second chip 220 of described the first insulating barrier 240 and with described the first chip 210 combinations, and the first insulating barrier 240 covers described multiple the 3rd pad 212.
In the present embodiment, described the first insulating barrier 240 is dry film.Described dry film is macromolecular compound, such as polyimides, epoxy resin, silica gel or benzocyclobutene etc., after ultraviolet irradiation, can produce polymerization reaction form stable material be attached on the first chip 210 and the second chip 220.In the present embodiment, adopt vacuum film applicator coating to form described dry film, comprising: the packaging body of dry film and the first chip 210 and the second chip 220 is placed in vacuum chamber; Described dry film is covered on described the second chip 220, described the second chip 220 is coated, and be bonded on described the first chip 210 surfaces.Vacuum chamber can guarantee between dry film and the first chip 210 and the second chip 220 without bubble, and laminating closely.In the present embodiment, described dry film covers described the 3rd pad 212.
In some implementations, described the first insulating barrier 240 can be also capsulation material, passes through Shooting Technique, in corresponding mould, fill capsulation material, be coated described the second chip 220, and be bonded to the surface of described the first chip 210, after solidifying through heating up, form described the first insulating barrier 240.
In other embodiments, described the first insulating barrier 240 can be also other insulating material.
In the present embodiment, the thickness that described dry film exceeds the part of described the second chip 220 is 5～20 μ m.In other embodiments, in the time that described the first insulating barrier 240 adopts other materials, the thickness of described the first insulating barrier 240 is determined according to its insulating capacity, and its thickness should guarantee can not cause electric leakage.
Forming after the first insulating barrier 240, described the first insulating barrier 240 is coated described the second chip 220 and covers the region outside the projection of described the second chip 220 on described the first chip 210, and described the second chip 220 is bonded to described the first chip 210.
Compared with prior art, with reference to figure 1, pass through insulating cement 130 combinations in prior art between the first chip 110 and the second chip 120, the area of insulating cement 130 is only suitable with the area of the second chip 120, causes its binding ability poor.And in the present embodiment, with reference to figure 6, between the first chip 210 and the second chip 220, not only pass through 230 combinations of insulation glue-line, in addition, because described the first insulating barrier 240 is coated described the second chip 220 and is bonded to described the first chip 210, strengthen the structural strength of combination between the first chip 210 and the second chip 220, made the second chip 220 be not easy to come off from the first chip 210, strengthened reliability of structure after whole encapsulation.
Step S105, with reference to figure 7, the first insulating barrier 240 described in etching, forms the first opening 250 that exposes described the 3rd pad 212.
In the present embodiment, described the first insulating barrier 240 is dry film, can adopt photoetching process to form described the first opening 250.Specifically comprise: first use the region outside dry film the first opening 250 regions to be formed described in UV-irradiation, make it produce polymerization reaction and form stable material, to stop follow-up etching; Then adopt photoetching process to remove not by the dry film region of UV-irradiation, form the first opening 250, described the first opening 250 exposes the 3rd pad 212 on described the first chip 210.
In certain embodiments, described the first insulating barrier 240 is capsulation material, can adopt laser beam drilling technique to form the first opening 250.Specifically comprise: the opening area for the treatment of using laser as thermal source to capsulation material heats, make to treat that opening area is rapidly heated, the capsulation material generating gasification in Ear Mucosa Treated by He Ne Laser Irradiation region, forms the first corresponding opening 250.In one embodiment, the pulse duration of described laser is 1ns～200ns, and pulse frequency is 80～200KHz, and laser is greater than 1E18W/cm at the energy of focal spot
2.Adopt laser beam drilling technique just can optionally remove capsulation material without forming mask, the heat producing when laser beam drilling is only concentrated in specific region, and laser degumming process is noncontact etching, and byproduct of reaction is gaseous state, pollutes little.
Step S106, with reference to figure 8, at described the first opening 250(with reference to figure 7) in form the first connector 260.
In the present embodiment, the material of described the first connector 260 is tin, adopts vacuum to print process of tin and forms.Under vacuum environment, tin cream is filled in the first opening 250 by mode of printing, can make tin cream fully fill up described the first opening 250 and not leave gap.Described the first insulating barrier 240 exposes the top surface of described the first connector 260, and because described the first opening 250 exposes the 3rd pad 212 on described the first chip 210, therefore forming after described the first connector 260, described the first connector 260 is connected with described the 3rd pad 212 electricity.
In other embodiments, the material of described the first connector 260 can also be copper or other metal materials.
Step S107 with reference to figure 9, forms the first metal coupling 270 being connected with its electricity on described the first connector 260.
In the present embodiment, described the first metal coupling 270 is tin ball.First print solder paste on described the first connector 260, then carry out high temperature reflux, under surface tension effects, form tin ball; Also first print fluxing and tin ball particle on described the first connector 260, then high temperature reflux forms soldered ball; Can also be on described the first connector 260 electrotinning post, then high temperature reflux forms soldered ball.
In other embodiments, the combination that described the first metal coupling 270 can also be copper post, principal column or copper post and tin ball etc.
In the present embodiment, because the top surface of described the first insulating barrier 240 is higher than described the second chip 220, forming after described the first metal coupling 270, described the first metal coupling 270 is also higher than described the second chip 220.
Compared with prior art, please continue to refer to Fig. 1, in the encapsulating structure of the prior art shown in Fig. 1, because the diameter of soldered ball 140 is less than the thickness of described the second chip 120 conventionally, therefore soldered ball 140 is lower than described the second chip 120, therefore, in the time this encapsulating structure being connected to pcb board by soldered ball 140, conventionally need on pcb board, need to form the extra perforate corresponding with the second chip 120, to hold described the second chip 120, soldered ball 140 be contacted with pcb board.And in the present embodiment, with reference to figure 9, by forming the first insulating barrier 240 and the first connector 260, the first metal coupling 270 is transferred on the first insulating barrier 240, make the first metal coupling 270 higher than described the second chip 220, without considering that the height because of the first metal coupling 270 is less than the thickness of the second chip 220 and forms extra perforate on pcb board, and can directly by the first metal coupling 270, the encapsulating structure of the first chip 210 and the second chip 220 be bonded to pcb board, simplify technique.
Continue with reference to figure 9, corresponding to the formation method 100 of above-mentioned chip-packaging structure, described chip-packaging structure comprises:
The first chip 210, the surface of described the first chip 210 has multiple the first pads 211;
The second chip 220, the area of described the second chip 220 is less than the area of described the first chip 210, the surface of described the second chip 220 has multiple the second pads 221, described multiple the second pad 221 is corresponding with the position of described multiple the first pads 211, and multiple second pads 221 on described the second chip 220 surfaces and described the first chip 210 surfaces multiple first pad 211 is corresponding combines;
The first insulating barrier 240, described the first insulating barrier 240 by coated described the second chip 220 and with described the first chip 210 combinations.
In the present embodiment, described chip-packaging structure also comprises:
The 3rd pad 212, is positioned at described the first chip 210 surfaces, and is positioned at described the second chip 220 outside described the first chip 210 surface projection regions, and described the 3rd pad 212 is covered by described the first insulating barrier 240;
The 3rd metal coupling (not shown), between described the first pad 211 and described the second pad 221, for described the second pad 221 is combined with described the first pad 211;
Insulation glue-line 230, between described the first chip 210 surfaces and described the second chip 220 surfaces, the area of described the first insulating barrier 240 and described insulation glue-line 230 and described the first chip 210 faying faces is greater than the area of described the second chip 220;
The first connector 260, runs through described the first insulating barrier 240, and is connected with described the 3rd pad 212 electricity; And
The first metal coupling 270, is positioned on described the first connector 260.
The utility model also provides another embodiment, please refer to Figure 10, and Figure 10 is the schematic flow sheet of the formation method 200 of another embodiment chips encapsulating structure of the utility model.The step of the formation method 200 below in conjunction with accompanying drawing to chip-packaging structure of the present utility model describes.For the purpose of simple and clear, in the present embodiment with a upper embodiment in same or analogous part no longer describe in detail, can be with reference to a upper embodiment.
Step S201, with reference to Figure 11, provides the first chip 310, and the surface of described the first chip 310 has multiple the first pads 311 and multiple the 3rd pad 312; The second chip 320 is provided, and the surface of described the second chip 320 has multiple the second pads 321, and described multiple the second pads 321 are corresponding with the position of described multiple the first pads 311, and the area of described the second chip 320 is less than the area of the first chip 310.
Step S202, with reference to Figure 12, forms and covers multiple first pads 311 on described the first chip 310 surfaces and the second insulating barrier 330 of multiple the 3rd pads 312.
In the present embodiment, described the second insulating barrier 330 is dry film or photoresist layer.Form after dry film or photoresist layer on described the first chip 310 surfaces, described dry film or photoresist layer cover described the first chip 310 surfaces, described the first pad 311 and the 3rd pad 312.The thickness of described dry film or photoresist layer is greater than the thickness of described the second chip 320, makes follow-up formation in described dry film or photoresist layer after the second opening, and the degree of depth of described the second opening is greater than the thickness of described the second chip 320.
In other embodiments, the material of described the second insulating barrier 330 can also be insulating polymer, or inorganic insulating material etc.
Step S203, with reference to Figure 13, the second insulating barrier 330 described in etching, formation exposes second opening 340 on described the first pad 311 and described the first chip 310 surfaces of part, formation exposes the 3rd opening 350 of described the 3rd pad 312, and described the second opening 340 can hold described the second chip 320.
In the present embodiment, described the second insulating barrier 330 is dry film or photoresist layer, adopts photoetching process to form described the second opening 340 and the 3rd opening 350.The area of described the second opening 340 is greater than the area of described the second chip 320, and the degree of depth of described the second opening 340 is greater than the thickness of described the second chip 320, follow-up described the second chip 320 can be placed in described the second opening 340, make the second pad 321 and the first chip 310 surfaces first pad 311 is corresponding combines.
In other embodiments, described the second insulating barrier 330 is other insulating polymers, or when inorganic insulating material, can first on described the second insulating barrier 330, form patterned photoresist layer, described patterned photoresist layer has the second opening to be formed and opening corresponding to the 3rd opening to be formed, along the opening of described patterned photoresist layer, the second insulating barrier 330 described in etching, to form the second opening 340 and the 3rd opening 350.
It should be noted that, the technique that forms described the second opening 340 and the 3rd opening 350 can form in same processing step, also can in different process step, form.For example, first form the second opening 340, described the second chip 320 is placed in described the second opening 340, make the second pad 321 and the first chip 310 surfaces first pad 311 is corresponding combines, and form after the first insulating barrier of coated described the second chip 320, then form the 3rd opening 350.
Step S204, with reference to Figure 14, by multiple second pads 321 on described the second chip 320 surfaces and described the first chip 310 surfaces multiple first pad 311 is corresponding combines, described the second chip 320 is positioned at described the second opening 340.
Described that multiple second pads 321 on the second chip 320 surfaces are corresponding to comprising with multiple first pads 311 on described the first chip 310 surfaces: described the second chip 320 is inserted in described the second opening 340, and multiple second pads 321 on described the second chip 320 surfaces are corresponding with multiple first pad 311 positions on described the first chip 310 surfaces; Second pad 321 on described the second chip 320 surfaces and first pad 311 on described the first chip 310 surfaces are passed through to the 3rd metal coupling (not shown) combination.Described integrating step can be identical with preceding method, do not repeat them here.
Step S205, with reference to Figure 15, forms the first insulating barrier 360, coated described the second chip 320 of described the first insulating barrier 360 and with described the first chip 310 combinations, and described the first insulating barrier 360 is filled described the second opening 340(with reference to Figure 14).
In the present embodiment, described the first insulating barrier 360 is insulating cement, as insulation silica gel, polyimides or BCB resin etc.Adopt gluing process, use point gum machine that insulating cement material is filled in described the second opening 340, insulating cement material is coated described the second chip 320, and insulating cement material can lean on self mobility to fill the void area between the first chip 310 surfaces and described the second chip 320 surfaces, until fill full described the second opening 340.And use gluing process, can accurately locate the position that forms insulating cement, insulating cement material is only formed in the second opening 340, and can be formed in the 3rd opening 350.
In the present embodiment, described the second opening 340 exposes described the first pad 311 and described the first chip 310 surfaces of part, after interior formation the first insulating barrier 360 of described the second opening 340, coated described the second chip 320 of described the first insulating barrier 360 is also bonded to described the first chip 310, strengthen the structural strength of combination between the first chip 310 and the second chip 320, make the second chip 320 be not easy to come off from described the first chip 310, strengthened the reliability of whole encapsulating structure.
Step S206, with reference to Figure 16, at interior formation the second connector 370 of described the 3rd opening 350.
Step S207 with reference to Figure 17, forms the second metal coupling 380 that electricity connects with it on described the second connector 370.
In the present embodiment, by forming the second insulating barrier 330 and the second connector 370, the 3rd pad 312 is caused on the second insulating barrier 330, the second metal coupling 380 is higher than described the second chip 320, without considering that the height because of the second metal coupling 380 is less than the thickness of the second chip 320 and needs additionally to form perforate on pcb board, and can directly by the second metal coupling 380, the encapsulating structure of the first chip 310 and the second chip 320 be bonded to PCB, simplify technique.
Continue with reference to Figure 17, corresponding to the formation method 200 of above-mentioned chip-packaging structure, described chip-packaging structure comprises:
The first chip 310, the surface of described the first chip 310 has multiple the first pads 311;
The second chip 320, the area of described the second chip 320 is less than the area of described the first chip 310, the surface of described the second chip 320 has multiple the second pads 321, described multiple the second pad 321 is corresponding with the position of described multiple the first pads 311, and multiple second pads 321 on described the second chip 320 surfaces and described the first chip 310 surfaces multiple first pad 311 is corresponding combines;
The first insulating barrier 360, described the first insulating barrier 360 by coated described the second chip 320 and with described the first chip 310 combinations.
In the present embodiment, described chip-packaging structure also comprises:
The 3rd pad 312, is positioned at described the first chip 310 surfaces, and is positioned at described the second chip 320 outside described the first chip 310 surface projection regions;
The second insulating barrier 330, covers the region outside described the first chip 310 surfaces that described the first insulating barrier 360 covers, and covers described the 3rd pad 312;
The 3rd metal coupling (not shown), between described the first pad 311 and described the second pad 321, for described the second pad 321 is combined with described the first pad 311;
The second connector 370, runs through described the second insulating barrier 330, and is connected with described the 3rd pad 312 electricity;
The second metal coupling 380, is positioned on described the second connector 370.
Although the utility model discloses as above, the utility model is not defined in this.Any those skilled in the art, not departing from spirit and scope of the present utility model, all can make various changes or modifications, and therefore protection range of the present utility model should be as the criterion with claim limited range.
Claims (10)
1. a chip-packaging structure, is characterized in that, comprising:
The first chip, the surface of described the first chip has multiple the first pads;
The second chip, the area of described the second chip is less than the area of described the first chip, the surface of described the second chip has multiple the second pads, described multiple the second pad is corresponding with the position of described multiple the first pads, and corresponding the combining of multiple the first pads of multiple second pads of described the second chip surface and described the first chip surface;
The first insulating barrier, described the first insulating barrier by described the second chip coated and with described the first chips incorporate.
2. chip-packaging structure as claimed in claim 1, is characterized in that, also comprises: insulation glue-line, and between described the first chip surface and described the second chip surface.
3. chip-packaging structure as claimed in claim 2, is characterized in that, the area of described the first insulating barrier and described insulation glue-line and described the first chips incorporate face is greater than the area of described the second chip.
4. chip-packaging structure as claimed in claim 1, is characterized in that, also comprises: be positioned at multiple the 3rd pads of described the first chip surface, described multiple the 3rd pads are positioned at the part of described the second chip outside the view field of described the first chip surface.
5. chip-packaging structure as claimed in claim 4, is characterized in that, also comprises:
Multiple the first connectors, run through respectively described the first insulating barrier, and connect with the corresponding electricity of described multiple the 3rd pad;
Multiple the first metal couplings, are positioned on described the first insulating barrier and with the corresponding electricity of described multiple the first connector and connect.
6. chip-packaging structure as claimed in claim 5, is characterized in that, described multiple the first metal coupling height are not less than the first insulating barrier top of coated described the second chip.
7. chip-packaging structure as claimed in claim 4, it is characterized in that, described the 3rd pad is positioned at the region outside described the first chip surface being covered by described the first insulating barrier, and described the first insulating barrier is filled in the region between described the first chip and the second chip surface.
8. chip-packaging structure as claimed in claim 7, is characterized in that, also comprises:
The second insulating barrier, cover described first insulating barrier cover described the first chip surface outside region;
Multiple the second connectors, run through respectively described the second insulating barrier, and connect with the corresponding electricity of described multiple the 3rd pad respectively;
Multiple the second metal couplings, be positioned on described the second insulating barrier and with the corresponding electrical connection of described multiple the second connector.
9. chip-packaging structure as claimed in claim 8, is characterized in that, described multiple the second metal coupling height are not less than the first insulating barrier top of coated described the second chip.
10. chip-packaging structure as claimed in claim 1, is characterized in that, also comprises: multiple the 3rd metal couplings, lay respectively between described multiple the first pad and described multiple the second pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420027332.4U CN203746826U (en) | 2014-01-16 | 2014-01-16 | Chip packaging structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201420027332.4U CN203746826U (en) | 2014-01-16 | 2014-01-16 | Chip packaging structure |
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| CN203746826U true CN203746826U (en) | 2014-07-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762187A (en) * | 2014-01-16 | 2014-04-30 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and structure |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103762187A (en) * | 2014-01-16 | 2014-04-30 | 苏州晶方半导体科技股份有限公司 | Chip packaging method and structure |
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