CN203746307U - Circuit for displaying digital logic states - Google Patents
Circuit for displaying digital logic states Download PDFInfo
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- CN203746307U CN203746307U CN201320801128.9U CN201320801128U CN203746307U CN 203746307 U CN203746307 U CN 203746307U CN 201320801128 U CN201320801128 U CN 201320801128U CN 203746307 U CN203746307 U CN 203746307U
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- operational amplifier
- resistor
- resistance
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- power supply
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- 239000003086 colorant Substances 0.000 abstract 1
- 238000000034 method Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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Abstract
The utility model relates to a circuit for displaying digital logic states, and belongs to the technical field of digital electronics. A logic level input terminal is connected with one end of a resistor R1, one end of a resistor R2 and an inverting input terminal of an operational amplifier U, the other end of the resistor R1 is grounded, the other end of the resistor R2 is connected with the output terminal of the operational amplifier U and one end of a dichromatic light emitting diode D1, the other end of the dichromatic light emitting diode D1 is connected with one end of a resistor R5, the other end of the resistor R5 is connected with a +5V power supply, one end of a resistor R4 is connected with a non inverting input terminal of the operational amplifier U and one end of a resistor R3, the other end of the resistor R3 is grounded, the other end of the R4 is connected with the +5V power supply, a positive power supply terminal of the operational amplifier U is connected with a +12V power supply, and a negative power supply terminal of the operational amplifier U is grounded. In the practical application of digital circuit technology experiments, the circuit for displaying the digital logic states is simple and can display two colors, and can display the logical states visually and observably, students can read the logical states rapidly and accurately, and the circuit for displaying the digital logic states is welcomed by the students.
Description
Technical field
The utility model relates to a kind of display circuit of digital logic states, belongs to Digital Electronic Technique field.
Background technology
Digital logic states display circuit is that DLC (digital logic circuit) logic state is detected, and shows 0 logic state or 1 logic state with the color of light emitting diode.In current digital circuit experiment equipment, digital logic states is mainly shown as master with monochrome, bright or its state of demonstration that goes out of red diode, 1 logic state is with the bright demonstration of red light emitting diodes, and 0 logic state is with the red light emitting diodes demonstration of going out, and this circuit structure is simple, but color is single, show not eye-catchingly, 1 logic state display brightness is not high, highlighted demonstration power consumption to increase; Reliability is not high; 0 logic state red light emitting diodes does not show; when fault electric current is zero no-output logic, red light emitting diodes also do not show, the state showing when student often can be fault while experiment is pronounced 0 logic state; think that circuit normally works by mistake; also having is 0 logic state with regard to circuit logic, and voltage is normal 0 logic state voltage, as 0.8V-2.4V; red light emitting diodes also can show, students' union thinks it is 1 logic state by mistake.
Summary of the invention
The technical problems to be solved in the utility model is: a kind of display circuit of digital logic states is provided, has designed simpler, the double-colored demonstration of a kind of structure, digital logic states display circuit that reliability is high.
Technical solutions of the utility model are: a kind of display circuit of digital logic states, comprises resistance R 1, R2, R3, R4, R5, dichromatic LED D1 and operational amplifier U, described logic level input end connecting resistance R1, one end of R2, the inverting input of operational amplifier U, the other end ground connection of resistance R 1, the output terminal of another termination operational amplifier U of resistance R 2 and one end of dichromatic LED D1, one end of the other end connecting resistance R5 of dichromatic LED D1, another termination+5V power supply of resistance R 5, resistance R 4 one in-phase input ends of termination operational amplifier U and one end of resistance R 3, resistance R 3 other end ground connection, resistance R 4 another termination+5V power supplys, positive supply termination+12V power supply of operational amplifier U, its negative power end ground connection.
Circuit is amplification principle relatively: as shown in Figure 1, when logic level input end is less than or equal to 2.4V, operational amplifier U exports 10.28V, dichromatic LED green light; When logic level input end is more than or equal to 2.6V, operational amplifier U exports 0.9V, dichromatic LED when red; When logic level input end equals 2.5V, operational amplifier U output 5V dichromatic LED does not work.
Dichromatic LED principle of work: dichromatic LED shows ruddiness and green glow as mentioned above, dichromatic LED in fact inside is to be made up of red light emitting diodes and green LED, as shown in frame as empty in Fig. 1 dichromatic LED D1, draw three pins, 1 logic state is with the bright demonstration of red light emitting diodes, and 0 logic state is with the bright demonstration of green LED; Output logic level is during lower than 2.5V, and as 0.8V-2.4V, circuit can, with the bright demonstration of green LED, be judged as 0 logic state.
The beneficial effects of the utility model are: this display circuit is in the practical application of digital circuit technique experiment, circuit is simple, double-colored demonstration, logic state intuitive display is eye-catching, student reads logic state quick and precisely, can be widely used in the detection of DLC (digital logic circuit) logic state, welcome by student.
Brief description of the drawings
Fig. 1 is the utility model circuit theory diagrams.
Embodiment
Below in conjunction with the drawings and specific embodiments, the utility model is described in further detail.
Embodiment 1: as shown in Figure 1, a kind of display circuit of digital logic states, comprises resistance R 1, R2, R3, R4, R5, dichromatic LED D1 and operational amplifier U, described logic level input end connecting resistance R1, one end of R2, the inverting input of operational amplifier U, the other end ground connection of resistance R 1, the output terminal of another termination operational amplifier U of resistance R 2 and one end of dichromatic LED D1, one end of the other end connecting resistance R5 of dichromatic LED D1, another termination+5V power supply of resistance R 5, resistance R 4 one in-phase input ends of termination operational amplifier U and one end of resistance R 3, resistance R 3 other end ground connection, resistance R 4 another termination+5V power supplys, positive supply termination+12V power supply of operational amplifier U, its negative power end ground connection.
By reference to the accompanying drawings specific embodiment of the utility model is explained in detail above, but the utility model is not limited to above-described embodiment, in the ken possessing those of ordinary skill in the art, can also under the prerequisite that does not depart from the utility model aim, make various variations.
Claims (1)
1. a display circuit for digital logic states, is characterized in that: comprise resistance (R1, R2, R3, R4, R5), dichromatic LED (D1) and operational amplifier (U), logic level input end connecting resistance (R1, R2) one end, the inverting input of operational amplifier (U), the other end ground connection of resistance (R1), the output terminal of another termination operational amplifier (U) of resistance (R2) and one end of dichromatic LED (D1), one end of the other end connecting resistance (R5) of dichromatic LED (D1), another termination+5V power supply of resistance (R5), the in-phase input end of resistance (R4) termination operational amplifier (U) and one end of resistance (R3), resistance (R3) other end ground connection, another termination+5V power supply of resistance (R4), positive supply termination+12V power supply of operational amplifier (U), its negative power end ground connection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320801128.9U CN203746307U (en) | 2013-12-09 | 2013-12-09 | Circuit for displaying digital logic states |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320801128.9U CN203746307U (en) | 2013-12-09 | 2013-12-09 | Circuit for displaying digital logic states |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203746307U true CN203746307U (en) | 2014-07-30 |
Family
ID=51346080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320801128.9U Expired - Fee Related CN203746307U (en) | 2013-12-09 | 2013-12-09 | Circuit for displaying digital logic states |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203746307U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346167A (en) * | 2018-08-03 | 2019-02-15 | 昆明理工大学 | A kind of diagnosis aid system based on artificial intelligence |
-
2013
- 2013-12-09 CN CN201320801128.9U patent/CN203746307U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109346167A (en) * | 2018-08-03 | 2019-02-15 | 昆明理工大学 | A kind of diagnosis aid system based on artificial intelligence |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140730 Termination date: 20141209 |
|
| EXPY | Termination of patent right or utility model |