CN203659880U - Semiconductor device - Google Patents
Semiconductor device Download PDFInfo
- Publication number
- CN203659880U CN203659880U CN201320877434.0U CN201320877434U CN203659880U CN 203659880 U CN203659880 U CN 203659880U CN 201320877434 U CN201320877434 U CN 201320877434U CN 203659880 U CN203659880 U CN 203659880U
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- Prior art keywords
- semiconductor device
- pole plate
- active area
- pin
- metal
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 91
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims description 20
- 239000013078 crystal Substances 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 11
- 238000000034 method Methods 0.000 claims description 9
- 230000000717 retained effect Effects 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 abstract description 4
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 239000011810 insulating material Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- Semiconductor Integrated Circuits (AREA)
Abstract
The utility model discloses a semiconductor device. The semiconductor device comprises a substrate, an insulating layer formed on the the upper surface of the substrate and at least one metal interconnecting layer formed on the insulating layer. The semiconductor device further comprises at least one metal layer formed on the lower surface of the substrate. According to the semiconductor device of the utility model, the at least one metal layer is formed on the lower surface of the substrate, and the at least one metal layer and the at least one metal interconnecting layer formed on the upper surface of the substrate can form a plate capacitor, and the plate capacitor can be connected to the input end or output end of the semiconductor device, and therefore, the matching of the input or output impedance to the target impedance of the semiconductor device can be realized.
Description
Technical field
The utility model relates to semiconductor applications, particularly a kind of semiconductor device.
Background technology
In the time that semiconductor device is used for rf power amplifier circuit or some other particular electrical circuit, need it to there is higher input and output impedance.But the input and output impedance of a lot of semiconductor device of manufacturing is at present very low, therefore need these semiconductor device to carry out impedance matching, such as, use a large amount of discrete components at peripheral circuit, or adopt bonding line the semiconductor device on same packaging frame is connected with electric capacity and is packaged together.But these methods can increase the design difficulty of circuit, reduce the reliability of circuit working.Meanwhile, owing to having introduced the equivalent inductance of bonding line, the fluctuation of its technique all can have a huge impact the Stability and dependability of performance of semiconductor device.
Utility model content
The device stability problem that while semiconductor device being carried out to input and output impedance matching in order to solve in prior art, circuit design difficulty is large and technological fluctuation causes, the utility model provides a kind of semiconductor device, comprise substrate, be formed at described substrate top surface insulating barrier, be formed at least one metal interconnecting layer on described insulating barrier, described semiconductor device also comprises at least one metal level that is formed at described substrate lower surface.
Further, described semiconductor device possesses He Fei active area, active area, in described non-active area, is formed with at least one capacity plate antenna.
Further, described capacity plate antenna comprises the first pole plate and the second pole plate that are oppositely arranged, described the first pole plate is to be retained in a part of metal in described non-active area by adjusting etching domain in the etching procedure that forms described metal interconnecting layer, and described the second pole plate is to be retained in a part of metal in described non-active area by adjusting etching domain in the etching procedure of metal level that forms described substrate lower surface.
Preferably, the pin that inputs or outputs in the packaging pin of described the first pole plate and described semiconductor device is connected, and the crystal cup that is connected to earth terminal in the packaging frame of described the second pole plate and described semiconductor device joins.
Preferably, the grounding pin in the packaging pin of described the first pole plate and described semiconductor device is connected, and the crystal cup that being connected in the packaging frame of described the second pole plate and described semiconductor device inputs or outputs end joins.
Compared with prior art, the semiconductor device that the utility model provides, its beneficial effect is:
1) inside of semiconductor device will be integrated in as the element of impedance matching, the problem that thereby while having avoided using discrete component to carry out impedance matching, circuit design difficulty is large, functional reliability is low, stability on performance of semiconductor device when also having avoided using bonding line mode to connect electric capacity simultaneously and carrying out impedance matching and the impact of reliability, reduced semiconductor device complexity in use and the failure rate that may bring;
2) what be integrated in semiconductor device inside adopts capacity plate antenna as the element of impedance matching, can adopt easily the metal interconnecting layer of semiconductor device itself and the metal level of device lower surface to realize, do not need extra capacitor to save cost on the one hand, make on the other hand integrated difficulty greatly reduce yet;
3) manufacture of this semiconductor device is easy, can be in the process for making of semiconductor device, adjust the size of electric capacity by adjusting the etching domain of metal level of metal interconnecting layer and device lower surface, and by adjusting the connected mode of capacitor pin, carry out the impedance matching that inputs or outputs end of semiconductor device.
Accompanying drawing explanation
Fig. 1 is the schematic sectional view of the subregion of semiconductor device of the present utility model;
Fig. 2 is the schematic sectional view of the first example of the connection pin of the capacity plate antenna of semiconductor device of the present utility model;
Fig. 3 is the schematic sectional view of the second example of the connection pin of the capacity plate antenna of semiconductor device of the present utility model;
Fig. 4 is the schematic sectional view of the subregion of the first execution mode of semiconductor device of the present utility model;
Fig. 5 is the schematic circuit of the impedance matching mode of Fig. 4;
Fig. 6 is the schematic sectional view of the subregion of the second execution mode of semiconductor device of the present utility model;
Fig. 7 is the schematic circuit of the impedance matching mode of Fig. 6;
Fig. 8 is the schematic sectional view of the subregion of the 3rd execution mode of semiconductor device of the present utility model;
Fig. 9 is the schematic circuit of the impedance matching mode of Fig. 8;
Figure 10 is the schematic sectional view of the subregion of the 4th execution mode of semiconductor device of the present utility model;
Figure 11 is the schematic circuit of the impedance matching mode of Figure 10;
Figure 12 is the schematic sectional view of the subregion of the 5th execution mode of semiconductor device of the present invention;
Figure 13 is the schematic circuit of the impedance matching mode of Figure 12.
Main description of reference numerals
1: Semiconductor substrate 2: insulating barrier
3: metal interconnecting layer 4: metal level
5: crystal cup 101: draw pin
20: the second pole plates of 10: the first pole plates
Embodiment
Below in conjunction with the drawings and specific embodiments, semiconductor device of the present utility model is described in further detail, but not as to restriction of the present utility model.
It should be noted that, schematic sectional view only shows the subregion of semiconductor device, therefore, the border in accompanying drawing can not be thought to the actual boundary of semiconductor device.
With reference to Fig. 1, it is the schematic sectional view of the subregion of semiconductor device of the present utility model.The semiconductor device that the utility model provides, comprises substrate 1, the insulating barrier 2 that is formed at successively substrate 1 upper surface and at least one metal interconnecting layer 3, also comprises at least one metal level 4 that is formed at substrate 1 lower surface.Semiconductor device possesses He Fei active area, active area, is formed with at least one capacity plate antenna in non-active area.Capacity plate antenna comprises the first pole plate 10 and the second pole plate 20 that are oppositely arranged, the first pole plate 10 is for be retained in a part of metal in non-active area by adjusting etching domain in the etching procedure that forms metal interconnecting layer 3, and the second pole plate 20 for being retained in a part of metal in non-active area by adjusting etching domain in the etching procedure of metal level 4 that forms substrate 1 lower surface.By this capacity plate antenna being connected to the end that inputs or outputs of semiconductor device, can realize that semiconductor device inputed or outputed to impedance to the coupling of target impedance.
The mode that the connection of the first pole plate 10 to capacity plate antenna can be drawn by routing realizes.As shown in Figure 2, the part that metal interconnecting layer is positioned at active area has the pin that routing is drawn conventionally, can utilize input/output terminal or the earth terminal etc. of this pin interface unit to realize being connected of packaging pin of the first pole plate 10 and device.Or as shown in Figure 3, can on the first pole plate 10 that is positioned at non-active area, directly carry out routing and draw, draw pin 101, so that the first pole plate 10 is connected with the packaging pin of device.
The connection of the second pole plate 20 to capacity plate antenna can be by adjusting the position of crystal cup 5 on the packaging frame of semiconductor device, crystal cup 5 and the second pole plate 20 are joined, and the second pole plate 20 is connected with input or output end, earth terminal or other predetermined end of device by crystal cup.
the first execution mode
Fig. 4 is the schematic sectional view of the subregion of the first execution mode of semiconductor device of the present utility model.This kind of implementation structure, is applicable to the input of former chip active area part or output and is positioned at the situation of chip upper surface.The first pole plate 10 is connected by the pin that inputs or outputs of drawing in the packaging pin of pin 101 and semiconductor device, and the crystal cup that is connected to earth terminal 5 in the packaging frame of the second pole plate 20 and semiconductor device joins.
The schematic equivalent circuit of this connected mode as shown in Figure 5, be equivalent to semiconductor device input or output an end electric capacity in parallel, thereby realize the coupling that inputs or outputs impedance and input or output to target impedance of the active area of semiconductor device.
the second execution mode
Fig. 6 is the schematic sectional view of the subregion of the second execution mode of semiconductor device of the present utility model.This kind of implementation structure, is applicable to the input of former chip active area part or output and is positioned at the situation of chip bottom.In this embodiment, the first pole plate 10 and metal interconnecting layer 3 are positioned at the part electrical isolation of active area, the first pole plate 10 is connected with the earth terminal of semiconductor device by drawing pin 101, and the crystal cup 5 that being connected in the packaging frame of the second pole plate 20 and semiconductor device inputs or outputs end joins.
The schematic equivalent circuit of this connected mode as shown in Figure 7, be equivalent to semiconductor device input or output an electric capacity of end series connection, thereby realize the coupling that inputs or outputs impedance and input or output to target impedance of the active area of semiconductor device.
the 3rd execution mode
Fig. 8 is the schematic sectional view of the subregion of the 3rd execution mode of semiconductor device of the present utility model.In this embodiment, semiconductor inputing or outputing in active area held the bottom that is positioned at chip, and the first pole plate 10 and metal interconnecting layer 3 are positioned at the part electrical isolation of active area, the first pole plate 10 is connected by the pin that inputs or outputs of drawing in the packaging pin of pin 101 and semiconductor device, and the floating empty crystal cup 5 of maintenance current potential in the packaging frame of the second pole plate 20 and semiconductor device joins.In this embodiment, crystal cup 5 also can be connected to predetermined end, such as being connected to direct current biasing end.
The schematic equivalent circuit of this connected mode as shown in Figure 9, be equivalent to semiconductor device input or output an electric capacity of end series connection, thereby realize the coupling that inputs or outputs impedance and input or output to target impedance of the active area of semiconductor device.
the 4th execution mode
Figure 10 is the schematic sectional view of the subregion of the 4th execution mode of semiconductor device of the present invention.The pin 101 of drawing on the first pole plate 10 keeps current potential floating empty, and the crystal cup 5 that being connected in the packaging frame of the second pole plate 20 and semiconductor device inputs or outputs end joins.In this embodiment, go out pin 101 and also can be connected with the predetermined pins in the packaging pin of semiconductor device, such as being connected with direct current biasing pin.
The schematic equivalent circuit of this connected mode as shown in figure 11, be equivalent to semiconductor device input or output an electric capacity of end series connection, thereby realize the coupling that inputs or outputs impedance and input or output to target impedance of the active area of semiconductor device.
the 5th execution mode
In above execution mode, semiconductor device all comprises a capacity plate antenna in non-active area.Be understandable that, semiconductor device of the present utility model can comprise one or more capacity plate antennas in non-active area, the all parallel connections of these capacity plate antennas, all series connection or part parallel connection and partly series connection combine to be connected to the end that inputs or outputs of semiconductor device, input or output the impedance matching of end.
In non-active area, comprise that two capacity plate antennas conduct further description as example below take semiconductor device.With reference to Figure 12, it is the schematic sectional view of the subregion of the 5th execution mode of semiconductor device of the present utility model.In this embodiment, two capacity plate antennas are formed in the non-active area of device, i.e. the first capacity plate antenna and the second capacity plate antenna.Wherein the first pole plate 10 of the first capacity plate antenna is by drawing pin 101 ground connection, and the first pole plate 10 of the second capacity plate antenna keeps current potential floating empty.The second pole plate of the first capacity plate antenna and the second capacity plate antenna all with the packaging frame of semiconductor device in the crystal cup 5 that inputs or outputs end that is connected to join.
The schematic equivalent circuit of this connected mode as shown in figure 13, be equivalent to semiconductor device input or output the end electric capacity electric capacity in parallel again of first connecting, thereby realize the coupling that inputs or outputs impedance and input or output to target impedance of the active area of semiconductor device.
Be understandable that, if need to, at the integrated multiple electric capacity of semiconductor device inside, can realize by forming multiple capacity plate antennas in the non-active area of device, the generation type of capacity plate antenna includes but not limited to above-mentioned implementation.
Said insulating barrier above, can be an insulating barrier, can be also the compound of multiple insulating barriers.Said megohmite insulant above, can be an insulating barrier, can be also the compound of multiple insulating barriers; Can be a kind of insulating material, can be also the compound of multiple insulating material.Insulating material can be the material of any obstruction flow of charge, such as dry air etc.; But be preferably the insulating material that dielectric constant is large, such as silicon dioxide etc.
Above embodiment is only illustrative embodiments of the present utility model, can not be used for limiting the utility model, and protection range of the present utility model is defined by the claims.Those skilled in the art can, in essence of the present utility model and protection range, make various modifications or be equal to replacement the utility model, these modifications or be equal to replacement and also should be considered as dropping in protection range of the present utility model.
Claims (5)
1. a semiconductor device, comprise substrate, be formed at described substrate top surface insulating barrier, be formed at least one metal interconnecting layer on described insulating barrier, it is characterized in that, described semiconductor device also comprises at least one metal level that is formed at described substrate lower surface.
2. semiconductor device according to claim 1, is characterized in that, described semiconductor device possesses He Fei active area, active area, in described non-active area, is formed with at least one capacity plate antenna.
3. semiconductor device according to claim 2, it is characterized in that, described capacity plate antenna comprises the first pole plate and the second pole plate that are oppositely arranged, described the first pole plate is to be retained in a part of metal in described non-active area by adjusting etching domain in the etching procedure that forms described metal interconnecting layer, and described the second pole plate is to be retained in a part of metal in described non-active area by adjusting etching domain in the etching procedure of metal level that forms described substrate lower surface.
4. semiconductor device according to claim 3, it is characterized in that, the pin that inputs or outputs in the packaging pin of described the first pole plate and described semiconductor device is connected, and the crystal cup that is connected to earth terminal or predetermined end in the packaging frame of described the second pole plate and described semiconductor device joins.
5. semiconductor device according to claim 3, it is characterized in that, grounding pin in the packaging pin of described the first pole plate and described semiconductor device is connected, and the crystal cup that being connected in the packaging frame of described the second pole plate and described semiconductor device inputs or outputs end joins.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320877434.0U CN203659880U (en) | 2013-12-27 | 2013-12-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320877434.0U CN203659880U (en) | 2013-12-27 | 2013-12-27 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203659880U true CN203659880U (en) | 2014-06-18 |
Family
ID=50926234
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320877434.0U Expired - Lifetime CN203659880U (en) | 2013-12-27 | 2013-12-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203659880U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681788A (en) * | 2013-12-27 | 2014-03-26 | 上海贝岭股份有限公司 | Semiconductor device and manufacturing method thereof |
-
2013
- 2013-12-27 CN CN201320877434.0U patent/CN203659880U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681788A (en) * | 2013-12-27 | 2014-03-26 | 上海贝岭股份有限公司 | Semiconductor device and manufacturing method thereof |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140618 |