CN203644823U - RRAM (resistive random access memory) memory cell structure capable of realizing multi-bit memory - Google Patents
RRAM (resistive random access memory) memory cell structure capable of realizing multi-bit memory Download PDFInfo
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- CN203644823U CN203644823U CN201320884857.5U CN201320884857U CN203644823U CN 203644823 U CN203644823 U CN 203644823U CN 201320884857 U CN201320884857 U CN 201320884857U CN 203644823 U CN203644823 U CN 203644823U
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- 239000000463 material Substances 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 230000008859 change Effects 0.000 claims description 33
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- YBMRDBCBODYGJE-UHFFFAOYSA-N germanium oxide Inorganic materials O=[Ge]=O YBMRDBCBODYGJE-UHFFFAOYSA-N 0.000 claims description 3
- PVADDRMAFCOOPC-UHFFFAOYSA-N oxogermanium Chemical compound [Ge]=O PVADDRMAFCOOPC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 229910000314 transition metal oxide Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 10
- 230000008569 process Effects 0.000 abstract description 7
- 238000005516 engineering process Methods 0.000 abstract description 5
- 238000002360 preparation method Methods 0.000 description 4
- 230000001413 cellular effect Effects 0.000 description 3
- 238000010276 construction Methods 0.000 description 3
- 238000007667 floating Methods 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000005684 electric field Effects 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
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Abstract
The utility model provides an RRAM (resistive random access memory) memory cell structure capable of realizing multi-bit memory, which comprises a substrate, a lower electrode located on the substrate, a resistance variable layer located on the lower electrode, and an upper electrode located on the resistance variable layer, wherein the resistance variable layer is provided with a plurality of gradient layers which are different in thickness, and the gradient layers are made of the same material. The RRAM memory cell structure provided by the utility model can realize multi-valued memory of a single memory unit, thereby improving the memory density of a memory, and reducing the cost. In addition, the RRAM memory cell structure is compatible with processing technologies of the traditional resistance variable memory because only improved on the thickness of the resistance variable layer is carried out with adopting new materials, and the process is simple.
Description
Technical field
The utility model belongs to non-volatile semiconductor memory field, specifically, relates to a kind of high density memory cells structure of multilevel storage.
Background technology
In the electronic information epoch, semiconductor memory is being brought into play vital effect aspect information storage.Non-volatility memorizer due to power down after data still can keep, therefore, have larger advantage at mobile storage intermediary parties mask.
The typical device structure of current non-volatility memorizer is floating gate type memory.But along with microelectric technique process node constantly advances, the Flash memory based on traditional floating gate structure is being faced with the severe challenge of data storing reliability.
The problem running in order to tackle traditional floating gate type structure, various novel non-volatility memorizers have obtained development rapidly in recent years, mainly comprise discrete charge storage device (as nanocrystalline and SONOS), ferroelectric memory (FRAM), phase transition storage (PRAM), magnetic memory (MRAM), micro electronmechanical memory and resistance-variable storing device (RRAM).Candidate as memory of future generation must have following characteristics: can contractility good, storage density is high, low in energy consumption, read or write speed fast, repeatable operation tolerance is strong, data hold time is long, with CMOS process compatible etc.
Resistive formula memory (Resistive Random Access Memory, be called for short RRAM) be under DC Electric Field, can between high-impedance state and low resistance state, realize a class perspective of future generation nonvolatile memory of reversible transformation as basis take the resistance of material, it has the potentiality at 32nm node and the existing main flow Flash memory of following replacement, becomes an important research direction of current novel memory.
Traditional RRAM device is typical MIM " sandwich " structure, is the change resistance layer material that electric resistance changing can occur between upper/lower electrode.Outside under biased effect, the storage of realization " 0 " and " 1 " thereby the resistance of device can change between high low resistance state.
Along with memory device is constantly to the future development of large capacity, high density storage, it is a highly effective solution that the RRAM of each cellular construction realizes multilevel storage.Multilevel storage means for RRAM that change resistance layer must have and is greater than state two, stable and that easily distinguish.Therefore RRAM cellular construction, how to prepare resistance state more than is an important topic.
Utility model content
The utility model proposes a kind of RRAM memory cell structure of realizing multidigit storage, can improve the storage density of memory device.
The RRAM memory cell structure of multidigit storage of the present utility model, comprises substrate, is positioned at the bottom electrode on described substrate, is positioned at the change resistance layer on described bottom electrode, and is positioned at the top electrode on described change resistance layer; Described change resistance layer has the gradient aspect of multiple different-thickness, and the material of described gradient aspect is identical.
Preferably, each gradient aspect area value of the upper surface of described gradient aspect is identical.
Preferably, described change resistance layer is silica, germanium oxide or transition metal oxide.
Preferably, the number of steps of described change resistance layer is three.
Preferably, described substrate is silicon or Germanium semiconductor material.
The change resistance layer of the resistance-variable storing device that the utility model provides comprises the gradient aspect with multiple different-thickness, for the resistive material of different-thickness, the required voltage difference of resistive occurs, and the also difference of resistance after resistive occurs; That is to say, for the utility model resistance-variable storing device, the actual resistance of a cellular construction, is to be determined by the parallel connection value of the change resistance layer resistance of different-thickness.Therefore,, by apply different voltage on upper/lower electrode, can make resistance-variable storing device present and exceed the resistance state of two.
Compared with traditional scheme, the resistance variation memory structure that the utility model provides can be realized the multilevel storage of single memory cell, thereby improves the storage density of memory, reduces costs.In addition, owing to being only that thickness to change resistance layer has been done improvement, make it have the gradient aspect of multiple different-thickness, do not adopt new material, can continue to adopt traditional resistance-variable storing device processing technology, there is the compatible strong and simple feature of technique.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of RRAM memory cell structure one preferred embodiment of the utility model multidigit storage, wherein, has the gradient aspect of two different-thickness in change resistance layer
Embodiment
The embodiment that embodies the utility model feature & benefits will describe in detail in the explanation of back segment.Be understood that the utility model can have various variations in different examples, it neither departs from scope of the present utility model, and explanation wherein and be shown in the use only explaining in essence, but not in order to limit the utility model.
It should be noted that, same as the prior art, the RRAM memory cell structure of multidigit storage of the present utility model, comprises substrate, is positioned at the bottom electrode on substrate, is positioned at the change resistance layer on bottom electrode, and is positioned at the top electrode on change resistance layer; Unlike the prior art, its change resistance layer has the gradient aspect of multiple different-thickness, and under normal circumstances, material and the processing step of making gradient aspect are all identical.
Refer to Fig. 1, Fig. 1 is the schematic diagram of RRAM memory cell structure one preferred embodiment of the utility model multidigit storage, in the present embodiment, has the gradient aspect of two different-thickness in change resistance layer.As shown in Figure 1, resistance-variable storing device of the present utility model comprises substrate 101, be arranged in bottom electrode 102 on substrate, be positioned at gradient aspect 103A and the 103B of two different-thickness of change resistance layer on bottom electrode 102, and is positioned at the top electrode 104 on change resistance layer.That is to say, two parts gradient aspect 103A and 103B that change resistance layer in the utility model is identical by material, thickness is different form, and the thickness h 1 of change resistance layer 103A is less than the thickness h 2 of change resistance layer 103B, has replaced the structure of only having the change resistance layer of single thickness in traditional resistance-variable storing device.
Although disclosed is in the present embodiment the resistance-variable storing device with two kinds of thickness change resistance layers, but those skilled in the art are not difficult to expect, by increasing again the change resistance layer of one or several thickness, can obtain resistance-variable storing device identical with the present embodiment principle, that storage density is higher.General, many one than the number of steps of gradient aspect of the store status number of RRAM memory cell.The number of steps of gradient aspect is more, and the storage bit number of RRAM memory cell can increase accordingly.Preferably, the number of steps of change resistance layer is three.
From each gradient aspect area value of the upper surface of gradient aspect, value difference as required, also value is identical as required.
Concrete, substrate 101 can be the semi-conducting material such as silicon, germanium, and change resistance layer 103A and 103B can be the materials that silica, germanium oxide, transition metal oxide or other have resistive characteristic, and electrode can be the metal materials such as nickel, platinum, tungsten.
For the process of resistance-variable storing device of preparing the present embodiment, in the time preparing the change resistance layer of different-thickness, need to increase several step process, and that other processing step only need keep is identical with the preparation technology of traditional resistance-variable storing device.We are the situation of silica with resistive material below, prepare as follows the gradient resistive aspect of two kinds of different-thickness:
Step S1: the silica gradient aspect 103B that deposit thickness is h2 on the bottom electrode preparing;
Step S2: the thin silicon oxide region of silica gradient aspect 103B lithographic definition that is h2 at thickness;
Step S3: this thin silicon oxide region of etching to residual thickness is h1, forms gradient aspect 103A.
From above-mentioned, its preparation process of the present embodiment only need increase some step process (step S2 and step S3) than traditional resistance-variable storing device method.Other preparation process with to enjoy preparation technology identical, does not repeat them here completely.
The resistance-variable storing device of the present embodiment can be stored three states, resets under (reset) state (the first store status), and thickness is that the resistive material of h1 and h2 is high-impedance state, and resistance is respectively r1 and r2(r1<r2); Under set (set) state (the 3rd store status), thickness is that the resistive material of h1 and h2 is low resistive state, and resistance is respectively r1 ' and r2 ' (r1 ' <r2 ' <<r1<r2); We know, for the resistive material that is h1 for the thickness compared with thin, V1 is lower for set voltage, and for the resistive material that is h2 for the thickness compared with thick, V2 is higher for set voltage, if apply the set voltage of a size between V1 and V2, so, at this moment this resistance-variable storing device is in the second store status.
When this resistance-variable storing device is during in the first store status, the resistive material of two kinds of thickness all under reset mode, total resistance R1=r1//r2.
When this resistance-variable storing device is during in the second store status, apply the set voltage of a size between set voltage V1 and set voltage V2, the resistive material generation resistive of thinner thickness, and there is not resistive in the thicker resistive material of thickness, R2=r1 ' //r2 ≈ r1 '.
When this resistance-variable storing device is during in the 3rd store status, apply a set voltage that is greater than V2, all there is resistive in the resistive material of two kinds of thickness, R3=r1 ' //r2 '.
In sum, according to magnitude relationship, R1>R2>R3, this resistance-variable storing device one has 3 resistance states.Certainly, before mention, by increasing again the change resistance layer of one or several thickness, can obtain identical with the present embodiment principle, have 4 or 4 above resistance states, it is higher that storage density can become, and do not repeat them here.
Therefore, description by the present embodiment can find out, compared with traditional scheme, the resistance variation memory structure that the utility model provides can be in the situation that not increasing material and process complexity, realize the multidigit storage of single memory cell, thereby improve the storage density of memory.
Above-described is only embodiment of the present utility model; described embodiment is not in order to limit scope of patent protection of the present utility model; therefore the equivalent structure that every utilization specification of the present utility model and accompanying drawing content are done changes, and in like manner all should be included in protection range of the present utility model.
Claims (5)
1. the RRAM memory cell structure that can realize multidigit storage, comprising: substrate, be positioned at the bottom electrode on described substrate, be positioned at the change resistance layer on described bottom electrode, and be positioned at the top electrode on described change resistance layer; It is characterized in that, described change resistance layer has the gradient aspect of multiple different-thickness, and the material of described gradient aspect is identical.
2. RRAM memory cell structure according to claim 1, is characterized in that, each gradient aspect area value of the upper surface of described gradient aspect is identical.
3. RRAM memory cell structure according to claim 1, is characterized in that, described change resistance layer is silica, germanium oxide or transition metal oxide.
4. RRAM memory cell structure according to claim 1, is characterized in that, the number of steps of described change resistance layer is three.
5. RRAM memory cell structure according to claim 1, is characterized in that, described substrate is silicon or Germanium semiconductor material.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320884857.5U CN203644823U (en) | 2013-12-30 | 2013-12-30 | RRAM (resistive random access memory) memory cell structure capable of realizing multi-bit memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320884857.5U CN203644823U (en) | 2013-12-30 | 2013-12-30 | RRAM (resistive random access memory) memory cell structure capable of realizing multi-bit memory |
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Granted publication date: 20140611 |