CN203632673U - Emergent reception detection circuit and optical line terminal - Google Patents
Emergent reception detection circuit and optical line terminal Download PDFInfo
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- CN203632673U CN203632673U CN201320785514.3U CN201320785514U CN203632673U CN 203632673 U CN203632673 U CN 203632673U CN 201320785514 U CN201320785514 U CN 201320785514U CN 203632673 U CN203632673 U CN 203632673U
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Abstract
The utility model discloses an emergent reception detection circuit and an optical line terminal. The emergent reception detection circuit comprises a reception light assembly, an emergent signal reception chip, and a control circuit. An energy storage capacitor is integrated in the emergent signal reception chip. When the emergent signal reception chip receives a trigger signal outputted by the control circuit, the emergent signal reception chip acquires response current outputted by the reception light assembly and transmits the response current to the energy storage capacitor for sampling and holding. The control circuit detects sampling voltage of the energy storage capacitor via a sampling output pin of the emergent signal reception chip and generates outward output of emergent detection signals. The utility model adopts a scheme using the emergent signal reception chip to replace a traditional discrete circuit design scheme, thereby completing the emergent signal reception detection task. The circuit structure is simple and the cost is low. Moreover, with the arrangement of a controllable discharge circuit, the whole emergent signal reception dynamic range is broadened and the precision of monitoring of optical signal reception of an OLT module is guaranteed.
Description
Technical field
The utility model belongs to optical communication technique field, relates to a kind of optical module being applied in optical communication system, specifically, relates to one and is applied in optical line terminal, for the burst of optical-fiber network being received to the circuit structure design detecting.
Background technology
Current, optical module is towards low-power consumption, low cost, high performance future development.For GPON system, the key technology of its realization comprises up channel multiplex technique, range finding and compensation technique, burst reception technique, service quality problem and DBA technology etc.Wherein, burst reception technique can help optical network management unit to find out the position of breaking down in optical fiber link, and then simplifies maintenance work, improves the reliability of system.And prominent transmitting/receiving signal correctly recovers the raising of dynamic range and a great problem that fast signal measuring ability is optical module, especially GPON OLT module faces.
At present, although it is many to meet the burst signal detection circuit arrangement of GPON agreement rated condition, but mostly need to design complicated discrete circuit structure and realize its function, not only there is larger design difficulty, and extended production time of burst receiving test circuit and optical module, cause the obvious lifting of optical module hardware cost.
Summary of the invention
The purpose of this utility model is to provide a kind of burst receiving test circuit, to solve existing burst signal detection circuit arrangement complex structure, problem that design difficulty is large.
For solving the problems of the technologies described above, the utility model is achieved by the following technical solutions:
A kind of burst receiving test circuit, comprises and receives optical assembly, burst receiving chip and control circuit; In described burst receiving chip, be integrated with storage capacitor, described burst receiving chip, in the time receiving the triggering signal of control circuit output, gathers the response current that receives optical assembly output, and is delivered to the storage capacitor maintenance of sampling; Described control circuit detects the sampled voltage of storage capacitor by the sampling output pin of burst receiving chip, and generation burst detection signal is externally exported.
Further, in described burst receiving chip, be integrated with mirror current source, receive the response current of described reception optical assembly output, and after dwindling according to preset proportion, transfer to the maintenance of sampling of described storage capacitor.
Further again, described burst receiving chip connects the response current output of described reception optical assembly by its mirror current source output pin, be also connected with the resistance device for response current being converted to voltage on described mirror current source output pin.
In order to meet the work requirements of mirror current source, in described burst receiving test circuit, be also provided with booster circuit, described burst receiving chip connects described booster circuit by its mirror current source input pin, receive the high direct voltage of booster circuit output, for the work of mirror current source provides direct voltage biasing.
In order to control the required high direct voltage of described booster circuit output mirror current source work, described control circuit outputs control signals to booster circuit, makes booster circuit the low-voltage dc power supply of input be converted to high direct voltage output under the control of control signal.
Further, on described burst receiving chip, be also integrated with image current sampling pin, described image current sampling pin, by sampling resistor ground connection, converts image current to voltage, for described storage capacitor charging, realize the sampling of prominent transmitting/receiving signal is kept.
In order to realize the accurate reception to the prominent transmitting/receiving signal of the next one, described control circuit is receiving after sampled voltage, output discharge signal is to the electric discharge pin of burst receiving chip, the electric charge storing in junction capacitance in mirror current source or parasitic capacitance is released fast, ready for receiving the arrival of next burst.
Based on above-mentioned burst receiving test circuit structure, the utility model also provides a kind of optical line terminal that adopts described burst receiving test circuit design, comprises and receives optical assembly, burst receiving chip and control circuit; In described burst receiving chip, be integrated with storage capacitor, described burst receiving chip, in the time receiving the triggering signal of control circuit output, gathers the response current that receives optical assembly output, and is delivered to the storage capacitor maintenance of sampling; Described control circuit detects the sampled voltage of storage capacitor by the sampling output pin of burst receiving chip, and generation burst detection signal is externally exported.
Further, described optical line terminal output burst detection signal is to the system end external with it, and the reset signal of receiving system end feedback transfers to the functional circuit that optical line terminal internal request resets before packet receives, to improve the dynamic range of the transmitting/receiving signal of dashing forward.
Further, in described optical line terminal, be also provided with limiting amplifier, described reception optical assembly converts the light signal receiving to the signal of telecommunication and transfers to described limiting amplifier by differential signal line, and carry out via described limiting amplifier, after the amplification processing of amplitude, exporting described system end to; In described differential signal line, be in series with ac coupling capacitor, be also connected with controllable discharge circuit on described differential signal line, the control end of described controllable discharge circuit receives the reset signal of described system end feedback.
Compared with prior art, advantage of the present utility model and good effect are: burst receiving test circuit of the present utility model adopts the burst receiving chip that is at least integrated with storage capacitor to replace the discrete circuit design in conventional art, and cooperation receives optical assembly and control circuit, complete the reception Detection task to burst, not only reduce circuit design difficulty, simplify circuit structure, reduce the hardware cost of optical line terminal, and by controlled controllable discharge circuit discharge time is set, can guarantee the correct recovery of primary optical signal light bag, and then improve the dynamic range of whole prominent transmitting/receiving signal, guarantee the monitoring precision of OLT optical module to receiving optical signals.
Read by reference to the accompanying drawings after embodiment of the present utility model, other features of the present utility model and advantage will become clearer.
Accompanying drawing explanation
Fig. 1 is the structural representation of GPON system uplink packet;
Fig. 2 is the schematic block circuit diagram of a kind of embodiment of the burst receiving test circuit that proposes of the utility model;
Fig. 3 is that happen suddenly shown in Fig. 2 burst of receiving test circuit receives detection signal sequential chart.
Embodiment
Below in conjunction with accompanying drawing, embodiment of the present utility model is described in more detail.
In GPON system, how uplink burst packet, for optical line terminal OLT module, is tested with quickly and accurately burst arrival and carries out accurately receiving most important to burst.In order to obtain higher bandwidth availability ratio, conventionally need GPON OLT to possess the signal testing function of setting up burst in several bits, under uplink burst pattern, each burst bag is carried out to input rapidly to realize optical line terminal OLT.
Realizing receiver side burst mode and apply why difficulty of required input, is because what adopt in GPON application is TDMA mode.The distance that arrives optical line terminal OLT due to different optical network unit ONU is unequal, and the light signal strength difference sent of the optical module of each ONU, the signal power that has caused OLT to receive is not identical at each time slot, thereby causes OLT easily to judge by accident.Fig. 1 is the GPON packet physical layer overhead (Physical-layer Overhead) that G.984.2 ITU-T stipulates, upstream rate is in the time of 1.244Gbps, the overhead of mandatory provision is 96bit, is made up of guard time (Guard Time) 32bit, lead code time (Preamble Time) 44bit and delimiter time (Delimiter Time) 20bit.Guard time refers to as avoiding signal packet conflict, the time interval providing between two continuous burst bags; Lead code is to extract for convenience phase place to recover to obtain bit synchronous and to receive signal amplitude, adds lead code " 101010 ... " before burst bag; And delimiter is to be a kind ofly used to indicate burst and to unwrap the special pattern of beginning, it can be used to carry out byte of sync.In addition, also stipulated CID(Consecutive Identical Digit) the longest permission 72bit of code.
As seen from Figure 1: if certain ONU is nearer apart from OLT, OLT receives a high-intensity signal, is then that certain remote ONU sends light signal when suddenly, and OLT is because just received high-intensity signal, and weak signal may be just wrong be read as 0 by 1, and can not identify.Vice versa.For this reason, need OLT to possess burst receiving function.The key that burst receives will re-establish rapidly decision threshold exactly in several bits, and receiving circuit correctly recovers data according to this thresholding.
The utility model is in order to meet the optical signal detecting requirement under burst mode, a kind of burst receiving test circuit of the burst receiving chip design that adopts low-power consumption, low cost, high integration has been proposed, guaranteeing under the prerequisite of receiving optical signals monitoring precision, reduce cost and the power consumption of GPON OLT, strengthened the flexibility of OLT modular design.
Take the optical line terminal based on GPON system (being GPON OLT) as example, elaborate concrete assembling structure and the operation principle thereof of described burst receiving test circuit by a specific embodiment below.
Shown in Figure 2, the burst receiving test circuit of the present embodiment is mainly made up of parts such as receiving optical assembly RA, burst receiving chip U1 and control circuit.Wherein, receive optical assembly RA for receiving up light signal, and generate response current Ipd and be sent to burst receiving chip U1, to realize reception and the detection to uplink burst signal.In described burst receiving chip U1, be integrated with storage capacitor Cs, for maintenance that uplink burst signal is sampled.Described burst receiving chip U1 is connected to control circuit, the triggering signal MCU_Triger of reception control circuit output, and in during described triggering signal MCU_Triger effectively, open the charge circuit of storage capacitor Cs, utilize the response current Ipd that receives optical assembly RA output for storage capacitor Cs charging, realize the sampling of uplink burst signal is kept.Described control circuit is by gathering the sampled voltage of storage capacitor Cs, can judge exactly and whether have prominent transmitting/receiving signal to arrive, and in the time detecting that prominent transmitting/receiving signal arrives, generate burst detection signal SD and externally export, to realize the indication that burst is arrived.
In the present embodiment, described control circuit preferably adopts a single-chip microprocessor MCU to coordinate simple peripheral circuit to set up and forms, shown in Figure 2.Select the described triggering signal MCU_Triger of a wherein road GPIO mouth P2 output of single-chip microprocessor MCU, and be sent to the triggering pin TRIGER of burst receiving chip U1, and then carry out break-make control to burst receiving chip U1 is inner for controlling the switching tube Q1 that described storage capacitor Cs discharges and recharges.
Also be integrated with mirror current source MIR in described burst receiving chip U1 inside, receive the response current Ipd of optical assembly RA output for mirror image, and transfer to described storage capacitor Cs by switching tube Q1, realize the sampling of prominent transmitting/receiving signal is kept.The mirror current source output pin MIROUT of burst receiving chip U1 is connected to the response current output of described reception optical assembly RA, and by a resistance device R1 ground connection, realizes the conversion from current signal to voltage signal by described resistance device R1.Described mirror current source MIR dwindles processing to response current Ipd according to preset proportion (being conventionally set as 5:1), and formation image current transfers to the image current sampling pin VIP of burst receiving chip U1.Described image current sampling pin VIP passes through a sampling resistor Rs ground connection, and then converts image current to mirror image voltage, is described storage capacitor Cs charging, realizes the sampling of prominent transmitting/receiving signal is kept.
In order to meet the work requirements of mirror current source MIR, the present embodiment has also designed booster circuit in described burst receiving test circuit, shown in Figure 2, for converting low-voltage dc power supply VCC to high direct voltage HV, export the mirror current source input pin MIRIN of burst receiving chip U1 to, and then setover for the work of mirror current source MIR provides required direct voltage.
For the amplitude of the high direct voltage HV to booster circuit output regulates, the control end of described booster circuit is connected to single-chip microprocessor MCU, for example connect an other road GPIO mouth P3 of MCU, for example receive MCU, by the control signal (pwm signal) of this road GPIO mouth P3 output, to regulate the frequency of oscillation of booster circuit internal oscillator circuit, realize the boosting inverter to low-voltage dc power supply VCC, and then output meets the high direct voltage HV of mirror current source MIR work requirements.
Owing to having parasitic capacitance or junction capacitance in mirror current source MIR inside, in the time that mirror current source MIR carries out mirror image output to receiving the response current Ipd of optical assembly RA output, described response current Ipd can be parasitic capacitance or the junction capacitance charging of mirror current source MIR inside simultaneously.In order not affect the next accurate recovery that receives signal bag, need to be before the next one receives the arrival of signal bag, the electric charge remaining in parasitic capacitance or the junction capacitance of mirror current source MIR inside is released in time, so ready for receiving next light signal on the horizon.For this reason, the present embodiment designs described single-chip microprocessor MCU and is gathering after the sampled voltage of storage capacitor Cs, output discharge signal MCU_Discharge is to the electric discharge pin DISCHARGE of burst receiving chip U1, and then the switching tube Q2 conducting of control burst receiving chip U1 inside, the electric charge storing in junction capacitance in mirror current source MIR or parasitic capacitance is released over the ground fast, ready for receiving the arrival of next burst.
In the present embodiment, preferably adopt the described discharge signal MCU_Discharge of an other road GPIO mouth P1 output of MCU, transfer to the electric discharge pin DISCHARGE of burst receiving chip U1.For the collection of sampled voltage in storage capacitor Cs, after can first utilizing the inner integrated amplifier of burst receiving chip U1 to amplify the sampled voltage of storage capacitor Cs, export the analog-to-digital conversion interface ADC of MCU to by the sampling output pin VOP of burst receiving chip U1, or convert to after digital signal by analog to digital conversion circuit independently, then be sent to the digital interface of MCU.MCU according to the sampled voltage receiving, has judged whether that light signal arrives, and has generated the burst detection signal SD of Transistor-Transistor Logic level, exported the system end of the described optical line terminal OLT of management by the input pin of optical line terminal OLT to.System end, according to the level state of the burst detection signal SD receiving, can be judged and have or not light signal input.When system end has been judged light signal when input, the time of advent that can utilize SD input to go out light signal on the one hand, be beneficial to the utilance of bandwidth; Generating reset signal RESET on the other hand, feed back to described optical line terminal OLT, control the corresponding function circuit reset in OLT module, such as control connection is for example, in energy-storage travelling wave tube (being connected on the capacity cell C1, the C2 that receive between optical assembly APD and the limiting amplifier LA input) electric discharge of limiting amplifier LA front end, to prepare to receive packet on the horizon.
In the present embodiment, described reception optical assembly RA utilizes its inner integrated avalanche photodide APD(or PIN type photodiode) receive the light signal of inputting by coupling fiber, and light signal is converted to after the signal of telecommunication, export transimpedance amplifier TIA to and carry out preposition amplification processing, and generate the signal of telecommunication of difference form, by difference signal terminal RXIN+, the RXIN-output of transimpedance amplifier TIA.Described differential signal isolates out after flip-flop wherein via a road ac coupling capacitor C1, C2 separately, transfer to the amplification processing that limiting amplifier LA carries out amplitude, then export system end to by differential signal lead-out terminal RXOUT+, the RXOUT-of limiting amplifier LA, to realize the reception of system end to up optical network data.
In order to improve the dynamic range of whole prominent transmitting/receiving signal, the present embodiment is provided with respectively a controllable discharge circuit in the differential data line of two ac coupling capacitor C1, C2 connection limiting amplifier LA, shown in Figure 2.The reset signal RESET feeding back by system end is transferred to the control end of these two controllable discharge circuits, control the discharge time of two controllable discharge circuits, make ac coupling capacitor C1 and C2 repid discharge, to guarantee that the subsequent optical signal light signal bag that especially intensity is less can correctly recover, and then improve the dynamic range of whole prominent transmitting/receiving signal.
The operation principle of burst receiving test circuit the present embodiment being proposed below in conjunction with Fig. 2, Fig. 3 is at length set forth.
System end passes through I
2c bus sends instructions under connected optical line terminal OLT, while requiring it to receive upstream data, the effective triggering signal MCU_Triger of MCU output low level is to the triggering pin TRIGER of burst receiving chip U1, and control integration is in the switching tube Q1 of burst receiving chip U1 inside conducting.Burst receiving chip U1 utilizes its inner integrated mirror current source MIR to carry out mirror image output to the response current Ipd that receives optical assembly RA output, and by sampling resistor Rs, current conversion is become after voltage, be the storage capacitor Cs charging that is integrated in burst receiving chip U1 inside by switching tube Q1.After charging finishes, triggering signal MCU_Triger is set to high level by MCU, and control switch pipe Q1 disconnects, and then the voltage of the sampling output pin VOP to burst receiving chip U1 carries out sampling processing.After sampling processing finishes, MCU sends the electric discharge pin DISCHARGE of the effective discharge signal MCU_Discharge of high level to burst receiving chip U1, make this pin become high level from low level, and then control the switching tube Q2 conducting of burst receiving chip U1 inside.Because the conducting resistance of switching tube Q2 is less, therefore can carry out repid discharge to the electric charge storing in the parasitic capacitance of mirror current source MIR inside or junction capacitance, thereby reduce to disturb bag tested bag to be received to the impact of detection signal, guarantee the monitoring precision of burst receiving optical signals.
After switching tube Q1 disconnects, the electric charge storing in storage capacitor Cs is via the inner integrated discharge circuit electric discharge of burst receiving chip U1, and then ready for detecting the arrival of next burst.
The present embodiment is by adopting high integrated burst receiving chip U1 to replace traditional discrete circuit design, realize accurate reception and detection to burst luminous signal, guaranteeing, under the prerequisite of receiving optical signals monitoring precision, to have simplified circuit design, reduce system power dissipation.Be applied in the circuit design of GPON OLT, can be improved bandwidth availability ratio, make the optical communication performance of GPON OLT module more stable, reliable.
Certainly, above embodiment is only in order to the technical solution of the utility model to be described, but not is limited; Although the utility model is had been described in detail with reference to previous embodiment, for the person of ordinary skill of the art, the technical scheme that still can record previous embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of the utility model technical scheme required for protection.
Claims (10)
1. a burst receiving test circuit, is characterized in that: comprise and receive optical assembly, burst receiving chip and control circuit; In described burst receiving chip, be integrated with storage capacitor, described burst receiving chip, in the time receiving the triggering signal of control circuit output, gathers the response current that receives optical assembly output, and is delivered to the storage capacitor maintenance of sampling; Described control circuit detects the sampled voltage of storage capacitor by the sampling output pin of burst receiving chip, and generation burst detection signal is externally exported.
2. burst receiving test circuit according to claim 1, it is characterized in that: in described burst receiving chip, be integrated with mirror current source, receive the response current of described reception optical assembly output, and after dwindling according to preset proportion, transfer to the maintenance of sampling of described storage capacitor.
3. burst receiving test circuit according to claim 2, it is characterized in that: described burst receiving chip connects the response current output of described reception optical assembly by its mirror current source output pin, on described mirror current source output pin, be also connected with the resistance device for response current being converted to voltage.
4. burst receiving test circuit according to claim 2, is characterized in that: described burst receiving chip connects booster circuit by its mirror current source input pin, receives the high direct voltage of booster circuit output.
5. burst receiving test circuit according to claim 4, is characterized in that: the control signal of described booster circuit reception control circuit output converts the low-voltage dc power supply of input to high direct voltage output under the control of control signal.
6. burst receiving test circuit according to claim 2, is characterized in that: on described burst receiving chip, be also integrated with image current sampling pin, described image current sampling pin is by sampling resistor ground connection.
7. according to the burst receiving test circuit described in any one in claim 1 to 6, it is characterized in that: described control circuit is receiving after sampled voltage, output discharge signal is to the electric discharge pin of burst receiving chip.
8. an optical line terminal, is characterized in that: be provided with the burst receiving test circuit as described in any one in the claims 1 to 7.
9. optical line terminal according to claim 8, it is characterized in that: described optical line terminal output burst detection signal is to the system end external with it, and the reset signal of receiving system end feedback transfers to the functional circuit that optical line terminal internal request resets before packet receives.
10. optical line terminal according to claim 9, it is characterized in that: in described optical line terminal, be also provided with limiting amplifier, described reception optical assembly converts the light signal receiving to the signal of telecommunication and transfers to described limiting amplifier by differential signal line, and carry out via described limiting amplifier, after the amplification processing of amplitude, exporting described system end to; In described differential signal line, be in series with ac coupling capacitor, be also connected with controllable discharge circuit on described differential signal line, the control end of described controllable discharge circuit receives the reset signal of described system end feedback.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320785514.3U CN203632673U (en) | 2013-12-04 | 2013-12-04 | Emergent reception detection circuit and optical line terminal |
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| CN201320785514.3U CN203632673U (en) | 2013-12-04 | 2013-12-04 | Emergent reception detection circuit and optical line terminal |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330323A (en) * | 2016-09-18 | 2017-01-11 | 青岛海信宽带多媒体技术有限公司 | OLT optical module and OLT |
| CN108551360A (en) * | 2018-04-17 | 2018-09-18 | 青岛海信宽带多媒体技术有限公司 | Light module test method, system, circuit and optical module |
-
2013
- 2013-12-04 CN CN201320785514.3U patent/CN203632673U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106330323A (en) * | 2016-09-18 | 2017-01-11 | 青岛海信宽带多媒体技术有限公司 | OLT optical module and OLT |
| US10110316B2 (en) | 2016-09-18 | 2018-10-23 | Hisense Broadband Multimedia Technologies Co., Ltd. | OLT optical module and OLT |
| CN106330323B (en) * | 2016-09-18 | 2019-01-08 | 青岛海信宽带多媒体技术有限公司 | OLT optical module and OLT |
| CN108551360A (en) * | 2018-04-17 | 2018-09-18 | 青岛海信宽带多媒体技术有限公司 | Light module test method, system, circuit and optical module |
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Granted publication date: 20140604 Termination date: 20191204 |