CN203617946U - Direct-current brush motor integrated controller - Google Patents
Direct-current brush motor integrated controller Download PDFInfo
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- CN203617946U CN203617946U CN201320691365.4U CN201320691365U CN203617946U CN 203617946 U CN203617946 U CN 203617946U CN 201320691365 U CN201320691365 U CN 201320691365U CN 203617946 U CN203617946 U CN 203617946U
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Abstract
The utility model discloses a direct-current brush motor integrated controller. The controller comprises a driving circuit and a gear control circuit. The driving circuit comprises two MOS pipe half-bridge driving chips, two diodes, two tantalum capacitors C7, six leaded multilayer ceramic capacitors, four MOS transistors and four resistors. The gear control circuit comprises three pedestals, one control chip, two leaded multilayer ceramic capacitors C9, three resistors and a button K1. According to the controller disclosed by the utility model, a plurality of drivers can be connected in parallel and used when adopting a digital speed regulation mode. A main controller controls each driver respectively through a multichannel complementation PWM wave so as to reach linkage control.
Description
Technical field
The utility model relates to the speed control device of DC MOTOR CONTROL aspect, particularly relates to jointly controlling of polytype direct current machine, is specifically related to a kind of brush direct current motor general controller.
Technical background
Along with industrial expansion, cost of labor improves gradually, and a large amount of Industry Control all needs cost-saving, enhances productivity, and uses intelligent system production control.A large amount of motors that use in industrial production, can have a kind of electric machine controller of intelligence, to improving industrial production structure, have very large help.DC motor speed-regulating control appliance can only be controlled separately a kind of type motor at present, and every kind of motor must configure an independent controller, and equipment cost is high.Each controller can only work independently, and can not be combined into systematic unity control, is unfavorable for industrial intellectuality.
Summary of the invention
The defect existing in order to overcome above-mentioned technology, the utility model provide a kind of formed by single-chip computer control system and metal-oxide-semiconductor bridge drive circuit have brush, a brshless DC motor general controller.
Receive and process input signal by Single Chip Microcomputer (SCM) system, and output control metal-oxide-semiconductor bridge drive circuit, reach its rotating speed control of rotating of controlling motor.Gear switch circuit, by switching output mode gear, after single-chip microcomputer is checked through gear signal, corresponding implementation has brush pattern and brushless mode activated.By switching input pattern gear, single-chip microcomputer can be accepted analog signal and two kinds of signals of pwm signal.When All Drives switches to PWM pattern, can control respectively All Drives by a master controller output multi-channel pwm signal.
A kind of brush direct current motor general controller of the utility model comprises drive circuit and gear control circuit;
Described drive circuit comprises the first metal-oxide-semiconductor half-bridge driven chip (IR2104) U1, the second metal-oxide-semiconductor half-bridge driven chip (IR2104) U2, the first diode D1, the second diode D2, the first tantalum capacitor C 3, the second tantalum capacitor C 7, the first leaded multilayer ceramic capacitor C1, the second leaded multilayer ceramic capacitor C2, the 3rd leaded multilayer ceramic capacitor C4, the 4th leaded multilayer ceramic capacitor C5, the 5th leaded multilayer ceramic capacitor C6, the 6th leaded multilayer ceramic capacitor C8, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, the 4th metal-oxide-semiconductor Q4, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4.The model of the first metal-oxide-semiconductor half-bridge driven chip U1 and the second metal-oxide-semiconductor half-bridge driven chip U2 is IR2104;
1 pin of described metal-oxide-semiconductor half-bridge driven chip U1, 3 pin and the first tantalum capacitor C 3 anodes, the anodic bonding of the first diode D1 also connects VCC end, 2 pin connect 16 pin of controller U3, input signal PWM1, 4 pin connect the negative electrode of the first tantalum capacitor C 3 and are connected to GND ground, 5 pin are connected with one end of the second resistance R 2, one end of 6 pin and the second leaded multilayer ceramic capacitor C2, the source electrode of the first metal-oxide-semiconductor Q1, the drain electrode of the second metal-oxide-semiconductor Q2, one end of the first leaded multilayer ceramic capacitor C1, one end of the 3rd leaded multilayer ceramic capacitor C4 connects and as output JP1, 7 pin are connected with one end of the first resistance R 1, the negative electrode of 8 pin and the first diode D1, the other end of the second leaded multilayer ceramic capacitor C2 connects, the other end of the first resistance R 1 is connected with the grid of the first metal-oxide-semiconductor Q1, the drain electrode of the first metal-oxide-semiconductor Q1 is connected with the other end of the first leaded multilayer ceramic capacitor C1 and meets vcc, the other end of the second resistance R 2 is connected with the grid of the second metal-oxide-semiconductor Q2, the source electrode of the second metal-oxide-semiconductor Q2 is connected with the other end of the 3rd leaded multilayer ceramic capacitor C4 and is connected to GND,
1 pin of the second metal-oxide-semiconductor half-bridge driven chip U2, 3 pin and the second tantalum capacitor C 7 anodes, the anodic bonding of diode D2 also connects VCC end, 2 pin connect 15 pin of controller U3, input signal PWM2, 4 pin connect the negative electrode of the second tantalum capacitor C 7 and are connected to GND ground, 5 pin are connected with one end of the 4th resistance R 4, one end of 6 pin and the 5th leaded multilayer ceramic capacitor C6, the source electrode of the 3rd metal-oxide-semiconductor Q3, the drain electrode of the 4th metal-oxide-semiconductor Q4, one end of the 5th leaded multilayer ceramic capacitor C5, one end of the 6th leaded multilayer ceramic capacitor C8 connects and as output JP2, 7 pin are connected with one end of the 3rd resistance R 3, the negative electrode of 8 pin and the second diode D2, the other end of the 5th leaded multilayer ceramic capacitor C6 connects, the other end of the 3rd resistance R 3 is connected with the grid of the 3rd metal-oxide-semiconductor Q3, the drain electrode of the 3rd metal-oxide-semiconductor Q3 is connected with the other end of the 4th leaded multilayer ceramic capacitor C5 and meets vcc, the other end of the 4th resistance R 4 is connected with the grid of the 4th metal-oxide-semiconductor Q4, the source electrode of the 4th metal-oxide-semiconductor Q4 is connected with the other end of the 6th leaded multilayer ceramic capacitor C8 and is connected to GND.
Gear control circuit comprises the first stand P1, the second stand P2, the 3rd stand P3, control chip U3, the 7th leaded multilayer ceramic capacitor C9 and the 8th leaded multilayer ceramic capacitor C10, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7 and button K1; Control chip model is STM8F3P6;
1 pin of control chip U3 connects 1 pin of the 3rd stand P3, and 2 pin of control chip U3 connect 2 pin of the 3rd stand P3, and 3 pin of control chip U3 connect 2 pin of the second stand P2, 1 pin of the second stand P2 meets VCC, 3 pin connect GND ground, 4 pin of control chip U3 and one end of button K1, one end of the 8th leaded multilayer ceramic capacitor C10, one end of the 7th resistance R 7 connects, 7 pin of control chip U3 are connected with one end of the 7th leaded multilayer ceramic capacitor C9 and receive GND, 8 pin of control chip U3 are connected with other one end of capacitor C 9 and meet 3.3V, 9 pin of control chip U3 are connected with one end of the 5th resistance R 5, the other end of the 5th resistance R 5 is connected to 3.3V power supply, 18 pin of control chip U4 are connected with one end of the 6th resistance R 6, the other end of the 6th resistance R 6 connects external signal SWIM, 16 pin of control chip U3 connect external signal PWM1, 15 pin of control chip U3 connect external signal PWM2, 12 pin of control chip U3 connect 1 pin of the first stand P1, 11 pin of control chip U3 connect 3 pin of the first stand P1, 2 pin of the first stand P1 meet VCC, the other end of button K1 is connected with the other end of the 8th leaded multilayer ceramic capacitor C10 and meets GND, another termination 3.3V power supply of the 7th resistance R 7, all the other pins of control chip U3 are built on stilts.
The beneficial effects of the utility model:
Stand P1 order double-pole double throw switch, can select control model.
1,, when 1 of P1,2 pin are connected, driver uses traditional analog speed-regulating mode.Can use traditional potentiometer switch, connect stand P2, control electric machine rotation, control rotating speed.
2,, when 2 of P1,3 pin are connected, driver is switched to digital speed-control pattern.Can use the complementary PWM ripple of digital signal, connect stand P3 input signal, control motor positive and inverse and speed governing.
3,, when multiple drivers use digital speed-control pattern, can in parallelly use.Master controller, by the complementary PWM ripple of multichannel, controls respectively each driver, reaches interlock and controls.
4, the K1 that pushes button, controller resets, and restarts.
Accompanying drawing explanation
Fig. 1 metal-oxide-semiconductor bridge drive circuit;
Fig. 2 gear and control system.
embodiment
Understand in order to make this use novel design feature, technological means to be easy to understand, further set forth the utility model below in conjunction with specific embodiment.
A kind of brush direct current motor general controller of the utility model comprises drive circuit and gear control circuit;
As shown in Figure 1, described drive circuit comprises the first metal-oxide-semiconductor half-bridge driven chip (IR2104) U1, the second metal-oxide-semiconductor half-bridge driven chip (IR2104) U2, the first diode D1, the second diode D2, the first tantalum capacitor C 3, the second tantalum capacitor C 7, the first leaded multilayer ceramic capacitor C1, the second leaded multilayer ceramic capacitor C2, the 3rd leaded multilayer ceramic capacitor C4, the 4th leaded multilayer ceramic capacitor C5, the 5th leaded multilayer ceramic capacitor C6, the 6th leaded multilayer ceramic capacitor C8, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, the 4th metal-oxide-semiconductor Q4, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4.The model of the first metal-oxide-semiconductor half-bridge driven chip U1 and the second metal-oxide-semiconductor half-bridge driven chip U2 is IR2104;
1 pin of described metal-oxide-semiconductor half-bridge driven chip U1, 3 pin and the first tantalum capacitor C 3 anodes, the anodic bonding of the first diode D1 also connects VCC end, 2 pin connect 16 pin of controller U3, input signal PWM1, 4 pin connect the negative electrode of the first tantalum capacitor C 3 and are connected to GND ground, 5 pin are connected with one end of the second resistance R 2, one end of 6 pin and the second leaded multilayer ceramic capacitor C2, the source electrode of the first metal-oxide-semiconductor Q1, the drain electrode of the second metal-oxide-semiconductor Q2, one end of the first leaded multilayer ceramic capacitor C1, one end of the 3rd leaded multilayer ceramic capacitor C4 connects and as output JP1, 7 pin are connected with one end of the first resistance R 1, the negative electrode of 8 pin and the first diode D1, the other end of the second leaded multilayer ceramic capacitor C2 connects, the other end of the first resistance R 1 is connected with the grid of the first metal-oxide-semiconductor Q1, the drain electrode of the first metal-oxide-semiconductor Q1 is connected with the other end of the first leaded multilayer ceramic capacitor C1 and meets vcc, the other end of the second resistance R 2 is connected with the grid of the second metal-oxide-semiconductor Q2, the source electrode of the second metal-oxide-semiconductor Q2 is connected with the other end of the 3rd leaded multilayer ceramic capacitor C4 and is connected to GND,
1 pin of the second metal-oxide-semiconductor half-bridge driven chip U2, 3 pin and the second tantalum capacitor C 7 anodes, the anodic bonding of diode D2 also connects VCC end, 2 pin connect 15 pin of controller U3, input signal PWM2, 4 pin connect the negative electrode of the second tantalum capacitor C 7 and are connected to GND ground, 5 pin are connected with one end of the 4th resistance R 4, one end of 6 pin and the 5th leaded multilayer ceramic capacitor C6, the source electrode of the 3rd metal-oxide-semiconductor Q3, the drain electrode of the 4th metal-oxide-semiconductor Q4, one end of the 5th leaded multilayer ceramic capacitor C5, one end of the 6th leaded multilayer ceramic capacitor C8 connects and as output JP2, 7 pin are connected with one end of the 3rd resistance R 3, the negative electrode of 8 pin and the second diode D2, the other end of the 5th leaded multilayer ceramic capacitor C6 connects, the other end of the 3rd resistance R 3 is connected with the grid of the 3rd metal-oxide-semiconductor Q3, the drain electrode of the 3rd metal-oxide-semiconductor Q3 is connected with the other end of the 4th leaded multilayer ceramic capacitor C5 and meets vcc, the other end of the 4th resistance R 4 is connected with the grid of the 4th metal-oxide-semiconductor Q4, the source electrode of the 4th metal-oxide-semiconductor Q4 is connected with the other end of the 6th leaded multilayer ceramic capacitor C8 and is connected to GND.
As shown in Figure 2, gear control circuit comprises the first stand P1, the second stand P2, the 3rd stand P3, control chip U3, the 7th leaded multilayer ceramic capacitor C9 and the 8th leaded multilayer ceramic capacitor C10, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7 and button K1; Control chip model is STM8F3P6;
1 pin of control chip U3 connects 1 pin of the 3rd stand P3, and 2 pin of control chip U3 connect 2 pin of the 3rd stand P3, and 3 pin of control chip U3 connect 2 pin of the second stand P2, 1 pin of the second stand P2 meets VCC, 3 pin connect GND ground, 4 pin of control chip U3 and one end of button K1, one end of the 8th leaded multilayer ceramic capacitor C10, one end of the 7th resistance R 7 connects, 7 pin of control chip U3 are connected with one end of the 7th leaded multilayer ceramic capacitor C9 and receive GND, 8 pin of control chip U3 are connected with other one end of capacitor C 9 and meet 3.3V, 9 pin of control chip U3 are connected with one end of the 5th resistance R 5, the other end of the 5th resistance R 5 is connected to 3.3V power supply, 18 pin of control chip U4 are connected with one end of the 6th resistance R 6, the other end of the 6th resistance R 6 connects external signal SWIM, 16 pin of control chip U3 connect external signal PWM1, 15 pin of control chip U3 connect external signal PWM2, 12 pin of control chip U3 connect 1 pin of the first stand P1, 11 pin of control chip U3 connect 3 pin of the first stand P1, 2 pin of the first stand P1 meet VCC, the other end of button K1 is connected with the other end of the 8th leaded multilayer ceramic capacitor C10 and meets GND, another termination 3.3V power supply of the 7th resistance R 7, all the other pins of control chip U3 are built on stilts.
Embodiment:
Stand P1 order double-pole double throw switch, selects control model.Interface JP1, JP2 connect respectively to need to control brushless motor two ends.
1, switch connection that P1 connects 1,2 pin, driver switches to traditional analog speed-regulating mode.Use traditional potentiometer switch, control driver.Potentiometer switch is connected stand P2, and potentiometer centre tap connects 2 pin of P2, and two ends connect respectively 1,3 pin of P2.Regulator potentiometer switch, the resistance size of adjustment potentiometer centre tap end place in circuit, changes the 2 pin voltages of P2 just, to changing the rotating speed of motor, reaches the function of controlling motor speed.
2, switch connection that P1 connects 2,3 pin, driver is switched to digital speed-control pattern.Use the complementary PWM ripple of digital signal, control driver.Derived digital signal signaling interface is connected stand P3 input signal, controls motor positive and inverse and speed governing.1 pin of P3 connects high level signal, and 2 pin connect low level signal, motor forward; Regulate the duty ratio of PWM, can regulate the rotating speed of motor.2 pin of P3 connect high level signal, and 1 pin connects low level signal, motor reversal; Regulate the duty ratio of PWM, can regulate the rotating speed of motor.
3, multiple driver switch connection that P1 connects 2,3 pin, while using digital speed-control pattern, can in parallelly use.Use a master controller, by the complementary PWM ripple of multichannel, connect respectively the interface of each controller P3, control respectively each driver, reach the function that interlock is controlled.
Claims (1)
1. a brush direct current motor general controller, comprises drive circuit and gear control circuit;
It is characterized in that: described drive circuit comprises the first metal-oxide-semiconductor half-bridge driven chip U1, the second metal-oxide-semiconductor half-bridge driven chip U2, the first diode D1, the second diode D2, the first tantalum capacitor C 3, the second tantalum capacitor C 7, the first leaded multilayer ceramic capacitor C1, the second leaded multilayer ceramic capacitor C2, the 3rd leaded multilayer ceramic capacitor C4, the 4th leaded multilayer ceramic capacitor C5, the 5th leaded multilayer ceramic capacitor C6, the 6th leaded multilayer ceramic capacitor C8, the first metal-oxide-semiconductor Q1, the second metal-oxide-semiconductor Q2, the 3rd metal-oxide-semiconductor Q3, the 4th metal-oxide-semiconductor Q4, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4; The model of the first metal-oxide-semiconductor half-bridge driven chip U1 and the second metal-oxide-semiconductor half-bridge driven chip U2 is IR2104;
1 pin of described metal-oxide-semiconductor half-bridge driven chip U1, 3 pin and the first tantalum capacitor C 3 anodes, the anodic bonding of the first diode D1 also connects VCC end, 2 pin connect 16 pin of controller U3, input signal PWM1, 4 pin connect the negative electrode of the first tantalum capacitor C 3 and are connected to GND ground, 5 pin are connected with one end of the second resistance R 2, one end of 6 pin and the second leaded multilayer ceramic capacitor C2, the source electrode of the first metal-oxide-semiconductor Q1, the drain electrode of the second metal-oxide-semiconductor Q2, one end of the first leaded multilayer ceramic capacitor C1, one end of the 3rd leaded multilayer ceramic capacitor C4 connects and as output JP1, 7 pin are connected with one end of the first resistance R 1, the negative electrode of 8 pin and the first diode D1, the other end of the second leaded multilayer ceramic capacitor C2 connects, the other end of the first resistance R 1 is connected with the grid of the first metal-oxide-semiconductor Q1, the drain electrode of the first metal-oxide-semiconductor Q1 is connected with the other end of the first leaded multilayer ceramic capacitor C1 and meets vcc, the other end of the second resistance R 2 is connected with the grid of the second metal-oxide-semiconductor Q2, the source electrode of the second metal-oxide-semiconductor Q2 is connected with the other end of the 3rd leaded multilayer ceramic capacitor C4 and is connected to GND,
1 pin of the second metal-oxide-semiconductor half-bridge driven chip U2, 3 pin and the second tantalum capacitor C 7 anodes, the anodic bonding of diode D2 also connects VCC end, 2 pin connect 15 pin of controller U3, input signal PWM2, 4 pin connect the negative electrode of the second tantalum capacitor C 7 and are connected to GND ground, 5 pin are connected with one end of the 4th resistance R 4, one end of 6 pin and the 5th leaded multilayer ceramic capacitor C6, the source electrode of the 3rd metal-oxide-semiconductor Q3, the drain electrode of the 4th metal-oxide-semiconductor Q4, one end of the 5th leaded multilayer ceramic capacitor C5, one end of the 6th leaded multilayer ceramic capacitor C8 connects and as output JP2, 7 pin are connected with one end of the 3rd resistance R 3, the negative electrode of 8 pin and the second diode D2, the other end of the 5th leaded multilayer ceramic capacitor C6 connects, the other end of the 3rd resistance R 3 is connected with the grid of the 3rd metal-oxide-semiconductor Q3, the drain electrode of the 3rd metal-oxide-semiconductor Q3 is connected with the other end of the 4th leaded multilayer ceramic capacitor C5 and meets vcc, the other end of the 4th resistance R 4 is connected with the grid of the 4th metal-oxide-semiconductor Q4, the source electrode of the 4th metal-oxide-semiconductor Q4 is connected with the other end of the 6th leaded multilayer ceramic capacitor C8 and is connected to GND,
Gear control circuit comprises the first stand P1, the second stand P2, the 3rd stand P3, control chip U3, the 7th leaded multilayer ceramic capacitor C9 and the 8th leaded multilayer ceramic capacitor C10, the 5th resistance R 5, the 6th resistance R 6, the 7th resistance R 7 and button K1; Control chip model is STM8F3P6;
1 pin of control chip U3 connects 1 pin of the 3rd stand P3, and 2 pin of control chip U3 connect 2 pin of the 3rd stand P3, and 3 pin of control chip U3 connect 2 pin of the second stand P2, 1 pin of the second stand P2 meets VCC, 3 pin connect GND ground, 4 pin of control chip U3 and one end of button K1, one end of the 8th leaded multilayer ceramic capacitor C10, one end of the 7th resistance R 7 connects, 7 pin of control chip U3 are connected with one end of the 7th leaded multilayer ceramic capacitor C9 and receive GND, 8 pin of control chip U3 are connected with other one end of capacitor C 9 and meet 3.3V, 9 pin of control chip U3 are connected with one end of the 5th resistance R 5, the other end of the 5th resistance R 5 is connected to 3.3V power supply, 18 pin of control chip U4 are connected with one end of the 6th resistance R 6, the other end of the 6th resistance R 6 connects external signal SWIM, 16 pin of control chip U3 connect external signal PWM1, 15 pin of control chip U3 connect external signal PWM2, 12 pin of control chip U3 connect 1 pin of the first stand P1, 11 pin of control chip U3 connect 3 pin of the first stand P1, 2 pin of the first stand P1 meet VCC, the other end of button K1 is connected with the other end of the 8th leaded multilayer ceramic capacitor C10 and meets GND, another termination 3.3V power supply of the 7th resistance R 7, all the other pins of control chip U3 are built on stilts.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320691365.4U CN203617946U (en) | 2013-11-05 | 2013-11-05 | Direct-current brush motor integrated controller |
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| CN201320691365.4U CN203617946U (en) | 2013-11-05 | 2013-11-05 | Direct-current brush motor integrated controller |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103607148A (en) * | 2013-11-05 | 2014-02-26 | 杭州电子科技大学 | Direct-current brush motor integration controller |
| CN111525869A (en) * | 2020-05-20 | 2020-08-11 | 浙江工商职业技术学院 | DC brush and brushless motor integrated controller |
-
2013
- 2013-11-05 CN CN201320691365.4U patent/CN203617946U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103607148A (en) * | 2013-11-05 | 2014-02-26 | 杭州电子科技大学 | Direct-current brush motor integration controller |
| CN103607148B (en) * | 2013-11-05 | 2016-08-24 | 杭州电子科技大学 | Direct-current brush motor integration controller |
| CN111525869A (en) * | 2020-05-20 | 2020-08-11 | 浙江工商职业技术学院 | DC brush and brushless motor integrated controller |
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Granted publication date: 20140528 Termination date: 20161105 |