CN203616609U - Grid frequency timing circuit - Google Patents
Grid frequency timing circuit Download PDFInfo
- Publication number
- CN203616609U CN203616609U CN201320880244.4U CN201320880244U CN203616609U CN 203616609 U CN203616609 U CN 203616609U CN 201320880244 U CN201320880244 U CN 201320880244U CN 203616609 U CN203616609 U CN 203616609U
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- triode
- timing circuit
- resistance
- diode
- resistor
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- Expired - Lifetime
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- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000009418 renovation Methods 0.000 description 1
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Abstract
The utility model provides a grid frequency timing circuit. The grid frequency timing circuit comprises a triode Q2, resistors R14 and R15 and a diode D2. The base electrode of the triode Q2 is connected with one end of the resistor R14 and one end of the resistor R15, and is connected with the negative electrode of the diode D2. The other end of the resistor R14 is connected with the ground. The emitting electrode of the triode Q2 is connected with the ground. The positive electrode of the diode D2 is connected with the ground. The other end of the resistor R15 is connected with an alternating current grid CAN. The collector electrode of the triode Q2 is connected with one end of a resistor R16, and is connected with a port of a timing chip. The other end of the resistor R16 is connected with a power supply. The grid frequency timing circuit is advantaged by accurate timing and cost saving. The grid frequency timing circuit saves the output port resource and raises the product competitiveness.
Description
Technical field
The utility model is a kind of mains frequency timing circuit, belongs to the renovation technique of mains frequency timing circuit.
background technology
At present, most electronic products adopt Tao Zhen to do the timing of chip as the principal earthquake of chip, as shown in Figure 2, because the error ratio of Tao Zhen is larger, generally in 5/1000ths left and right, more accurate Tao Zhen or crystal oscillator need higher price, and this kind of scheme need 2 output ports to be used as the port of Tao Zhen, give growing tension resources of chip band pressure.
Utility model content
The purpose of this utility model is to consider the problems referred to above and provides a kind of energy accurate timing, and cost-effective mains frequency timing circuit.The utility model has been saved delivery outlet resource, has promoted product competitiveness.
The technical solution of the utility model is: mains frequency timing circuit of the present utility model, include triode Q2, resistance R 14 and R15, diode D2, wherein the base stage of triode Q2 is connected with one end of resistance R 14 and R15 and is connected with the negative electrode of diode D2, the plus earth of the other end ground connection of resistance R 14, the grounded emitter of triode Q2 and diode D2, the other end of resistance R 15 connects AC network CAN, the collector of triode Q2 is connected with one end of resistance R 16 and is connected with the port of timing chip, and the other end of resistance R 16 is connected with power supply.
The utility model is used for the structure of detection of grid frequency owing to adopting by a ball bearing made using, be used as the benchmark of timing by this frequency, and adopt in chip shake as time base, utilize the reset mouth that can only serve as input port that chip seldom uses just can realize more accurate timing, and saved 2 valuable delivery outlet resources for chip, promote product competitiveness.The utility model circuit component quantity is few, and circuit is realized simple and reliable, and applicable scope is wide.The utility model is that a kind of cost use is low, economizes port, more accurate timing, convenient and practical mains frequency timing circuit applied widely.
Accompanying drawing explanation
Fig. 1 is schematic diagram of the present utility model;
Fig. 2 is the schematic diagram of existing product.
Embodiment
Embodiment:
Schematic diagram of the present utility model as shown in Figure 1, mains frequency timing circuit of the present utility model, include triode Q2, resistance R 14 and R15, diode D2, wherein the base stage of triode Q2 is connected with one end of resistance R 14 and R15 and is connected with the negative electrode of diode D2, the plus earth of the other end ground connection of resistance R 14, the grounded emitter of triode Q2 and diode D2, the other end of resistance R 15 connects AC network CAN, the collector of triode Q2 is connected with one end of resistance R 16 and is connected with the port of timing chip, and the other end of resistance R 16 is connected with power supply.
In the present embodiment, above-mentioned timing chip is single-chip microcomputer.Above-mentioned power supply is+5V power supply.
Principle of work of the present utility model is as follows: when the voltage of AC network CAN is high, AC network CAN is by R15, R14 dividing potential drop, and turn-on transistor Q2, drags down the voltage of timing chip input port.When the voltage of AC network CAN is low, by diode D2, R15, to ACN, triode Q2 ends, and timing chip input port voltage is drawn high.By detecting the change in voltage of timing chip input port, the mains frequency of alternating current just can be detected, reach the object of timing.The utility model, by the voltage of the collector of detection transistor, carrys out timing with the frequency that alternating current detected, and with a RESET input mouth being of little use, bring 2 input/output universal ports, and saved a Tao Zhen, and the degree of accuracy of the timing improving.
Claims (3)
1. a mains frequency timing circuit, it is characterized in that including triode Q2, resistance R 14 and R15, diode D2, wherein the base stage of triode Q2 is connected with one end of resistance R 14 and R15 and is connected with the negative electrode of diode D2, the plus earth of the other end ground connection of resistance R 14, the grounded emitter of triode Q2 and diode D2, the other end of resistance R 15 connects AC network CAN, the collector of triode Q2 is connected with one end of resistance R 16 and is connected with the port of timing chip, and the other end of resistance R 16 is connected with power supply.
2. mains frequency timing circuit according to claim 1, is characterized in that above-mentioned timing chip is single-chip microcomputer.
3. mains frequency timing circuit according to claim 1, is characterized in that above-mentioned power supply is+5V power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320880244.4U CN203616609U (en) | 2013-12-30 | 2013-12-30 | Grid frequency timing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320880244.4U CN203616609U (en) | 2013-12-30 | 2013-12-30 | Grid frequency timing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203616609U true CN203616609U (en) | 2014-05-28 |
Family
ID=50769240
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320880244.4U Expired - Lifetime CN203616609U (en) | 2013-12-30 | 2013-12-30 | Grid frequency timing circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203616609U (en) |
-
2013
- 2013-12-30 CN CN201320880244.4U patent/CN203616609U/en not_active Expired - Lifetime
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140528 |