CN203523017U - Earphone automatic adaption circuit - Google Patents
Earphone automatic adaption circuit Download PDFInfo
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- CN203523017U CN203523017U CN201320386425.1U CN201320386425U CN203523017U CN 203523017 U CN203523017 U CN 203523017U CN 201320386425 U CN201320386425 U CN 201320386425U CN 203523017 U CN203523017 U CN 203523017U
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Abstract
The utility model discloses an earphone automatic adaption circuit comprising a base-band chip and an earphone socket interface circuit. The earphone automatic adaption circuit is characterized by also comprising an MIC processing circuit in circuit connection with the base-band chip, and an on-off switching circuit which is connected between the earphone socket interface circuit and the MIC processing circuit and used for switching the connection state between the earphone socket interface circuit and the MIC processing circuit in dependence on instructions of the base-band chip. By employing the earphone automatic adaption circuit, the type of a connected earphone can be automatically detected, and the circuit can be automatically adjusted to a state that the circuit is matched with a plug of the earphone, mobile terminals provided with the earphone automatic adaption circuits are compatible and matched with earphone sockets of different standards in the market, and users can match the mobile terminals with earphones that they like discretionarily.
Description
Technical field
The utility model relates to electronic communication field, relates in particular to circuit and the adaptation method of the electronic equipments such as computer with earphone adaptable interface, mobile terminal, panel computer, player.
Background technology
General headset plug on market, as shown in Figure 1, comprises four terminals, and the order according to the end by described plug to root, is followed successively by the first terminal 111, the second terminal 112, the 3rd terminal 113 and the 4th terminal 114.General headset plug on market, its terminal is defined according to following two kinds of earphone interface standards:
The first earphone interface standard: the first terminal 111 is left channel audio signal reception terminal; The second terminal 112 is right channel audio signal reception terminal; The 3rd terminal 113 for audio signal output end be transmitter, MIC+; The 4th terminal 114 is earth terminal.
The second earphone interface standard: the first terminal 111 is left channel audio signal reception terminal; The second terminal 112 is right channel audio signal reception terminal; The 3rd terminal 113 is earth terminal; The 4th terminal 114 for audio signal output end be transmitter, MIC+.
Earphone socket of the prior art, as shown in Figure 1, is provided with five decks corresponding with headset plug, is respectively the first deck 121, the second deck 122, the 3rd deck 123, the 4th deck 124 and the 5th deck 125; When headset plug is inserted in earphone socket, the first terminal 111 is stuck in described the first deck 121 and with its circuit and is connected; The second terminal 112 is stuck in described the second deck 122 and with its circuit and is connected; The 3rd terminal 113 is stuck in described the 3rd deck 123 and with its circuit and is connected; The 4th terminal 114 is stuck in described the 4th deck 124 and realizes the circuit connection of the 4th terminal 114, the first deck 121 and the 4th deck 124.
A kind of electronic equipment of the prior art, the 3rd deck 123 of its earphone socket is connected with the audio signal input end mouth of baseband chip, its 4th deck 124 ground connection, this electronic equipment only can match with the headset plug that meets the first earphone interface standard; Another kind of electronic equipment of the prior art, the 3rd deck 123 ground connection of its earphone socket, its the 4th deck 124 is connected with the audio signal input end mouth of baseband chip, and this electronic equipment only can match with the headset plug that meets the second earphone interface standard.
Therefore in prior art, electronic equipment only matches with a kind of headset plug, the headset plug of another kind of earphone interface standard cannot mate with this electronic equipment use, the limitation that this has just caused earphone to use, consumer need to upgrade corresponding earphone when replacing new terminal equipment, causes the wasting of resources.
Utility model content
The purpose of this utility model is to provide a kind of earphone automatic adaptation circuit.
Earphone automatic adaptation circuit provided by the utility model, comprises baseband chip and earphone socket interface circuit; And the MIC treatment circuit being connected with described baseband chip circuitry phase and be connected to described earphone socket interface circuit and described MIC treatment circuit between for switch the switch switching circuit of the connection status of described earphone socket interface circuit and described MIC treatment circuit according to the instruction of baseband chip.
The utility model institute earphone automatic adaptation circuit, can automatically detect the kind of access earphone the state automatically the regulation of electrical circuit being matched as for this headset plug, can make to be provided with the earphone socket of the various criterion on the compatible adaptive market of mobile terminal of this circuit, the earphone that user can arrange in pairs or groups arbitrarily and oneself like.
Accompanying drawing explanation
Fig. 1 is the structural representation of the headset plug described in background technology and earphone socket;
The earphone automatic adaptation circuit module schematic diagram that Fig. 2 provides for the utility model embodiment mono-;
Fig. 3 is the port schematic diagram of the baseband chip described in Fig. 2;
Fig. 4 is the electrical block diagram of the MIC treatment circuit described in Fig. 2;
Fig. 5 is the electrical block diagram of the switch switching circuit described in Fig. 2;
Fig. 6 is the electrical block diagram of the earphone socket interface circuit described in Fig. 2.
Embodiment
For making object, technical scheme and the advantage of the utility model embodiment clearer, below in conjunction with the accompanying drawing in the utility model embodiment, technical scheme in the utility model embodiment is clearly and completely described, obviously, described embodiment is the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making the every other embodiment obtaining under creative work prerequisite, all belong to the scope of the utility model protection.
As shown in Figure 2, the present embodiment provides a kind of earphone automatic adaptation circuit, comprise the baseband chip 2100 that is provided with audio signal input end mouth and the earphone socket interface circuit 2400 that is provided with the 3rd deck 2403 and the 4th deck 2404, it is characterized in that: also comprise the MIC treatment circuit 2200 being connected with described baseband chip 2100 circuitry phases and be connected to described earphone socket interface circuit 2400 and described MIC treatment circuit 2200 between for switch the switch switching circuit 2300 of described earphone socket interface circuit 2400 and the connection status of described MIC treatment circuit 2200 according to the instruction of baseband chip 2100.It will be understood by those skilled in the art that when headset plug is inserted in earphone socket, the 3rd terminal 113 of headset plug is stuck in described the 3rd deck 2403 and with its circuit and is connected; The 4th terminal 114 of headset plug is stuck in described the 4th deck 2404 and with its circuit and is connected.Described earphone socket interface circuit 2400 comprises that with the connection status of described MIC treatment circuit 2200 the 3rd deck 2403 is connected with described MIC treatment circuit 2200 and the first state of the 4th deck 2404 ground connection; And the 3rd the second state of being connected with described MIC treatment circuit 2200 of deck 2403 ground connection and the 4th deck 2404.Described switch switching circuit 2300 is switched between described the first state and the second state according to the earphone automatic adaptation circuit described in instruction control the present embodiment of baseband chip 2100, when the earphone automatic adaptation circuit described in the present embodiment switches to the first state, can match with the earphone socket of the first earphone interface standard described in background technology; When switching to the second state, the earphone automatic adaptation circuit described in the present embodiment can match with the earphone socket of the second earphone interface standard described in background technology.Like this, the electronic equipment that has configured the earphone automatic adaptation circuit described in the present embodiment is compatible adaptive above-mentioned two kinds of earphone sockets automatically, the earphone that user can arrange in pairs or groups arbitrarily and oneself like.
As shown in Figure 5, described switch switching circuit 2300 comprises the first simulation single-pole double-throw switch (SPDT) U1 and the second simulation single-pole double-throw switch (SPDT) U2; Described the first simulation single-pole double-throw switch (SPDT) U1 is equipped with the first high level triggering and conducting port B11, the first low level triggering and conducting port B01, the second deck connectivity port A2 and the first control port S1; Described the second simulation single-pole double-throw switch (SPDT) U2 is equipped with the second high level triggering and conducting port B12, the second low level triggering and conducting port B02, the second deck connectivity port A2 and the second control port S2; Described the first high level triggering and conducting port B11 is all connected with described MIC treatment circuit 2200 with described the second low level triggering and conducting port B02; Described the second deck connectivity port A2 connects the 4th deck 2404; Described the second deck connectivity port A2 connects the 3rd deck 2403; Described the first control port S1 and described the second control port S2 are all connected with described baseband chip 2100; Described the first low level triggering and conducting port B01 and the equal ground connection of the second high level triggering and conducting port B12.It will be appreciated by those skilled in the art that, described the first simulation single-pole double-throw switch (SPDT) U1 receives by described the first control port (S1) control signal that described baseband chip 2100 is sent, and according to described the second deck connectivity port A2 and described the first high level triggering and conducting port B11 is conducted or and described the first low level triggering and conducting port B01 be conducted the two one of between switching; Described the second simulation single-pole double-throw switch (SPDT) U2 receives by described the second control port (S2) control signal that described baseband chip 2100 is sent, and according to described the second deck connectivity port A2 and described the second high level triggering and conducting port B12 is conducted or and described the second low level triggering and conducting port B02 be conducted the two one of between switch, realize with the headset plug of current access and matching.As when as described in the first simulation single-pole double-throw switch (SPDT) U1 in as described in the second deck connectivity port A2 and as described in the state that is conducted of the first high level triggering and conducting port B11, simultaneously, described the second simulation single-pole double-throw switch (SPDT) U2 is when state that described the second deck connectivity port A2 and described the second high level triggering and conducting port B12 are conducted, described the 4th deck 2404 is connected with described MIC treatment circuit 2200, described the 3rd deck 2403 ground connection, now described earphone socket meets the second earphone interface standard; Contrary, the state being conducted in described the second deck connectivity port A2 and described the first low level triggering and conducting port B01 as described the first simulation single-pole double-throw switch (SPDT) U1, simultaneously, described the second simulation single-pole double-throw switch (SPDT) U2 is when state that described the second deck connectivity port A2 and described the second low level triggering and conducting port B02 are conducted, described the 3rd deck 2403 ground connection and described the 4th deck 2404 are connected with described MIC treatment circuit 2200, and now described earphone socket meets the first earphone interface standard.
As shown in Figure 5, described switch switching circuit 2300 also comprises the first inductance B1; Described first inductance B1 one end ground connection and the other end are connected with described the first low level triggering and conducting port B01 and the second high level triggering and conducting port B12 respectively.It will be understood by those skilled in the art that described the first inductance B1 can effectively suppress High-frequency Interference, guarantee the audio quality of electronic equipment, and promote the antistatic effect of described switch switching circuit 2300.
Preferably, the first inductance B1 is a magnetic bead, can better suppress High-frequency Interference, guarantees audio quality.
As shown in Figure 5, described the first simulation single-pole double-throw switch (SPDT) U1 and described the second simulation single-pole double-throw switch (SPDT) U2 all also comprise the power port VCC that connects battery, for accessing the power supply of the operating voltage that meets described switch switching circuit 2300.
Concrete, as shown in Fig. 3 and Fig. 5, described baseband chip 2100 is provided with the first control signal output port ENABLE1 of being connected with described the first control port S1 and is connected with described the second control port S2.It will be understood by those skilled in the art that described the first control port S1 receives the control signal that baseband chip 2100 sends by the first control signal output port ENABLE1 and switches its state; In like manner, the control signal that described the second control port (S2) reception baseband chip 2100 sends by the second control signal output port ENABLE2 is switched its state.
As shown in Figure 4, described MIC treatment circuit 2200 comprises identification module 2210, filtration module 2220 and every straight module 2230; Described identification module 2210 is connected with one end of described the first high level triggering and conducting port B11 and described the second low level triggering and conducting port B02, described baseband chip 2100 and described filtration module 2220 respectively; Described be connected with the other end of described filtration module 2220 every straight module 2230 one end and the other end is connected with described baseband chip 2100.
Concrete, as shown in Figures 3 and 4, described baseband chip 2100 is provided with the first audio signal input end mouth MICN1, the second audio signal input end mouth MICP1, identification signal input port ADC_DET and bias voltage input port EARBIAS; Described identification module 2210 is connected with baseband chip 2100 by described bias voltage input port EARBIAS and described identification signal input port ADC_DET respectively; Describedly every straight module 2230, by described the first audio signal input end mouth MICN1, be connected with described baseband chip 2100 with the second audio signal input end mouth MICP1 respectively.The size of the level signal that described baseband chip 2100 receives according to identification signal input port produces control signal, by described the first control signal output port ENABLE1 and the second control signal output port ENABLE2, control signal is sent to respectively to the first simulation single-pole double-throw switch (SPDT) U1 and the second simulation single-pole double-throw switch (SPDT) U2 again, the control signal that the first simulation single-pole double-throw switch (SPDT) U1 and the second simulation single-pole double-throw switch (SPDT) U2 receive according to it is carried out the state of switch conducting, thereby realize, automatically matches from the headset plug of different earphone interface standards.
Further, as shown in Figure 4, described identification module 2210 comprises the first capacitor C 1, the second capacitor C 2, the first resistance R 1, the second resistance R 2, the 3rd resistance R 3 and the second inductance B2; Described bias voltage input port EARBIAS, the first resistance R 1, the second resistance (R2), the 3rd resistance (R3) and described identification signal input port ADC_DET connect successively; Described first capacitor C 1 one end connects described bias voltage input port EARBIAS and other end ground connection; Described second capacitor C 2 one end are connected between described the first resistance R 1 and other end ground connection; Described second inductance B2 one end is connected between described the second resistance R 2 and the 3rd resistance R 3 and the other end is connected respectively with described the first high level triggering and conducting port B11 and described the second low level triggering and conducting port B02 respectively.The operation principle of this identification module 2210 that the present embodiment provides is as follows: electronic equipment has accessed after earphone, after each terminal of headset plug is connected with each deck difference circuit of earphone socket, and the working impedance R of earphone
mICcan to the output signal of described bias voltage input port EARBIAS, carry out dividing potential drop in the mode of connecting with the first resistance R 1, the second resistance R 2, like this, the magnitude of voltage V of described identification signal input port ADC_DET signal
aDC_DETfor V
eARBIAS* R
mIC/ R1+R2+R
mIC.Further, described the second inductance B2 is a magnetic bead, and described magnetic bead B2 can play better inhibition High-frequency Interference, guarantees the quality of audio frequency input.
Further, as shown in Figure 4, describedly every straight module 2230, comprise the 3rd capacitor C 3 and the 4th capacitor C 4; Described the first audio signal input end mouth MICN1 and the other end that described the 3rd capacitor C 3 one end connect baseband chip 2100 connect described filtration module 2220; Described the second audio signal input end mouth MICP1 and the other end that described the 4th capacitor C 4 one end connect baseband chip 2100 connect described filtration module 2220.It will be appreciated by those skilled in the art that, described the 3rd capacitor C 3 and the 4th capacitor C 4 are for isolating the direct voltage of audio signal, for guaranteeing that the first audio signal input end mouth MICN1 of baseband chip and the second audio signal input end mouth MICP1 input without direct current signal, guarantee the normal work of the first audio signal input end mouth MICN1 and the second audio signal input end mouth MICP1.
A nearlyer step, as shown in Figure 4, described filtration module 2220 comprises the 5th capacitor C 5, the 6th capacitor C 6 and the 7th electric capacity (C7); Described the 5th electric capacity two ends are connected with the 4th capacitor C 4 with described the 3rd capacitor C 3 respectively; Described the 6th capacitor C 6 one end connect described the 4th capacitor C 4 and other end ground connection; Described the 7th capacitor C 7 one end connect described the 3rd capacitor C 3 and other end ground connection.It will be appreciated by those skilled in the art that, described the 5th capacitor C 5 can filtering the first audio signal input end mouth MICN1 and the second audio signal input end mouth MICP1 between common mode disturbances, described the 6th capacitor C 6 and the 7th capacitor C 7 can be distinguished the differential mode interference of filtering the first audio signal input end mouth MICP1 and the second audio signal input end mouth MICN1, to guarantee the quality of two-way audio input signal.As shown in Figure 3, described baseband chip 2100 is also provided with interrupt signal input port EINT_HP, interrupt signal power port VDD18.As shown in Figure 6, the earphone automatic adaptation circuit that the present embodiment provides, also comprises the 6th resistance R 6, the 7th resistance R 7 and the 3rd inductance B3; Described earphone socket also comprises the 5th deck 2405.Described interrupt signal input port EINT_HP, described the 6th resistance R 6, described the 3rd inductance B3 and described the 5th deck 2405 successively circuit connect; Described the 7th resistance R 7 one end connect described interrupt signal power port VDD18 and the other end is connected between described the 6th resistance R 6 and described the 3rd inductance B3.
It will be appreciated by those skilled in the art that, when headset plug is not during plugged earphone socket, together with the described interrupt signal power port VDD18 of described the 5th deck 2405 and baseband chip 2100, to described interrupt signal input port EINT_HP, provide high level signal, now baseband chip 2100 is controlled described the first control signal output port ENABLE1 output low level control signals and described the second control signal output port ENABLE2 output high-level control signal.When described the first simulation single-pole double-throw switch (SPDT) U1 receives described low level control signal by its first control port S1, described the first simulation single-pole double-throw switch (SPDT) U1 switches to the state that described the second deck connectivity port A2 and described the first low level triggering and conducting port B01 are conducted, now described the 4th deck 2404 is by ground connection after described the first inductance B1, simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 receives described high-level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switches to the state that the second deck connectivity port A2 and described the second high level triggering and conducting port B12 are conducted described in it, now described the 3rd deck 2403 is by ground connection after described the first inductance B1, so the standby IDLE state of described earphone socket in described the 3rd deck 2403 and the 4th deck 2404 equal ground connection.
It will be appreciated by those skilled in the art that, when headset plug plugged earphone socket, the 5th deck 2405 and the first deck 2401 are conducted, the 5th deck 2405 is connected with the first port 111 of headset plug, and described the first port D.C. resistance is over the ground negligible 32 ohm, therefore now the 5th deck 2405 is equivalent to ground connection; Thus, now the 5th deck 2405 provides ground signalling to described interrupt signal input port EINT_HP together with described the 7th resistance R 7, now baseband chip 2100 triggers low level interruption, and baseband chip 2100 detects the magnitude of voltage V of described identification signal input port ADC_DET signal
aDC_DET.
Magnitude of voltage V when described identification signal input port ADC_DET signal
aDC_DETwhile being greater than or equal to 0.9V, described baseband chip 2100 is controlled described the first control signal output port ENABLE1 and the equal output low level signal of the second control signal output port ENABLE2.Now described the first simulation single-pole double-throw switch (SPDT) U1 receives described low level control signal by its first control port S1, described the first simulation single-pole double-throw switch (SPDT) U1 switches to the state that described the second deck connectivity port A2 and described the first low level triggering and conducting port B01 are conducted, and now described the 4th deck 2404 passes through ground connection after described the first inductance B1; Simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 receives described low level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switches to the state that the second deck connectivity port A2 and described the second low level triggering and conducting port B02 are conducted described in it, now described the 3rd deck 2403 is conducted with described MIC treatment circuit 2200, therefore, earphone socket now meets the first earphone interface standard.
Magnitude of voltage V when described identification signal input port ADC_DET signal
aDC_DETwhile being less than 0.9V, described baseband chip 2100 controls described the first control signal output port ENABLE1 and the second control signal output port ENABLE2 all exports high level signal.Now described the first simulation single-pole double-throw switch (SPDT) U1 receives described high-level control signal by its first control port S1, described the first simulation single-pole double-throw switch (SPDT) U1 switches to the state that described the second deck connectivity port A2 and described the first high level triggering and conducting port B11 are conducted, and now described the 4th deck 2404 and described MIC treatment circuit 2200 are conducted; Simultaneously, when described the second simulation single-pole double-throw switch (SPDT) U2 receives described high-level control signal by its second control port S2, described the second single-pole double-throw switch (SPDT) switches to the state that the second deck connectivity port A2 and described the second high level triggering and conducting port B12 are conducted described in it, now described the 3rd deck 2403 is by ground connection after described the first inductance B1, therefore, earphone socket now meets the first earphone interface standard.
Further, as shown in Figure 3, described baseband chip 2100 is also provided with left channel audio signal output port (LEFT_AUDIO) and right channel audio signal output port (RIGHT_AUDIO); As shown in Figure 6, earphone socket is also provided with the first deck 2401 and the second deck 2402; Described the first deck 2401 access described left channel audio signal output ports (LEFT_AUDIO); Described the second deck 2402 access described right channel audio signal output ports (RIGHT_AUDIO).It will be appreciated by those skilled in the art that, in the time of in headset plug is inserted into earphone socket, the first terminal 111 of headset plug is connected with described the first deck 2401 circuit, the second terminal 112 of headset plug is connected with described the second deck 2402 circuit, baseband chip 2100 by described left channel audio signal output port (LEFT_AUDIO) and described right channel audio signal output port (RIGHT_AUDIO) to earphone output audio signal.
It should be noted that; the first simulation single-pole double-throw switch (SPDT) U1 that described switch switching circuit 2300 is included and the second simulation single-pole double-throw switch (SPDT) U2 are single channel simulation single-pole double-throw switch (SPDT); also can be equal to and substitute this two functions that single channel simulation single-pole double-throw switch (SPDT) is realized with a two-way simulation single-pole double-throw switch (SPDT), this implementation method also should belong to protection range of the present utility model.
Finally it should be noted that: above embodiment only, in order to the technical solution of the utility model to be described, is not intended to limit; Although the utility model is had been described in detail with reference to previous embodiment, those of ordinary skill in the art is to be understood that: its technical scheme that still can record aforementioned each embodiment is modified, or part technical characterictic is wherein equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution depart from the spirit and scope of each embodiment technical scheme of the utility model.
Claims (10)
1. an earphone automatic adaptation circuit, comprise baseband chip (2100) and earphone socket interface circuit (2400), it is characterized in that: also comprise the MIC treatment circuit (2200) being connected with described baseband chip (2100) circuitry phase and be connected to described earphone socket interface circuit (2400) and described MIC treatment circuit (2200) between for switch the switch switching circuit (2300) of the connection status of described earphone socket interface circuit (2400) and described MIC treatment circuit (2200) according to the instruction of baseband chip (2100).
2. earphone automatic adaptation circuit as claimed in claim 1, is characterized in that: described switch switching circuit (2300) comprises the first simulation single-pole double-throw switch (SPDT) (U1) and the second simulation single-pole double-throw switch (SPDT) (U2); Described the first simulation single-pole double-throw switch (SPDT) (U1) is equipped with the first high level triggering and conducting port (B11), the first low level triggering and conducting port (B01), the second deck (2402) connectivity port (A1) and the first control port (S1); Described the second simulation single-pole double-throw switch (SPDT) (U2) is equipped with the second high level triggering and conducting port (B12), the second low level triggering and conducting port (B02), the second deck connectivity port (A2) and the second control port (S2); Described the first high level triggering and conducting port (B11) is all connected with described MIC treatment circuit (2200) with described the second low level triggering and conducting port (B02); Described the second deck (2402) connectivity port (A1) connects the 4th deck (2404); Described the second deck connectivity port (A2) connects the 3rd deck (2403); Described the first control port (S1) and described the second control port (S2) are all connected with described baseband chip (2100); Described the first low level triggering and conducting port (B01) and the second high level triggering and conducting port (B12) be ground connection all.
3. earphone automatic adaptation circuit as claimed in claim 2, is characterized in that: also comprise the first inductance (B1); Described the first inductance (B1) one end ground connection and the other end are connected with described the first low level triggering and conducting port (B01) and the second high level triggering and conducting port (B12) respectively.
4. earphone automatic adaptation circuit as claimed in claim 2, is characterized in that: described MIC treatment circuit (2200) comprises identification module (2210), filtration module (2220) and every straight module (2230); Described identification module (2210) is connected with one end of described the first high level triggering and conducting port (B11) and described the second low level triggering and conducting port (B02), described baseband chip (2100) and described filtration module (2220) respectively; Described be connected with the other end of described filtration module (2220) every straight module (2230) one end and the other end is connected with described baseband chip (2100).
5. earphone automatic adaptation circuit as claimed in claim 4, is characterized in that: described baseband chip (2100) is provided with the first audio signal input end mouth (MICN1), the second audio signal input end mouth (MICP1), identification signal input port (ADC_DET) and bias voltage input port (EARBIAS); Described identification module (2210) is connected with baseband chip (2100) by described bias voltage input port (EARBIAS) and described identification signal input port (ADC_DET) respectively; Describedly every straight module (2230), by described the first audio signal input end mouth (MICN1), be connected with described baseband chip (2100) with the second audio signal input end mouth (MICP1) respectively.
6. earphone automatic adaptation circuit as claimed in claim 5, is characterized in that: described identification module (2210) comprises the first electric capacity (C1), the second electric capacity (C2), the first resistance (R1), the second resistance (R2), the 3rd resistance (R3) and the second inductance (B2); Described bias voltage input port (EARBIAS), the first resistance (R1), the second resistance (R2), the 3rd resistance (R3) and described identification signal input port (ADC_DET) are connected successively; Described the first electric capacity (C1) one end connects described bias voltage input port (EARBIAS) and other end ground connection; Described the second electric capacity (C2) one end is connected between described the first resistance (R1) and other end ground connection; Described the second inductance (B2) one end is connected between described the second resistance (R2) and the 3rd resistance (R3) and the other end is connected respectively with described the first high level triggering and conducting port (B11) and described the second low level triggering and conducting port (B02) respectively.
7. earphone automatic adaptation circuit as claimed in claim 4, is characterized in that: describedly every straight module (2230), comprise the 3rd electric capacity (C3) and the 4th electric capacity (C4); Described baseband chip (2100) is provided with the first audio signal input end mouth (MICN1) and the second audio signal input end mouth (MICP1); Described the 3rd electric capacity (C3) one end connects described the first audio signal input end mouth (MICN1) and the other end connects described filtration module (2220); Described the 4th electric capacity (C4) one end connects described the second audio signal input end mouth (MICP1) and the other end connects described filtration module (2220).
8. earphone automatic adaptation circuit as claimed in claim 4, is characterized in that: described filtration module (2220) comprises the 5th electric capacity (C5), the 6th electric capacity (C6) and the 7th electric capacity (C7); Describedly every straight module (2230), comprise the 3rd electric capacity (C3) and the 4th electric capacity (C4); Described the 5th electric capacity two ends are connected with the 4th electric capacity (C4) with described the 3rd electric capacity (C3) respectively; Described the 6th electric capacity (C6) one end connects described the 4th electric capacity (C4) and other end ground connection; Described the 7th electric capacity (C7) one end connects described the 3rd electric capacity (C3) and other end ground connection.
9. earphone automatic adaptation circuit as claimed in claim 2, is characterized in that: described baseband chip (2100) is provided with the first control signal output port (ENABLE1) being connected with described the first control port (S1) and the second control signal output port (ENABLE2) being connected with described the second control port (S2).
10. earphone automatic adaptation circuit as claimed in claim 2, is characterized in that: described baseband chip (2100) is also provided with interrupt signal input port (EINT_HP), interrupt signal power port (VDD18); Described earphone socket interface circuit (2400) also comprises the 6th resistance (R6), the 7th resistance (R7) and the 3rd inductance (B3) and the 5th deck (2405); Described interrupt signal input port (EINT_HP), described the 6th resistance (R6), described the 3rd inductance (B3) and described the 5th deck (2405) successively circuit connect; Described the 7th resistance (R7) one end connects described interrupt signal power port (VDD18) and the other end is connected between described the 6th resistance (R6) and described the 3rd inductance (B3).
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320386425.1U CN203523017U (en) | 2013-07-01 | 2013-07-01 | Earphone automatic adaption circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320386425.1U CN203523017U (en) | 2013-07-01 | 2013-07-01 | Earphone automatic adaption circuit |
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| CN203523017U true CN203523017U (en) | 2014-04-02 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103391495A (en) * | 2013-07-01 | 2013-11-13 | 上海摩软通讯技术有限公司 | Automatic earphone adaptation circuit and adaptation method thereof |
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2013
- 2013-07-01 CN CN201320386425.1U patent/CN203523017U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103391495A (en) * | 2013-07-01 | 2013-11-13 | 上海摩软通讯技术有限公司 | Automatic earphone adaptation circuit and adaptation method thereof |
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