CN203502711U - Array substrate and display device - Google Patents
Array substrate and display device Download PDFInfo
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- CN203502711U CN203502711U CN201320642105.8U CN201320642105U CN203502711U CN 203502711 U CN203502711 U CN 203502711U CN 201320642105 U CN201320642105 U CN 201320642105U CN 203502711 U CN203502711 U CN 203502711U
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- electrode
- pixel electrode
- public electrode
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- array base
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- 239000000758 substrate Substances 0.000 title claims abstract description 31
- 238000009413 insulation Methods 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 230000001681 protective effect Effects 0.000 claims description 39
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 10
- 230000000694 effects Effects 0.000 abstract description 7
- 239000013078 crystal Substances 0.000 abstract 2
- 239000007788 liquid Substances 0.000 abstract 2
- 238000000034 method Methods 0.000 description 41
- 238000004519 manufacturing process Methods 0.000 description 10
- 230000015572 biosynthetic process Effects 0.000 description 9
- 238000005530 etching Methods 0.000 description 8
- 238000000576 coating method Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 230000005684 electric field Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005265 energy consumption Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 210000004276 hyalin Anatomy 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
Images
Landscapes
- Liquid Crystal (AREA)
- Thin Film Transistor (AREA)
Abstract
The embodiment of the utility model discloses an array substrate and a display device comprising the array substrate, and belongs to the technical field of display. The technical problems that an existing ADSDS type liquid crystal displayer is small in storage capacitance, an image can not be conveniently maintained, and the display effect is poor are solved. The array substrate comprises a grid metal layer, a grid insulation layer, an active layer, a source-drain metal layer, a protection layer, a pixel electrode and a common electrode. The grid metal layer, the grid insulation layer, the active layer, the source-drain metal layer and the protection layer are formed on a liner substrate from bottom to top. The pixel electrode and the common electrode are arranged on the protection layer. The protection layer is provided with a hole, and the pixel electrode is connected with the drain electrode of the source-drain metal layer through the hole. The projections of the drain electrode and the common electrode on the liner substrate are at least partially overlapped. The array substrate can be applied to a crystal liquid panel, a crystal liquid TV set, a liquid crystal displayer, a digital photo frame, a mobile phone, a tablet computer and other display devices.
Description
Technical field
The utility model belongs to display technique field, is specifically related to a kind of array base palte and display device.
Background technology
Development along with display technique, Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) owing to thering is the advantages such as volume is little, low in energy consumption, radiationless, in flat pannel display field, occupied leading position.Wherein, senior super Wei Chang conversion (Advanced super Dimension Switch, ADSDS) type TFT-LCD adopts horizontal component of electric field to drive liquid crystal, has the advantages such as wide visual angle, high aperture, high permeability be widely used because of it.
At present, on the array base palte of ADSDS type liquid crystal display, be all to form public electrode wire in gate metal layer, and public electrode wire and pixel electrode overlapping in the projection section of substrate, this lap can form memory capacitance, to keep the voltage difference between pixel electrode and public electrode.
The inventor finds in realizing process of the present invention; at least there is following problem in prior art: between existing public electrode wire and pixel electrode, is separated with gate insulation layer and protective seam; therefore the spacing between public electrode wire and pixel electrode is larger; formed memory capacitance is less; be unfavorable for the maintenance of picture, cause the poor technical matters of display effect.
Utility model content
The utility model embodiment provides a kind of array base palte and has been provided with the display device of this array base palte, and the memory capacitance that has solved existing ADSDS type liquid crystal display is less, is unfavorable for the maintenance of picture, causes the poor technical matters of display effect.
For achieving the above object, embodiment of the present utility model adopts following technical scheme:
The utility model provides a kind of array base palte, comprises underlay substrate and is formed at successively gate metal layer, gate insulation layer, active layer, source leakage metal level, the protective seam on underlay substrate, and be positioned at pixel electrode and the public electrode on described protective seam;
On described protective seam, offer via hole, described pixel electrode is connected with the drain electrode that is positioned at described source leakage metal level by described via hole;
Described drain electrode and described public electrode underlay substrate to be projected to small part overlapping.
Preferably, described pixel electrode and described public electrode arrange with layer.
Preferably, described pixel electrode and described public electrode are all slit-shaped.
In another embodiment, described public electrode is formed on described protective seam, and described public electrode top is formed with insulation course, and described pixel electrode is formed on described insulation course;
Described via hole runs through described protective seam and described insulation course, and described pixel electrode is connected with described drain electrode by described via hole.
Preferably, described public electrode is tabular, and described pixel electrode is slit-shaped.。
In another embodiment, described pixel electrode is formed on described protective seam, and described pixel electrode top is formed with insulation course, and described public electrode is formed on described insulation course;
Described via hole runs through described protective seam, and described pixel electrode is connected with described drain electrode by described via hole.Further, this array base palte also comprises the public electrode wire being connected with described public electrode, and described public electrode wire is positioned at described gate metal layer, and described public electrode wire and described pixel electrode underlay substrate to be projected to small part overlapping.
The utility model also provides a kind of display device, comprises above-mentioned array base palte.
Compared with prior art; technique scheme tool provided by the utility model has the following advantages: utilize public electrode and drain electrode between lap as memory capacitance; because be only separated with protective seam between public electrode and drain electrode; so than prior art; spacing between public electrode and drain electrode is less; formed memory capacitance is also just larger, thereby can keep better picture, has improved display effect.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, below the accompanying drawing of required use during embodiment is described is briefly described.
The schematic diagram of the array base palte that Fig. 1 a provides for embodiment 1 of the present utility model;
Fig. 1 b is that Fig. 1 a is along the cut-open view of A-A line;
The schematic diagram one of the manufacture process of the array base palte that Fig. 2 a provides for embodiment 1 of the present utility model;
Fig. 2 b is that Fig. 2 a is along the cut-open view of A-A line;
The schematic diagram two of the manufacture process of the array base palte that Fig. 3 a provides for embodiment 1 of the present utility model;
Fig. 3 b is that Fig. 3 a is along the cut-open view of A-A line;
The schematic diagram three of the manufacture process of the array base palte that Fig. 4 a provides for embodiment 1 of the present utility model;
Fig. 4 b is that Fig. 4 a is along the cut-open view of A-A line;
The schematic diagram four of the manufacture process of the array base palte that Fig. 5 a provides for embodiment 1 of the present utility model;
Fig. 5 b is that Fig. 5 a is along the cut-open view of A-A line;
The schematic diagram five of the manufacture process of the array base palte that Fig. 6 a provides for embodiment 1 of the present utility model;
Fig. 6 b is that Fig. 6 a is along the cut-open view of A-A line.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, the technical scheme in the utility model embodiment is carried out to clear, complete description.
Embodiment 1:
As shown in Fig. 1 a and Fig. 1 b; the array base palte that the utility model embodiment provides; comprise the gate metal layer 1, gate insulation layer 10, active layer 2, source leakage metal level 3, the protective seam 60 that are formed at successively from bottom to up on underlay substrate 100; and be positioned at pixel electrode 4 on protective seam 60 and public electrode 5(because underlay substrate is generally transparency carrier; gate insulation layer and protective seam only form the hyaline layer of via structure for substantially all covering underlay substrates in subregion; for illustrating conveniently, not shown underlay substrate, gate insulation layer and protective seam in Fig. 1 a).
Wherein, offer via hole 6 on protective seam 60, the drain electrode 31 that pixel electrode 4 leaks in metal level 3 with source by via hole 6 is connected.Drain electrode 31 and public electrode 5 underlay substrate to be projected to small part overlapping, as the dotted line frame part in Fig. 1 a and Fig. 1 b.
In the array base palte that the utility model embodiment provides; utilize the lap between public electrode 5 and drain electrode 31 to form memory capacitance; because be only separated with protective seam between public electrode 5 and drain electrode 31; so than prior art; spacing between public electrode 5 and drain electrode 31 is less; formed memory capacitance is also just larger, thereby can keep better picture, has improved display effect.
In addition, known according to the computing formula of electric capacity, the size of electric capacity is directly proportional to the overlapping area between electric capacity two-plate, and the spacing between electric capacity two-plate is inversely proportional to.The utility model embodiment is the size that spacing between public electrode 5 and drain electrode 31 increases memory capacitance by reducing to form the two-plate of memory capacitance, therefore can also guarantee that memory capacitance is enough under large prerequisite, 31 the area that suitably reduces to drain, thus the aperture opening ratio of liquid crystal display improved.And in the utility model embodiment, also saved public electrode wire of the prior art, further improved the aperture opening ratio of liquid crystal display.
As a preferred version, in the utility model embodiment, pixel electrode 4 and public electrode arrange with layer 5.Can in a composition technique, form pixel electrode 4 and public electrode 5 so simultaneously, to simplify the manufacture process of array base palte, also reduce the thickness of array base palte simultaneously.
Further, pixel electrode 4 and public electrode 5 are all slit-shaped.Pixel electrode 4 and public electrode 5 can be staggered like this, be more convenient for pixel electrode 4 and public electrode 5 and carry out arranging with layer, also can make to form even, stable horizontal component of electric field between pixel electrode 4 and public electrode 5.
The utility model embodiment also provides the manufacture method of this array base palte, comprising:
S1: form successively the figure of gate metal layer, gate insulation layer, active layer, source leakage metal level, protective seam on underlay substrate, wherein, offer via hole on protective seam.
Specifically comprise:
S11: as shown in Figure 2 a and 2 b, comprise the figure of the gate metal layer 1 of grid and grid line by composition technique formation for the first time on underlay substrate.
S12: as shown in Figure 3 a and Figure 3 b shows, complete on the basis of above-mentioned steps, by the figure of the gate insulation layer 10 of composition technique formation for the second time, wherein gate insulation layer 10 forms via hole at non-display area, for driving signal to transfer to grid line grid, so the via hole on not shown gate insulation layer 10 in Fig. 3 a and Fig. 3 b.
S13: as shown in Figure 3 a and Figure 3 b shows, complete on the basis of above-mentioned steps, comprise the figure of active layer 2 by composition technique formation for the third time, wherein, the figure of active layer 2 is positioned at the top of grid.
S14: as shown in Fig. 4 a and Fig. 4 b, complete on the basis of above-mentioned steps, the figure by the 4th composition technique formation source leakage metal level, specifically comprises data line, source electrode 32, drain electrode 31.
S15: as shown in Fig. 5 a and Fig. 5 b, complete on the basis of above-mentioned steps, form the figure of protective seam by the 5th composition technique, and be formed with via hole 6 on protective seam.
Above-mentioned steps S11 to S15 all can form by composition techniques such as conventional exposure, development, etchings, can certainly wait by printing other composition technique, is no longer elaborated herein.
S2: on protective seam, form the figure comprise pixel electrode and public electrode, wherein, pixel electrode is connected with the drain electrode that is arranged in source and leaks metal level by via hole, drain electrode and public electrode underlay substrate to be projected to small part overlapping.
Concrete:
S21: as shown in Fig. 6 a and Fig. 6 b, complete on the basis of above-mentioned steps, utilize the coating process such as deposition or sputter to form layer of transparent electrode 40, this transparency electrode 40 is preferably indium tin oxide (Indium Tin Oxides, ITO).
S22: by the 6th composition technique, transparency electrode 40 is carried out to composition, through processes such as exposure, development, etchings, form and to comprise and being positioned at the pixel electrode 4 of layer and the figure of public electrode 5, as shown in Figure 1.Pixel electrode 4 is connected with the drain electrode 31 that is positioned at source and leaks metal level 3 by via hole 6, drain electrode 31 and public electrode 5 underlay substrate to be projected to small part overlapping.Preferably, pixel electrode 4 and public electrode 5 are all slit-shaped.
After completing above-mentioned steps, can form the array base palte that the utility model embodiment provides.
Embodiment 2:
The present embodiment is substantially the same manner as Example 1, and its difference is, the pixel electrode in the present embodiment and public electrode are positioned at different transparency conducting layers, and are separated with insulation course between pixel electrode and public electrode.
As a preferred version; public electrode is formed on protective seam; public electrode top is formed with insulation course; pixel electrode is formed on insulation course; wherein public electrode can for tabular can be also slit-shaped; pixel electrode is slit-shaped, and object is that public electrode and pixel electrode can form stable multi-dimensional electric field.Via hole runs through protective seam and insulation course, and pixel electrode is connected with drain electrode by via hole.Like this, between public electrode and drain electrode, be still only separated with protective seam, so formed capacitance size is suitable in the electric capacity forming between public electrode and drain electrode and embodiment 1.
In the manufacture method of the array base palte that the present embodiment provides, the step S1 in step S1 and embodiment 1 is basic identical, no longer describes in detail herein.
Step S2 in the present embodiment: on protective seam; formation comprises the figure of pixel electrode and public electrode, and wherein, pixel electrode is connected with the drain electrode that is positioned at source leakage metal level by via hole; drain electrode and public electrode underlay substrate to be projected to small part overlapping, be specially:
S201: on the basis of completing steps S1, utilize the coating process such as deposition or sputter to form ground floor transparency electrode on protective seam.
S202: by composition technique, this ground floor transparency electrode is carried out to composition, through processes such as exposure, development, etchings, form the figure that comprises public electrode.
S203: utilize the coating process such as deposition or sputter to form one deck insulation film on public electrode.
S204: by composition technique, insulation film is carried out to composition, form the insulation course figure that offers via hole.
Because the via hole in the present embodiment has run through insulation course and protective seam, thus can be in this composition technique etching insulation course and protective seam continuously, form the insulation course figure and the protective seam figure that offer via hole.In addition, if on protective seam except via hole, do not need other figures of etching, can omit the composition technique of step S15, step 202 is the 5th composition technique, step 204 is the 6th composition technique, step 206 is below the 7th composition technique.
S205: utilize the coating process such as deposition or sputter to form second layer transparency electrode on insulation course.
S206: by composition technique, this second layer transparency electrode is carried out to composition, through processes such as exposure, development, etchings, form the figure that comprises pixel electrode.
After completing above-mentioned steps, can form the array base palte that the utility model embodiment provides.
Embodiment 3:
The difference of the present embodiment and embodiment 1 and embodiment 2 is; in the array base palte of the present embodiment, pixel electrode is positioned on protective seam; pixel electrode top forms insulation course; public electrode is formed on insulation course; pixel electrode can be tabular or slit-shaped; public electrode is slit-shaped; owing to comprising protective seam and insulation course is two-layer between public electrode and drain electrode; the memory capacitance forming between it is compared aforementioned preferred version and is reduced to some extent, but still has compared to existing technology the effect that increases memory capacitance and improve aperture opening ratio.
The array substrate manufacturing method of the present embodiment is similar to Example 2, and something in common repeats no more, and difference is, described formation comprises the figure of pixel electrode and public electrode, is specially:
Utilize the coating process such as deposition or sputter on described protective seam, to form ground floor transparency electrode;
By comprising the composition technique of the processes such as exposure, development, etching, described ground floor transparency electrode is carried out to composition, form the figure that comprises pixel electrode;
Utilize the coating process such as deposition or sputter on described pixel electrode, to form one deck insulation film;
Utilize the coating process such as deposition or sputter on described insulation course, to form second layer transparency electrode;
By comprising the composition technique of the processes such as exposure, development, etching, described second layer transparency electrode is carried out to composition, form the figure that comprises public electrode.
Embodiment 4:
On the basis of above-described embodiment 1～3, further, described array base palte can also be provided with the public electrode wire being connected with public electrode, this public electrode wire is positioned at gate metal layer, form with a composition technique with grid and grid line, and public electrode wire and pixel electrode underlay substrate to be projected to small part overlapping.Be equivalent to the technical scheme of above-described embodiment to combine with prior art, make to form the first memory capacitance between public electrode and drain electrode, between public electrode wire and pixel electrode, form the second memory capacitance simultaneously, further improve the size of memory capacitance.
Manufacture method and above-described embodiment of the array base palte that the present embodiment provides are basic identical, and its difference is only step S11: on underlay substrate, by composition technique formation for the first time, comprise the figure of the gate metal layer of grid and grid line, be specially:
On underlay substrate, by composition technique formation for the first time, comprise the figure of the gate metal layer of public electrode wire, grid and grid line, be that public electrode wire and grid and grid line form simultaneously, and the pixel electrode that makes public electrode wire and follow-up formation underlay substrate to be projected to small part overlapping.
The utility model embodiment also provides a kind of display device, comprises the array base palte that the utility model above-described embodiment provides.This display device can be any product or parts with Presentation Function such as liquid crystal panel, LCD TV, liquid crystal display, digital album (digital photo frame), mobile phone, panel computer.
The display device providing due to the utility model embodiment has identical technical characterictic with the array base palte that above-mentioned the utility model embodiment provides, so also can produce identical technique effect, solves identical technical matters.
The above; it is only embodiment of the present utility model; but protection domain of the present utility model is not limited to this; anyly be familiar with those skilled in the art in the technical scope that the utility model discloses; the variation that can expect easily or replacement, within all should being encompassed in protection domain of the present utility model.Therefore, protection domain of the present utility model should be as the criterion with the protection domain of claim.
Claims (8)
1. an array base palte, is characterized in that: comprise underlay substrate and be formed at successively gate metal layer, gate insulation layer, active layer, source leakage metal level, the protective seam on underlay substrate, and be formed at pixel electrode and the public electrode on described protective seam;
On described protective seam, offer via hole, described pixel electrode is connected with the drain electrode that is arranged in described source leakage metal level by described via hole;
Described drain electrode and described public electrode underlay substrate to be projected to small part overlapping.
2. array base palte according to claim 1, is characterized in that: described pixel electrode and described public electrode arrange with layer.
3. array base palte according to claim 1, is characterized in that: described public electrode is formed on described protective seam, and described public electrode top is formed with insulation course, and described pixel electrode is formed on described insulation course;
Described via hole runs through described protective seam and described insulation course, and described pixel electrode is connected with described drain electrode by described via hole.
4. array base palte according to claim 2, is characterized in that: described pixel electrode and described public electrode are all slit-shaped.
5. array base palte according to claim 3, is characterized in that: described public electrode is tabular, and described pixel electrode is slit-shaped.
6. array base palte according to claim 1, is characterized in that: described pixel electrode is formed on described protective seam, and described pixel electrode top is formed with insulation course, and described public electrode is formed on described insulation course;
Described via hole runs through described protective seam, and described pixel electrode is connected with described drain electrode by described via hole.
7. array base palte according to claim 1, it is characterized in that: also comprise the public electrode wire being connected with described public electrode, described public electrode wire is positioned at described gate metal layer, and described public electrode wire and described pixel electrode underlay substrate to be projected to small part overlapping.
8. a display device, is characterized in that: comprise the array base palte described in claim 1 to 7 any one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320642105.8U CN203502711U (en) | 2013-10-17 | 2013-10-17 | Array substrate and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320642105.8U CN203502711U (en) | 2013-10-17 | 2013-10-17 | Array substrate and display device |
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| Publication Number | Publication Date |
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| CN203502711U true CN203502711U (en) | 2014-03-26 |
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| CN201320642105.8U Expired - Lifetime CN203502711U (en) | 2013-10-17 | 2013-10-17 | Array substrate and display device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103499905A (en) * | 2013-10-17 | 2014-01-08 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
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- 2013-10-17 CN CN201320642105.8U patent/CN203502711U/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103499905A (en) * | 2013-10-17 | 2014-01-08 | 北京京东方光电科技有限公司 | Array substrate, manufacturing method thereof and display device |
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Granted publication date: 20140326 |