CN203481233U - Alpha-IGZO thin film sensing array image sensor - Google Patents
Alpha-IGZO thin film sensing array image sensor Download PDFInfo
- Publication number
- CN203481233U CN203481233U CN201320590530.7U CN201320590530U CN203481233U CN 203481233 U CN203481233 U CN 203481233U CN 201320590530 U CN201320590530 U CN 201320590530U CN 203481233 U CN203481233 U CN 203481233U
- Authority
- CN
- China
- Prior art keywords
- igzo
- image sensor
- connects
- gate
- alpha
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Solid State Image Pick-Up Elements (AREA)
Abstract
The utility model discloses an alpha-IGZO thin film sensing array image sensor, belonging to the technical field of semiconductor devices. The alpha-IGZO thin film sensing array image sensor comprises a group of gate lines and a group of data lines arranged in a crossing mode, and pixel units defined by the gate lines and the data lines and arranged in an array shape. Each pixel unit comprises a thin film transistor and a photoelectric diode; the thin film transistor comprises a source and a drain forming a channel correspondingly; an alpha-IGZO thin film island is arranged between the source and the drain; and the drain is connected with the data line. The alpha-IGZO TFT (Thin Film Transistor) is used for manufacturing an alpha-Si:HPIN sensor, and when the sensor is applied to a real-time X-ray medical image (fluoroscopy) system and/or nondestructive testing system, the system performances are improved. After the alpha-IGZO TFT is used, mobility is 10 to 15 times higher than that of the current commercial amorphous silicon TFT, low cutoff current is provided, the signal to noise ratio is reduced by about 30%, and the real-time medical X-ray image quality is improved greatly.
Description
Technical field
The utility model belongs to technical field of semiconductor device, is specifically related to the image sensor of α-IGZO film-sensing array.
Background technology
Along with the enhancing gradually of people's self health consciousness, various atraumatic medical detection method medical images (as X-ray Chest X-rays) are subject to people's favor.TFT(Thin Film Transistor, thin-film transistor) dull and stereotyped X radiation transducers is vital element in digitized video technology.Due to the technology maturation of the active-matrix non-crystalline silicon tft of read signal in and flat panel industry low with amorphous silicon making PIN photodiode transducer cost, amorphous silicon technology is very extensive in large-scale medical imaging application.
At present, transducer adopts thin-film transistor slab construction conventionally.Non-crystalline silicon tft mobility is very low, 0.5 ~ 1 cm
2/ Vs, in order, for real-time fluorescence fluoroscopy application provides high-quality image, to require system will have very high frame per second (> 30Hz), low cut-off current and signal to noise ratio.
At the end of last century, industrial quarters attempts overcoming the above problems with low temperature polycrystalline silicon TFT.Low temperature polycrystalline silicon TFT has higher mobility, about 50 ~ 150 cm
2/ Vs, and can be integrated into α-Si PIN transducer.Yet because the complicated technology of laser crystallization and corresponding homogeneity question make it be difficult to be applied to massive plate and make.High leakage current causes TFT on-off ratio lower than 6 simultaneously, and this has also increased the background noise while reading.Table 1 has been done contrast (table 1: non-crystalline silicon tft, the contrast of multi-crystal TFT and α-IGZO TFT technology) α-IGZO TFT technology and the existing TFT technology that is applied to medical imaging system.
| tFT technology | mobility (cm 2/ Vs) | cut-off current (A) | switch current ratio | large-area uniformity | annotation |
| α-Si:H | <1 | ~ 10 -12 | ~ 8 | good (Gen-8) | low mobility, is difficult to improve frame per second and increases panel size |
| poly-Si | ~ 100 | ~ 10 -8 | ~ 6 | poor (Gen-4) | need extra dopant implant and crystallization processes |
| α-IGZO | 10 ~ 15 | ~ 10 -13 | ~ 9 | good (Gen-8) | medium mobility technique is simple, good uniformity in glass substrate. |
Utility model content
Not enough for the defect existing in prior art, the purpose of this utility model is to provide the image sensor of α-IGZO film-sensing array, by make α-Si:H PIN transducer with α-IGZO TFT, be applied to real-time medical imaging (fluoroscopy) system and/or non-destructive testing system, and then improved system performance.Mobility after use α-IGZO TFT, than exceed 10 ~ 15 times of current commercial non-crystalline silicon tft, has lower cut-off current, and its signal to noise ratio has also reduced approximately 30%.Significantly improved real time medical X ray image quality.
The image sensor of α-IGZO film-sensing array, comprise be one group of gate line of cross arrangement and one group of data wire and by described gate line and data wire, defined be the pixel cell that array-like is arranged, described pixel cell comprises a film transistor device and a photodiode device, each film transistor device connects corresponding gate line and data wire, and each photodiode device connects bias line and film transistor device drains accordingly;
Described film transistor device, comprises source electrode and the drain electrode of relative formation raceway groove, between described source electrode and drain electrode, is provided with α-IGZO film island, and described drain electrode is connected with data wire.
Described data wire connects charge amplifier, and described charge amplifier connects MUX, described MUX connection mode number converter.
Described first gate line connects first grid driver, and described second gate line connects second grid driver.
Described first gate line both sides connect respectively first grid driver and the 3rd gate drivers, and described second gate line both sides connect respectively second grid driver and the 4th gate drivers.
Described data wire upside connects the first charge amplifier, and downside connects the second charge amplifier.
The image sensor of α-IGZO film-sensing array, also comprise gate electrode on substrate, cover gate insulator on substrate and gate electrode, on α-IGZO film island and etching step island above gate insulator and between source electrode and drain electrode, be positioned at and on source electrode, be provided with PIN step and be positioned at the transparency electrode on PIN step, described transparency electrode connects bias line.
The utility model compared with prior art, to α-Si base PIN transducer, is applied to real time X-ray fluoroscopy by integrated α-IGZO TFT, and tool has the following advantages:
1. frame frequency increases to 40Hz from 30Hz, has increased 31.6%;
2. can drive more pixel, panel also increases to 60cm x 60cm from 45cm x 45cm, has increased by 77.8%;
3. reduce background noise: reduce by 34.5% Johnson noise, 34.8% KTC switching noise and 31.6% TFT and fall into and disturb noise, be less than the cut-off current I of an order of magnitude
off;
4. improved the dynamic range of system, CT dynamic range will improve 25%;
5. be applied to extensive glass and sink to the bottom, cost of manufacture is low;
6. Pixel Dimensions can be below 100um, but still has more than 50% DQE.Therefore, it can be used for making X-ray milk-line machine.
Accompanying drawing explanation
Fig. 1 is the structural representation of array base palte of the present utility model;
Fig. 2 is the structural representation that the employing bigrid of the utility model bilateral read schemes drives;
Fig. 3 is the structural representation that employing four grids of the utility model bilateral read schemes drive;
Fig. 4 is the channel design schematic diagram that the utility model pixel cell is connected to charge amplifier;
Fig. 5 A-5M is the cross-sectional view in the utility model preparation flow;
In figure: 1-gate line, 2-data wire, 3-pixel cell, 4-film transistor device, 5-photodiode device, 6-charge amplifier, 6a-the first charge amplifier, 6b-the second charge amplifier, 7-MUX, 8-analog to digital converter, 9-bias line, 10-gate drivers, 10a-first grid driver, 10b-second grid driver, 10c-the 3rd gate drivers, 10d-the 4th gate drivers, 11-substrate, 12-gate electrode, 13-gate insulator, 14-α-IGZO thin layer, 15-etching step layer, 16-etching step island, 17-α-IGZO film island, 18-source-drain electrode layer, 19-PIN step, 20-transparency electrode, 21-source electrode, 22-drain electrode, 23-the first protective layer, 24-contact chip, 25-the second protective layer, 26-plane layer, 27-flash layer.
Embodiment
Below in conjunction with Figure of description, the utility model is described in further details.
As shown in Figure 1, the image sensor of α-IGZO film-sensing array, comprise be one group of gate line 1 of cross arrangement and one group of data wire 2 and by described gate line 1 and data wire 2, defined be the pixel cell 3 that array-like is arranged, described pixel cell 3 comprises a film transistor device 4 and a photodiode device 5.
Every row film transistor device 4 connects corresponding gate line 1, by controlled by gate line 1.Described gate line 1 connects gate drivers 10.Every row film transistor device 4 connects corresponding data wire 2.Described data wire 2 connects charge amplifier 6.Film transistor device 4 is controlled by gate line 1, and each photodiode device 5 connects bias line 9 and film transistor device 4 drains accordingly.
Image sensor, comprises m bar gate line 1 and n bar data wire 2.N and m are determined by the spacing (spacing between pixel size+two pixel cell) of dull and stereotyped effective area and pixel cell 3.For an effective area, be the image sensor flat board of 45cm x 45cm, Pixel Dimensions is 148um, and the spacing between two neighbors is 8um, and pel spacing is 156um.
Described gate drivers 10 is given every row assigned address in array in order.After a line is designated, the electric charge that the film transistor device 4 in this row can shift storage is to all data wires 2, and what these electric charges were parallel is read, and is transformed into voltage signal by charge amplifier 6.The voltage signal of charge amplifier 6 outputs is sent to analog to digital converter 8 by MUX 7, and analog to digital converter 8 sends digital output signal and carries out picture signal processing to computer.
As a kind of preferred, in order to obtain the maximum frame rate of large scale sensor array, used the bigrid of bilateral read schemes to drive, as Fig. 2.Described first gate line 1 connects first grid driver 10a, and described second gate line 1 connects second grid driver 10b, and described data wire 2 upsides connect the first charge amplifier 6a, and downside connects the second charge amplifier 6b.When bigrid drives, when sequentially specifying the address of first gate line 1 and second gate line 1, can reduce the every frame time of half.
Preferred as another kind, or the employing four grids drivings of bilateral read schemes, as Fig. 3.Described first gate line 1 both sides connect respectively first grid driver 10a and the 3rd gate drivers 10c, described second gate line 1 both sides connect respectively second grid driver 10b and the 4th gate drivers 10d, described data wire 2 upsides connect the first charge amplifier 6a, and downside connects the second charge amplifier 6b.When four grid levels drive, because the effective length of gate line 1 has reduced half, grid RC time constant has also reduced 50%.
In addition, adopt bigrid to drive or the driving of four grids, for the length of data wire 2, the data wire RC constant that bilateral reads end is the same little with one-sided twice, by synthetic data wire impedance after using bilateral read schemes, has reduced half.
In order to reduce the RC time delay of gate line 1 and data wire 2, this just need to reduce grid circuit resistance R
gwith data circuit resistance R
d, and reduce grid-data cross electric capacity (C
data) and other parasitic capacitances (as C
gS), as shown in Figure 4.By increasing the thickness of gate line 1 and data wire 2, reduce TFT G-D overlapping overlapping with G-S, can reduce total RC time of delay.For α-Si TFT, total RC is less than 0.5us time of delay.
For α-Si TFT, photodiode capacitance C
pDwith the upper resistance R of TFT
oN-TFTthe time is read in control.The time of having read is by τ
rEAD=m * τ
pIXELdetermine, wherein τ
pIXEL=R
oN-TFT* C
pIXELbe the time constant of this element sensor, during m=3, can guarantee pixel cell capacitance C
pIXEL99.3% electric charge can be read.C
pIXEL=C
pD+ C
gD, wherein, C
pIXELpixel cell capacitance, C
pDphotodiode capacitance, C
gDit is parasitic TFT overlap capacitance.For t
a-Si=1.5um, ε
a-Si=11 and elemental area size be (148um)
2the effective area A of fill factor, curve factor 70%
pDpIN photodiode, can estimate its capacitor C
pDfor 1pF.C
gDbe parasitic TFT overlap capacitance, for α-Si TFT, be about 32fF.Little C like this
gDnegligible, thereby C
pIXEL=C
pD.
For α-Si TFT, R
oN-TFTbe about 2Mohms.τ
pIXEL=2.08 Mohm*1pF=2.07us.So τ
rEAD=2.07 x 3=6.22us.Suppose the τ time of integration of charge amplifier 6
iNTfor 16.5us, to output voltage V
0can obtain gray value clearly, the total time of reading τ
rEAD/GATELINE,, from starting to formulate gate line address to last output voltage signal, equal τ
rEADwith τ
iNTand.So τ
rEAD/GATE LINE=τ
rEAD+ τ
iNT=22.72 us.This has spent 22.72us x 1442=32.8ms and has read whole framework, means per secondly can obtain 30.5 frameworks.
In order to obtain identical pixel size and panel size, frame per second is greater than 30Hz, or keeps identical frame per second and increase panel size (increasing gate line and the data wire of same pixel spacing size), and we must reduce the resistance R on TFT
oN-TFTobtain little τ
pIXELand τ
rEAD.
When α-IGZO TFT replaces α-Si TFT, because its mobility is about 10 ~ 15 cm
2/ Vs, this makes R
oN-TFTbe down to and be approximately 0.25 Mohms.For single gate line τ
pIXEL=0.25Mohm*1pF=0.25us, τ
rEAD=0.25x3=0.76us.Suppose the τ time of integration of charge amplifier 6
iNTfor 16.5us, every the time of reading τ that gate line 1 is total
rEAD/GATE LINEgeneral is 17.26us.Read whole framework and spend 17.26us x 1442=24.9ms, by replacing α-Si TFT frame per second can be increased to 40.17Hz from 30.52Hz with α-IGZO TFT.
If keep the identical frame per second of 30Hz, α-IGZO TFT can drive more more pixel on large-area flat-plate.Like this, the panel of 60cm x 60cm size is drivable, and wherein effective area has increased 77.7% (3600cm
2vs. 2025cm
2), gate line has increased by 33.3% (3864 vs. 2885) and number of pixels has increased by 77.7% (14,791,716 vs. 8,323,225).
Table two is the performance parameter contrast of a-Si TFT switch and a-IGZO TFT switch
α-IGZO TFT has lower cut-off current and larger switch current ratio compared with α-Si TFT simultaneously, and this can help keep closing in TFT the electric charge of closed state and reduce background noise, the dynamic range of all right improved system.
The preparation method of the image sensor of α-IGZO film-sensing array, comprises the following steps:
1. as shown in Figure 5A, on substrate 11, deposit gate electrode 12 and construct gate line 1 and spacing.Further, described substrate 11 is glass substrate, and gate electrode 12 is double-deck (1500 ~ 2500 Al+500 ~ 1500 Mo) or three layers of (500 ~ 1000 Al+500 ~ 1000, Mo+1500 ~ 2500 Mo) structure.Al is in order to reduce the resistance of gate line 1, and Mo deposits and covers on Al in order to stop Al to form mound shape.With photoetching process and the dry/wet-etching technology of standard, form gate line 1 and spacing;
2. as shown in Figure 5 B, deposit successively gate insulator 13, α-IGZO thin layer 14 and etching step layer 15.Further, PECVD deposition 1500 ~ 2500 SiO
2gate insulator 13, PVD deposition 500 ~ 1000 α-IGZO thin layer 14 carries out 200 ℃ ~ 350 ℃ post annealed in vacuum furnace, the SiO of PECVD deposition 1500 ~ 2500
2etching step layer 15;
3. as shown in Figure 5 C, construct etching step island 16.Further, with photoetching and dry etching, construct the etching step island 16 of TFT;
4. as shown in Figure 5 D, construct α-IGZO film island 17.Further, with photoetching and wet etching, go out α-IGZO film island 17, carry out 200 ℃ ~ 300 ℃ post annealed in vacuum furnace, α-IGZO film island 17 is active area of α-IGZO thin layer (14);
5. as shown in Fig. 5 E, sedimentary origin-drain electrode layer 18.Further, the Cr of PVD deposition 500 ~ 1500 does source-drain electrodes 22;
6. as shown in Fig. 5 F, precipitate and etch PIN step 19 and transparency electrode 20.Further, PECVD deposits three layers of PIN, i.e. 500 ~ 1000 N-α-Si:H, 1 ~ 2.0um I α-Si:H, 300 ~ 1000 P+ α-Si:H, PVD deposits 500 ~ 1000 ITO as transparency electrode 20, with three layers of PIN step 19 of photoetching and dry etching ITO and Cr, forms PIN pixel;
7. as shown in Fig. 5 G, construct source electrode 21 and drain electrode 22.Further, with photoetching and dry etching, construct source electrode 21 and the drain electrode 22 of α-IGZO TFT, in vacuum furnace, carry out subsequently 200 ℃ ~ 300 ℃ annealing;
8. as shown in Fig. 5 H, deposit the first protective layer 23.Further, with PECVD, deposit the first protective layer (23) of the SiON of 0.5 ~ 1.5um;
9. as shown in Fig. 5 I, construct and connect the drain electrode 22 of TFT and the hole of 2 of data wires, be connected the hole of 9 of PIN transducer and bias lines and the hole of opening in advance EDGE CONTACT sheet 24.Further, with photoetching and dry etching, go out to be connected the hole of the drain electrode 22 of TFT and 2 of data wires, the hole that is connected 9 of PIN pixel and bias lines and the hole of opening in advance EDGE CONTACT sheet 24;
10. as shown in Fig. 5 G, deposit and construct data wire 2, bias line 9 and contact chip 24.Further, PVD deposits 500 ~ 1000 Mo, 1.0 ~ 2.0um Al, and 500 ~ 1000 Mo tri-layer data electrodes, construct data wire 2 with photoetching and dry etching, gate line 1 and contact chip 24 subsequently;
11. as shown in Fig. 5 K, deposits the second protective layer 25, opens contact chip 24.Further, the second protective layer 25 of PECVD deposition 0.5 ~ 1.5umSiON, opens contact chip 24 with photoetching and dry etching subsequently;
12. as shown in Fig. 5 L, and complanation applies SOG or BCB forms plane layer 26, and deposition CsI forms flash layer 27;
13. as shown in Fig. 5 M, and tape automated bonding goes out gate drivers 10 and charge amplifier 6.
So far, the image sensor of α-IGZO film-sensing array, comprise substrate 11, be positioned at the gate electrode 12 on substrate 11, cover the gate insulator 13 on substrate 11 and gate electrode 12, above gate insulator 13 and on source electrode 21 and the α-IGZO film island 17 and the etching step island 16 that drain between 22, be positioned at the data wire 2 in drain electrode 22, relatively form source electrode 21 and the drain electrode 22 of raceway groove, with drain electrode 22 data wires that are connected 2, be positioned at and on source electrode 21, be provided with PIN step 19, and be positioned at the transparency electrode 20 on PIN step 19, be positioned at the first protective layer 23 of source electrode 21 and drain electrode 22 tops, connect the contact chip 24 of the first protective layer 23 and gate insulator 13, be positioned at the first protective layer 23, the second protective layer 25 of data wire 2 and bias line 9 tops, be positioned at plane layer 26 and the flash layer 27 of the second protective layer 25 tops.
Table three is this sensor characteristics form
| Sensor characteristics book | ? |
| Type | Based on CsI(cesium iodide) scintillator technology, the electronic plane transducer of high-quality digital picture is provided |
| Size sensor | 43 cm x 43 cm (17 " x17 "), for dissimilar test, comprise lung and pelvis, guarantee that best patient covers |
| Pixel size | 148um provides the picture quality of high spatial resolution for radiating test |
| Image array size | 2880 pixel x 2881 pixels |
| Dynamic frame per second | Be up to the comprehensive perspective program of 30 frame per second |
| Pulse perspective | To 15 umber of pulses per second, can reduce x-ray dose at most |
Table four is the performance parameter table of comparisons of this transducer and non-crystalline silicon tft
| Thin Film Transistor (TFT) | Amorphous silicon | Indium oxide gallium zinc |
| Pixel size (um) | 148 | 148 |
| Frame rate (Hz) | 30.16 | 32.42 |
| Panel length (cm) | 45 | 60 |
| Panel width (cm) | 45 | 60 |
| Door switch line number | 2,885 | 3,846 |
| Pixel reads the time | 5.39 | 0.64 |
| Pixel quantity | 8,323,225 | 14,791,716 |
| Mobility Ueff (cm2/Vs) | 0.82 | 12.20 |
As can be seen from the above table, for identical pixel size, identical frame rate, this transducer door switch line number has improved 33.3%, and pixel quantity has promoted 77.7%, with the obvious advantage.
Shown in the above and figure; it is only preferred embodiment of the present utility model; be not limited to protection range of the present utility model, all being equal to replacement, revising or improving of making in conception principle of the present utility model,, within being all included in protection range of the present utility model.
Claims (6)
1. the image sensor of α-IGZO film-sensing array, it is characterized in that, comprise the one group of gate line (1) and the one group of data wire (2) that are cross arrangement, and by described gate line (1) and data wire (2), defined be the pixel cell (3) that array-like is arranged, described pixel cell (3) comprises a film transistor device (4) and a photodiode device (5), each film transistor device (4) connects corresponding gate line (1) and data wire (2), each photodiode device (5) connects bias line (9) and the corresponding drain electrode of film transistor device (4) (22),
Described film transistor device (4), comprises source electrode (21) and the drain electrode (22) of relative formation raceway groove, between described source electrode (21) and drain electrode (22), is provided with α-IGZO film island (17), and described drain electrode (22) is connected with data wire (2).
2. the image sensor of α-IGZO film-sensing array as claimed in claim 1, it is characterized in that, described data wire (2) connects charge amplifier (6), and described charge amplifier (6) connects MUX (7), described MUX (7) connection mode number converter (8).
3. the image sensor of α-IGZO film-sensing array as claimed in claim 1, is characterized in that, described first gate line (1) connects first grid driver (10a), and described second gate line (1) connects second grid driver (10b).
4. the image sensor of α-IGZO film-sensing array as claimed in claim 1, it is characterized in that, described first gate line (1) both sides connect respectively first grid driver (10a) and the 3rd gate drivers (10c), and described second gate line (1) both sides connect respectively second grid driver (10b) and the 4th gate drivers (10d).
5. the image sensor of the α-IGZO film-sensing array as described in claim 3 or 4, is characterized in that, described data wire (2) upside connects the first charge amplifier (6a), and downside connects the second charge amplifier (6b).
6. the image sensor of α-IGZO film-sensing array as claimed in claim 1, it is characterized in that, also comprise the gate electrode (12) being positioned on substrate (11), cover the gate insulator (13) on substrate (11) and gate electrode (12), be positioned at gate insulator (13) top and α-IGZO film island (17) and etching step island (16) between source electrode (21) and drain electrode (22), be positioned at and on source electrode (21), be provided with PIN step (19), and be positioned at the transparency electrode (20) on PIN step (19), described transparency electrode (20) connects bias line (9).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320590530.7U CN203481233U (en) | 2013-09-24 | 2013-09-24 | Alpha-IGZO thin film sensing array image sensor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320590530.7U CN203481233U (en) | 2013-09-24 | 2013-09-24 | Alpha-IGZO thin film sensing array image sensor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203481233U true CN203481233U (en) | 2014-03-12 |
Family
ID=50229508
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320590530.7U Expired - Fee Related CN203481233U (en) | 2013-09-24 | 2013-09-24 | Alpha-IGZO thin film sensing array image sensor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203481233U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681717A (en) * | 2013-09-24 | 2014-03-26 | 徐廷贵 | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof |
| CN109935605A (en) * | 2019-03-12 | 2019-06-25 | 上海奕瑞光电子科技股份有限公司 | Imaging sensor and preparation method thereof |
| WO2020082390A1 (en) | 2018-10-27 | 2020-04-30 | Huawei Technologies Co., Ltd. | Sensor and display device |
-
2013
- 2013-09-24 CN CN201320590530.7U patent/CN203481233U/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103681717A (en) * | 2013-09-24 | 2014-03-26 | 徐廷贵 | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof |
| WO2020082390A1 (en) | 2018-10-27 | 2020-04-30 | Huawei Technologies Co., Ltd. | Sensor and display device |
| US11594161B2 (en) | 2018-10-27 | 2023-02-28 | Huawei Technologies Co., Ltd. | Sensor and display device |
| CN109935605A (en) * | 2019-03-12 | 2019-06-25 | 上海奕瑞光电子科技股份有限公司 | Imaging sensor and preparation method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2021106287A (en) | Semiconductor device and method for manufacturing the same | |
| CN100369267C (en) | Semiconductor device and display comprising same | |
| CN103096799B (en) | Radiographic imaging device and radiographic imaging system | |
| CN103928470B (en) | Oxide semiconductor TFT array substrate and manufacturing method thereof | |
| JP2023182700A (en) | display device | |
| CN105097675A (en) | Array substrate and preparation method thereof | |
| CN203481233U (en) | Alpha-IGZO thin film sensing array image sensor | |
| CN102593164A (en) | Radiation imaging device, radiation imaging display system, and transistor | |
| CN102738206A (en) | Oxide semiconductor film and semiconductor device | |
| CN105489552A (en) | Manufacturing method of LTPS array substrate | |
| CN104600028B (en) | The preparation method and its structure of low temperature polycrystalline silicon TFT substrate | |
| CN103928343B (en) | Thin film transistor (TFT) and organic light emitting diode display preparation method | |
| CN102544110B (en) | Thin film transistor with parasitic capacitance correction structure, and liquid crystal display with thin film transistor | |
| CN104465669A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN104167998A (en) | Amplifier circuit and image sensor using amplifier | |
| CN104952885A (en) | Display baseplate, manufacturing method thereof and display device | |
| CN105789117A (en) | Manufacturing method of TFT substrate and manufactured TFT substrate | |
| CN106663685A (en) | Semiconductor device and method for manufacturing same | |
| CN108550601B (en) | Radiographic imaging array fabrication process for metal oxide thin film transistors with reduced mask count | |
| CN104599959A (en) | Manufacturing method and structure of low-temperature polycrystalline silicon TFT substrate | |
| CN103681717A (en) | An image sensor of an alpha-IGZO film sensing array and a manufacturing method thereof | |
| JP2014192320A (en) | Imaging device and imaging display system | |
| US9564461B2 (en) | Radiation image-pickup device and radiation image-pickup display system | |
| CN102759832B (en) | Liquid crystal display substrate and manufacturing method thereof | |
| CN105355593A (en) | TFT substrate manufacturing method and TFT substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140312 Termination date: 20200924 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |