CN203481232U - Array baseboard and display device - Google Patents
Array baseboard and display device Download PDFInfo
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- CN203481232U CN203481232U CN201320584570.0U CN201320584570U CN203481232U CN 203481232 U CN203481232 U CN 203481232U CN 201320584570 U CN201320584570 U CN 201320584570U CN 203481232 U CN203481232 U CN 203481232U
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Abstract
The utility model discloses an array baseboard and a display device. The array baseboard contains a substrate baseboard and a buffer layer, a semiconductor layer, a grid insulating layer, a grid metal layer, an interlayer dielectric layer, a source-drain metal layer and a pixel electrode layer which are successively formed on the substrate baseboard. The array baseboard also comprises a common electrode layer formed between the substrate baseboard and the buffer layer. In the technical scheme, as the common electrode layer can be formed on the substrate baseboard before the buffer layer is formed, the common electrode layer can form storage capacitance with the pixel electrode layer and also can form storage capacitance with the semiconductor layer, thus increasing the storage capacitance of the array baseboard, raising pixel voltage holding ratio of the array baseboard and reducing bad phenomena such as scintillation of the display device and the like. in addition, in comparison with the prior art, as subsequent technological processes of a protection layer, a passivation layer and the like also can be saved, film structure and making process of the array baseboard can be simplified.
Description
Technical field
The utility model relates to Display Technique field, relates in particular to a kind of array base palte and display unit.
Background technology
Along with TFT(Thin Film Transistor, thin-film transistor) development of lcd technology, possess low in energy consumption, resolution is high, reaction speed is fast and aperture opening ratio high based on LTPS(Low Temperature Poly-silicon, low temperature polycrystalline silicon) the TFT display unit of technology becomes main flow gradually, various electronic equipments have been widely used in, in the digital electronic devices such as LCD TV, smart mobile phone, panel computer and digital camera.
But, in the high-resolution products such as TFT display unit based on LTPS technology, more and more higher along with product resolution and aperture opening ratio, can cause the pel spacing (pixel pitch) of the array base palte of LTPS TFT display unit more and more less, and then cause the storage capacitance of array base palte more and more less.Due to for LTPS tft array substrate, in onesize leakage current situation, the less meeting of storage capacitance causes the conservation rate of pixel voltage lower, and then can cause the generation of bad phenomenon such as flicker (Flicker) etc., greatly reduced the quality of the high-resolution products such as array base palte or TFT display unit, therefore, how when not affecting array base palte aperture opening ratio, to improve its storage capacitance, become the problem that industry is needed solution badly.
Utility model content
The utility model embodiment provides a kind of array base palte and display unit, in order to solve less the caused array base palte of storage capacitance or the lower problem of display unit quality of the array base palte existing in prior art.
The utility model embodiment provides a kind of array base palte, described array base palte comprises underlay substrate, is formed on resilient coating, semiconductor layer, gate insulator, grid metal level, interlayer dielectric layer, source leakage metal level and the pixel electrode layer on described underlay substrate successively, also comprises:
Be formed on the common electrode layer between described underlay substrate and described resilient coating.
In embodiment described in the utility model, can be before forming resilient coating, on underlay substrate, form common electrode layer, make common electrode layer not only can form storage capacitance with pixel electrode layer, also can form storage capacitance with semiconductor layer, thereby played the effect of the bad phenomenon such as flicker that increase the storage capacitance of array base palte, the pixel voltage conservation rate that improves array base palte and reduction display unit, improved the quality of array base palte and display unit.
In addition; compared with prior art; because described pixel electrode layer can be formed directly in described source, leak on metal level, thereby also can save the technique preparation flows such as follow-up protective layer and passivation layer, thereby also can reach, simplify the film layer structure of array base palte and the effect of manufacture craft.
Further, the floor projection region on described underlay substrate and the described semiconductor layer floor projection region on described underlay substrate exists overlapping with described pixel electrode layer respectively in the floor projection region of described common electrode layer on described underlay substrate.
Further, described semiconductor layer is polysilicon layer.
Further, the pattern that metal level comprises source electrode, drain electrode and data wire is leaked in described source, is formed with and is respectively used to source electrode via hole and drain via that described source electrode, drain electrode are electrically connected to described semiconductor layer in described interlayer dielectric layer and gate insulator.
Further, described common electrode layer is prepared from by transparent conductive material.
Wherein, described transparent conductive material is ITO(indium tin oxide target).
Further, the utility model embodiment also provides a kind of display unit, and described display unit comprises the array base palte described in the utility model embodiment.
The utility model beneficial effect is as follows:
The utility model embodiment provides a kind of array base palte and display unit, described array base palte comprises underlay substrate, is formed on resilient coating, semiconductor layer, gate insulator, grid metal level, interlayer dielectric layer, source leakage metal level and the pixel electrode layer on described underlay substrate successively, also comprises: be formed on the common electrode layer between described underlay substrate and described resilient coating.In embodiment described in the utility model, due to can be before forming resilient coating, on underlay substrate, form common electrode layer, make common electrode layer not only can form storage capacitance with pixel electrode layer, also can form storage capacitance with semiconductor layer, play the effect of the bad phenomenon such as flicker that increase the storage capacitance of array base palte, the pixel voltage conservation rate that improves array base palte and reduction display unit, improved the quality of array base palte and display unit; In addition, compared with prior art, owing to also can saving the technological processes such as follow-up protective layer and passivation layer, thereby also can reach, simplify the film layer structure of array base palte and the effect of manufacture craft.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the utility model embodiment, below the accompanying drawing of required use during embodiment is described is briefly introduced, apparently, accompanying drawing in the following describes is only embodiment more of the present utility model, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Figure 1 shows that the structural representation of array base palte described in the utility model embodiment mono-;
Fig. 2 (a) is depicted as the manufacture craft schematic diagram one of array base palte described in the utility model embodiment mono-;
Fig. 2 (b) is depicted as the manufacture craft schematic diagram two of array base palte described in the utility model embodiment mono-;
Fig. 2 (c) is depicted as the manufacture craft schematic diagram three of array base palte described in the utility model embodiment mono-;
Fig. 2 (d) is depicted as the manufacture craft schematic diagram four of array base palte described in the utility model embodiment mono-;
Fig. 2 (e) is depicted as the manufacture craft schematic diagram five of array base palte described in the utility model embodiment mono-;
Fig. 2 (f) is depicted as the manufacture craft schematic diagram six of array base palte described in the utility model embodiment mono-;
Fig. 2 (g) is depicted as the manufacture craft schematic diagram seven of array base palte described in the utility model embodiment mono-;
Fig. 2 (h) is depicted as the manufacture craft schematic diagram eight of array base palte described in the utility model embodiment mono-;
Fig. 2 is (i) depicted as the manufacture craft schematic diagram nine of array base palte described in the utility model embodiment mono-;
Figure 3 shows that the planar structure schematic diagram of array base palte described in the utility model embodiment mono-.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with accompanying drawing, the utility model is described in further detail, obviously, described embodiment is only the utility model part embodiment, rather than whole embodiment.Embodiment based in the utility model, those of ordinary skills are not making all other embodiment that obtain under creative work prerequisite, all belong to the scope of the utility model protection.
Embodiment mono-:
The utility model embodiment mono-provides a kind of array base palte, as shown in Figure 1, it is the structural representation of array base palte described in the utility model embodiment mono-, described array base palte comprises underlay substrate 11, be formed on resilient coating 12 on described underlay substrate 11, semiconductor layer 13, gate insulator 14, grid metal level 15, interlayer dielectric layer 16, source successively leaks metal level 17 and pixel electrode layer 18, particularly, described array base palte also comprises:
Be formed on the common electrode layer 19 between described underlay substrate 11 and described resilient coating 12.
Particularly, described common electrode layer 19 can partly cover described underlay substrate 11, and the floor projection region on described underlay substrate 11 and the floor projection region of described semiconductor layer 13 on described underlay substrate 11 exist overlapping with described pixel electrode layer 18 respectively in the floor projection region of described common electrode layer 19 on described underlay substrate 11.
Further, described common electrode layer 19 can be prepared from by transparent conductive material conventionally, and described transparent conductive material can be ITO, AZO(Al-Doped ZnO) etc. material, the utility model embodiment is not limited in any way this.
Further, described semiconductor layer 13 can be polysilicon layer or non-polysilicon layer; Particularly, in embodiment described in the utility model, described semiconductor layer 13 can be polysilicon layer conventionally.
Further, metal level 17 is leaked in described source can comprise the pattern of source electrode, drain electrode and data wire conventionally, and the utility model embodiment does not repeat this; Correspondingly, in described interlayer dielectric layer 16 and gate insulator 14, also can be formed with and be respectively used to described source to leak the source electrode in metal level 17, source electrode via hole and the drain via (label is 161 or 162 respectively) that drain electrode is electrically connected to described semiconductor layer 13, the utility model embodiment does not repeat this yet.
In embodiment described in the utility model, can be before forming resilient coating 12, on underlay substrate 11, form common electrode layer 19, make common electrode layer 19 not only can form storage capacitance with pixel electrode layer 18, also can form storage capacitance with semiconductor layer 13, play the effect of the bad phenomenon such as flicker that increase the storage capacitance of array base palte, the pixel voltage conservation rate that improves array base palte and reduction display unit, improved the quality of array base palte and display unit.
In addition; compared with prior art; owing to being no longer provided with the film layer structures such as protective layer, common electrode layer and passivation layer between described pixel electrode layer 18 and described source leakage metal level 17; therefore; also the technique preparation flows such as follow-up protective layer and passivation layer be can save, thereby also can reach, the film layer structure of array base palte and the effect of manufacture craft simplified.
Particularly, the mode with array base palte fabrication processing figure is elaborated to the structure of array base palte described in the utility model embodiment below, and the manufacture craft of described array base palte can comprise the following steps:
Step 101: on underlay substrate 11, form common electrode layer 19, specifically can be as shown in Figure 2 (a) shows.
Particularly, described underlay substrate 11 can be glass substrate or plastic base etc., and the utility model embodiment is not limited in any way this; Further, form common electrode layer 19 on described underlay substrate 11 before, can carry out pre-cleaning operation to described underlay substrate 11, afterwards, can adopt the modes such as deposition, sputter on described underlay substrate 11, to form public electrode thin layer, and by comprising that the composition technique of the techniques such as photoresist coating, exposure, development, etching, photoresist lift off forms the common electrode layer 19 that possesses setting pattern on described underlay substrate 11, the utility model embodiment does not repeat this.
Further, the pattern of described common electrode layer 19 can partly cover described underlay substrate 11, and, in order to reach the object of the storage capacitance that increases array base palte, in embodiment described in the utility model, the pattern of described common electrode layer 19 can meet the following conditions conventionally: the floor projection region on described underlay substrate 11 and the floor projection region of semiconductor layer 13 on described underlay substrate 11 exist overlapping with pixel electrode layer 18 respectively in the floor projection region of described common electrode layer 19 on described underlay substrate 11, thereby make described common electrode layer 19 not only can form storage capacitance with pixel electrode layer 18, also can form storage capacitance with semiconductor layer 13, and then reach the storage capacitance that increases array base palte, improve the object of array base palte and display unit product energy.
It should be noted that, the pattern of described common electrode layer 19 can also all cover described underlay substrate 11, can reduce like this composition technique one time, but can increase some unnecessary parasitic capacitances, therefore, preferably, the pattern part of described common electrode layer 19 covers described underlay substrate, and the floor projection region on described underlay substrate 11 and the floor projection region of semiconductor layer 13 on described underlay substrate 11 exist overlapping with pixel electrode layer 18 respectively in its floor projection region on described underlay substrate 11.
Step 102: in described common electrode layer 19, form resilient coating 12, specifically can be as shown in Fig. 2 (b).
Particularly, in embodiment described in the utility model, can adopt CVD(Chemical Vapor Deposition, chemical vapour deposition (CVD)) etc. method in described common electrode layer 19, deposit resilient coating 12; Further, the double hyer insulation layer structure that described resilient coating 12 can form for silicon nitride film layer and silicon oxide film layer, can be the monolayer insulating layer structures such as silicon nitride film layer or silicon oxide film layer, the utility model embodiment be limited in any way this yet.
Step 103: on described resilient coating 12, form semiconductor layer 13, specifically can be as shown in Figure 2 (c).
Particularly, described semiconductor layer 13 can be polysilicon layer or non-polysilicon layer; When described semiconductor layer 13 is polysilicon layer, can adopt the methods such as CVD deposited amorphous silicon layer on described resilient coating 12, and to adopt the methods such as quasi-molecule laser annealing (ELA) or solid-phase crystallization (SPC) be polysilicon by described amorphous silicon crystallization, afterwards, then by comprising that the composition technique of the techniques such as photoresist coating, exposure, development, etching, photoresist lift off forms required poly-silicon pattern.
Step 104: on described semiconductor layer 13, form gate insulator 14, specifically can be as shown in Figure 2 (d) shows.
Particularly, can adopt the methods such as CVD to deposit gate insulator 14 on described semiconductor layer 13; Further, described gate insulator 14 can be silicon oxide layer, silicon nitride layer or the composite insulation layer that is comprised of silicon oxide layer and silicon nitride layer etc., and the utility model embodiment is not limited in any way this.
Step 105: on described gate insulator 14, form grid metal level 15, specifically can be as shown in Fig. 2 (e).
Particularly, described grid metal level 15 can comprise the pattern of grid, grid line and public electrode wire, and the utility model embodiment does not repeat this; And, while forming grid metal level 15 on described gate insulator 14, can adopt PVD(Physical Vapor Deposition, physical vapour deposition (PVD)) etc. method forms a metal level on described gate insulator 14, and by comprising that the composition technique of the techniques such as photoresist coating, exposure, development, etching, photoresist lift off once forms the pattern of grid, grid line and public electrode wire on described gate insulator 14.
Further, described metal level can be aluminium lamination, tungsten layer, chromium layer or other metals and metallic compound conductive layer etc., and the utility model embodiment is not limited in any way this.
Step 106: on described grid metal level 15, form interlayer dielectric layer 16, specifically can be as shown in Fig. 2 (f).
Particularly, can adopt the methods such as CVD on described grid metal level 15, to deposit described interlayer dielectric layer 16, to play the described grid metal level 15 of protection and to isolate described grid metal level 15 and the object of follow-up source leakage metal level 17; Wherein, described interlayer dielectric layer 16 can be prepared from by materials such as silica, silicon nitrides, and the utility model embodiment is not limited in any way this.
Step 107: within described interlayer dielectric layer 16 and described gate insulator 14, form to connect to the source electrode via hole of described semiconductor layer 13 and drain via (wherein, described source electrode via hole and drain via respectively label are 161 or 162), specifically can be as shown in Fig. 2 (g).
Particularly, can adopt one or many composition technique within described interlayer dielectric layer 16 and described gate insulator 14, to form source electrode via hole, the drain via of the described semiconductor layer 13 that can go directly, the utility model embodiment is not limited in any way this.
Step 108: in described source electrode via hole 161, drain via 162 and possess on the interlayer dielectric layer 16 of described source electrode via hole 161, drain via 162 and form and comprise source electrode, drain electrode (wherein, described source electrode, drain electrode respectively label are 171 or 172) source leak metal level 17, specifically can be as shown in Fig. 2 (h).
Particularly, in this step 108, can possess interlayer dielectric layer 16 surface deposition one electric conducting materials of source electrode via hole 161 and drain via 162, and by comprise the composition technique of the techniques such as photoresist coating, exposure, development, etching, photoresist lift off form comprise described source electrode 171,172 the source of draining leaks metal level 17.
Wherein, described electric conducting material can be aluminium, tungsten, chromium or other metals and metallic compound etc., and the utility model embodiment is not limited in any way this.
It should be noted that, because described source leakage metal level 17 can comprise the pattern of source electrode, drain electrode and data wire conventionally, therefore, similarly to the prior art, in this step 108, forming source electrode 171, drain in 172, can also form data wire (Data) simultaneously, the utility model embodiment does not repeat this.
Step 109: in described source, leak on metal level 17 and form pixel electrode layer 18, specifically can as Fig. 2 (i) as shown in.
Particularly, can adopt the methods such as CVD to leak on metal level 17 and deposit a transparent conductive material layer in described source, and by comprising that the composition technique of the techniques such as photoresist coating, exposure, development, etching, photoresist lift off obtains possessing the pixel electrode layer 18 of setting pattern.
It should be noted that, resulting pixel electrode layer 18 can be electrically connected to the drain electrode 172 that leak in metal level 17 in described source conventionally, and the utility model embodiment no longer repeats this.
That is to say, after above-mentioned steps 101～step 109, can obtain the array base palte described in the utility model embodiment, particularly, the planar structure schematic diagram of resulting array base palte can be as shown in Figure 3 (in Fig. 3, VIA1 can finger source electrode via hole 161, VIA2 can refer to drain via 162, and, clear in order to illustrate, each in Fig. 3 layer structure is all transparent or semitransparent pattern signals), wherein, described common electrode layer (Vcom) 19 under can being positioned at described pixel electrode layer (Pixel) 18, also can expanded scope to the semiconductor layer 13(of described pixel electrode layer 18 1 sides be the active layer described in Fig. 3) under, thereby make described common electrode layer 19 not only can form storage capacitance with pixel electrode layer 18, also can form storage capacitance with semiconductor layer 13, reaching simplification array base palte manufacture craft, on the basis of film layer structure, reached the storage capacitance that increases array base palte, improve the object of array base palte and display unit product energy.
The utility model embodiment mono-provides a kind of array base palte, described array base palte comprises underlay substrate, is formed on resilient coating, semiconductor layer, gate insulator, grid metal level, interlayer dielectric layer, source leakage metal level and the pixel electrode layer on described underlay substrate successively, also comprises: be formed on the common electrode layer between described underlay substrate and described resilient coating.In embodiment described in the utility model, due to can be before forming resilient coating, on underlay substrate, form common electrode layer, make common electrode layer not only can form storage capacitance with pixel electrode layer, also can form storage capacitance with semiconductor layer, play the effect of the bad phenomenon such as flicker that increase the storage capacitance of array base palte, the pixel voltage conservation rate that improves array base palte and reduction display unit, improved the quality of array base palte and display unit; In addition, compared with prior art, owing to also can saving the technological processes such as follow-up protective layer and passivation layer, thereby also can reach, simplify the film layer structure of array base palte and the effect of manufacture craft.
It should be noted that; the utility model embodiment all be take top gate type TFT that semiconductor layer is polysilicon layer and is described as example; the TFT that is amorphous silicon layer etc. for semiconductor layer; the utility model embodiment is applicable equally; and the TFT for bottom gate type TFT or other malformations; as long as need to, by increasing the scheme that increases storage capacitance over against area, also all belong to the protection range of the utility model embodiment.
Embodiment bis-:
The utility model embodiment bis-provides a kind of display unit, described display unit can be display panels, Electronic Paper, OLED(Organic Light-Emitting Diode, Organic Light Emitting Diode) any product or parts that possess Presentation Function such as panel, mobile phone, panel computer, television set, display, notebook computer, DPF, navigator, the utility model embodiment is not limited in any way this; Particularly, described display unit comprises the array base palte described in the utility model embodiment mono-, and the utility model embodiment bis-repeats no more this.
It should be noted that, display unit described in the utility model embodiment can be TN(Twisted Nematic, twisted-nematic) pattern, VA(Vertical Alignment, vertical orientated) pattern, IPS(In-Plane Switching, plane conversion technology) pattern or ADS(Advanced Super Dimension Switch, a senior super dimension switch technology) pattern, the utility model embodiment is not limited in any way this; More preferably, the display unit described in the utility model embodiment is particularly useful for IPS pattern and ADS pattern.
Obviously, those skilled in the art can carry out various changes and modification and not depart from spirit and scope of the present utility model the utility model.Like this, if within of the present utility model these are revised and modification belongs to the scope of the utility model claim and equivalent technologies thereof, the utility model is also intended to comprise these changes and modification interior.
Claims (7)
1. an array base palte, comprises underlay substrate, is formed on resilient coating, semiconductor layer, gate insulator, grid metal level, interlayer dielectric layer, source leakage metal level and the pixel electrode layer on described underlay substrate successively, it is characterized in that, also comprises:
Be formed on the common electrode layer between described underlay substrate and described resilient coating.
2. array base palte as claimed in claim 1, is characterized in that,
Floor projection region on described underlay substrate and the described semiconductor layer floor projection region on described underlay substrate exists overlapping with described pixel electrode layer respectively in the floor projection region of described common electrode layer on described underlay substrate.
3. array base palte as claimed in claim 1, is characterized in that, described semiconductor layer is polysilicon layer.
4. array base palte as claimed in claim 3, it is characterized in that, the pattern that metal level comprises source electrode, drain electrode and data wire is leaked in described source, is formed with and is respectively used to source electrode via hole and drain via that described source electrode, drain electrode are electrically connected to described semiconductor layer in described interlayer dielectric layer and gate insulator.
5. array base palte as claimed in claim 1, is characterized in that,
Described common electrode layer is prepared from by transparent conductive material.
6. array base palte as claimed in claim 5, is characterized in that,
Described transparent conductive material is indium tin oxide target.
7. a display unit, is characterized in that, comprises the arbitrary described array base palte of claim 1～6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320584570.0U CN203481232U (en) | 2013-09-22 | 2013-09-22 | Array baseboard and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320584570.0U CN203481232U (en) | 2013-09-22 | 2013-09-22 | Array baseboard and display device |
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| CN203481232U true CN203481232U (en) | 2014-03-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106023825A (en) * | 2016-06-22 | 2016-10-12 | 联想(北京)有限公司 | Display screen, manufacturing method of display screen and electronic equipment |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106023825A (en) * | 2016-06-22 | 2016-10-12 | 联想(北京)有限公司 | Display screen, manufacturing method of display screen and electronic equipment |
| CN106023825B (en) * | 2016-06-22 | 2021-02-19 | 联想(北京)有限公司 | Display screen, manufacturing method of display screen and electronic equipment |
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