CN203480293U - Intelligent I<2>C bus identification controlling apparatus - Google Patents
Intelligent I<2>C bus identification controlling apparatus Download PDFInfo
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- CN203480293U CN203480293U CN201320569322.9U CN201320569322U CN203480293U CN 203480293 U CN203480293 U CN 203480293U CN 201320569322 U CN201320569322 U CN 201320569322U CN 203480293 U CN203480293 U CN 203480293U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
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Abstract
The utility model, which belongs to the field of the industrial control technology, especially relates to an intelligent I<2>C bus identification controlling apparatus that is suitable for the industrial intelligent control system. The intelligent identification controlling apparatus comprises a CPU module and at least one function module; the CPU module realizes power supplying by a 24-V power line and a function module; and the CPU module carries out module tail end identification and address distribution between the CPU module and the function module by multi-path parallel data lines. The multi-path parallel data lines include a tail end determination line for identifying whether the own module has a tail end function, a reset line with the reset function, an input latch line with the input latch function, an output refresh line with the output refresh function, and an address distribution line with the address distribution function. The provided apparatus effectively utilizes the I<2>C bus and other signal lines to realize back plate communication and module intelligent identification of the distributed control system. Moreover, the provided apparatus has the advantages of simple structure, convenient function module expansion, less occupies resources, and high efficiency and energy conservation.
Description
Technical field
The utility model belongs to industrial control technology field, particularly a kind of I
2c bus Intelligent Recognition control device, is applicable to industrial intelligent control system.
Background technology
At industrial control field, intelligent controller application is very extensive, is the core industry of futurity industry automation development.Existing intelligent controller is applied more aspect intelligent appliance, but applies also in developing stage in the especially system-level Industry Control of Industry Control.Existing intelligent controller mainly comprises RS232, RS485, Modebus and CAN etc. in the communication of industry spot, and RS232, RS485, Modebus communication coding are simple, and application is convenient, but from module without specific address position, intelligent not; CAN communication robust is good, be widely used, but plate level communication medium-rate is at the scene slower, is applicable to long term distance communication.I
2c bus is a two-way two wire bus, for transmit data between integrated circuit.I
2c bus, without any need for voltage transitions or special interface, has advantages of that the resource of taking is few, easy to operate.I
2c is a twin wire universal serial bus, is respectively serial data line SDA and serial time clock line SCL, I
2each device in C bus is identified by unique address.Some address of devices are by the configuration of external hardware own, and some address of devices have been cured in chip internal and not configurable.Existing for I
2the research of C concentrates on its communication mode mostly, and has ignored I in industrial control field
2the application of C communication in intellectuality, I
2c is because the advantages such as its address is unique, speed is fast are well worth doing in the intelligent field of Industry Control.
Summary of the invention
The purpose of this utility model is: overcome the deficiencies in the prior art, a kind of novel I is provided
2c bus Intelligent Recognition control device, this device greatly increased industrial control field Intelligent Recognition and can expansion.
For achieving the above object, the technical solution of the utility model is as follows:
An I2C bus Intelligent Recognition control device, comprises a CPU module 1 and at least one functional module 2; Described CPU module 1 realizes power supply by 24V power lead 3 and functional module 2; Described 24V power lead 3 is common external 24V stabilized voltage supply, and 24V+ is positive source, and 24VGND is power cathode; Described CPU module 1 realizes the identification of module tail end and address assignment between CPU module 1 and functional module 2 by multidiameter delay data line; Described CPU module 1 realizes the communication between the obtaining and install of module information of described functional module 2 by I2C connection 4; Described multidiameter delay data line comprises the reset line 6, the input and latch line 7 with input and latch function that have tail end discriminant line 5 that whether self module of identification is tail end function, have reset function, have the output refresh line 8 of output refresh function and have the address assignment line 9 of address allocation function; Described tail end discriminant line 5 input ends are connected to this module 24V power lead 3 anodal 24V+, and output terminal is connected to the IO port of this functional module CPU, are connected with the tail end discriminant line of next module; Current functional module tail end discriminant line is connected with the 24V+ of the 24V power lead of next module, if tail end, tail end discriminant line is low level, this tail end signal is transferred to this module CPU, then by I2C connection, tail end information is fed back to CPU module 1, take that this judges by detecting tail end discriminant line signal whether this module is tail end module.
The further technical scheme of the utility model is as follows:
Preferably, described address assignment line 9 input ends are connected to an IO port of this functional module CPU, and output terminal is connected to another IO port of this functional module CPU, and are connected with the input end of the address assignment line of next functional module.
Preferably, described CPU module 1 and functional module 2 are the intelligent controller with I2C interface; Described I2C connection 4 is the I2C bus being comprised of serial time clock line SCL and two lines of serial data line SDA, forms inner I2C bus, and CPU module 1 is as I2C host node, functional module 2 as I2C from node.
Preferably, described address assignment line 9 is for after functional module 2 judgements are certainly as tail end module, and CPU module 1 distributes different addresses to each functional module 2 according to groove position.
Preferably, described reset line 6, input and latch line 7, output refresh line 8 are the general data line of the IO port that is connected to this functional module CPU.
Preferably, described reset line 6, for CPU module 1 each functional module 2 of reset; Described input and latch line 7 notifies each functional module 2 input cycles for CPU module 1, and each functional module 2 is no longer revised the current data interlock that will input simultaneously in internal memory, and the input that guarantees each module is the data of synchronization; Output refresh line 8 is input to the current data that will export after each functional module 2 for CPU module 1, and output refresh line 8 is effective, and the data that each module will be exported simultaneously output to port.
Technique effect of the present utility model is as follows:
The I that the utility model provides
2c bus Intelligent Recognition control device effectively utilizes I
2c bus realizes and controls and communicate by letter with other signal wires, by the Intelligent Recognition of tail end Intelligent Recognition and address smart allocation practical function module, thereby make control device have simple in structure, functional module expand convenient, take few, the energy-efficient feature of resource, guaranteed real-time and the expansion of control device.
Accompanying drawing explanation
Fig. 1 is the utility model apparatus structure schematic diagram;
Fig. 2 is the utility model functional module information.
Embodiment
Below in conjunction with drawings and Examples, that the utility model is described in further detail is as follows:
embodiment 1:
An I2C bus Intelligent Recognition control device, it comprises a CPU module 1 and at least one functional module 2; CPU module 1 realizes power supply by 24V power lead 3 and functional module 2; 24V power lead 3 is common external 24V stabilized voltage supply, and 24V+ is positive source, and 24VGND is power cathode; CPU module 1 realizes the identification of module tail end and address assignment between CPU module 1 and functional module 2 by multidiameter delay data line; CPU module 1 realizes the communication between the obtaining and install of module information of described functional module 2 by I2C connection 4; Multidiameter delay data line comprises the reset line 6, the input and latch line 7 with input and latch function that have tail end discriminant line 5 that whether self module of identification is tail end function, have reset function, have the output refresh line 8 of output refresh function and have the address assignment line 9 of address allocation function; Tail end discriminant line 5 input ends are connected to this module 24V power lead 3 anodal 24V+, and output terminal is connected to the IO port of this functional module CPU, are connected with the tail end discriminant line of next module; Current functional module tail end discriminant line is connected with the 24V+ of the 24V power lead of next module, if tail end, tail end discriminant line is low level, this tail end signal is transferred to this module CPU, then by I2C connection, tail end information is fed back to CPU module 1, take that this judges by detecting tail end discriminant line signal whether this module is tail end module.
In the present embodiment, I2C functional module address of devices can distribute by CPU module, functional module information has been cured in each functional module, by providing an I2C interface from controller to each I2C, master controller operates respectively each functional module, first gives from controller and distributes an address, then setting data transport-type, realize master controller and from the communication between controller, thereby obtain the module information of functional module, with the control that realizes the later stage with communicate by letter.
embodiment 2:
Different from above-described embodiment 1, furtherly, the present embodiment comprises 3 functional modules, and CPU module 1 and functional module 2 are with I
2the intelligent controller of C interface; I
2c connection 4 is the I being comprised of serial time clock line SCL and two lines of serial data line SDA
2c bus, forms inner I
2c bus, CPU module 1 is as I
2c host node, functional module 2 is as I
2c is from node.Concrete operations flow process is concise and to the point is divided into initial phase, tail end judgement, address assignment and data transmit-receive three parts.
1) initial phase
Port and I2C clock rate and other hardware informations of initial phase configuration CPU module, and CPU module is set is main frame, then broadcasts start signal to remaining each functional module.Functional module receives after start signal, starts to carry out tail end judgement.
2) tail end judgement
By tail end discriminant line, directly judge tail end.Its judgement flow process is: tail end discriminant line is connected with the 24V+ of the 24V power lead of next module, if tail end, tail end discriminant line is low level, and this tail end signal is transferred to this module CPU, and CPU judges by detecting tail end discriminant line signal whether this module is tail end module.After the tail end module of device being detected, CPU module enters address assignment.
3) address assignment
Address assignment line 9 input ends are connected to an IO port of this functional module CPU, and output terminal is connected to another IO port of this functional module CPU, and are connected with the input end of the address assignment line of next functional module.As shown in Figure 1, after device powers on, CPU module sends reseting data, after each functional module resets, the I2C bus address of the CPU of each functional module is set to maximal value (0xFE), and meanwhile, the response I2C position (AA position) of the CPU of each functional module is made as and does not respond I2C.
The CPU of CPU module is now made as height by address assignment line, only has the CPU of direct-connected (nearest) first functional module with it high signal can be detected, and the CPU of other functional module due to by last block lock this signal, can't detect high level.
The CPU module of first functional module detects after high signal, to respond I2C position (AA) and be made as response I2C, the CPU of CPU module and 0xFE address communication, obtain this module information, for example module type, tail end etc. whether, then a functional module is given in address of the every sub-distribution of CPU module, and if first functional module address is exactly 0x02, second functional module address is 0x04, the 3rd functional module address is 0x06, until be judged as the tail end module of tail end before.When first functional module received behind address, the address assignment of end and CPU module is revised self I2C address simultaneously, then opens the partition line in this module, and the high level of partition line is delivered to second functional module.
The CPU of CPU module after having completed the communication of first module, after time delay a period of time, with second carry out address allocation procedure, with first module class seemingly.Until tail end module assignment is complete, halt address distributes.
4) data transmit-receive
The data type of each functional module has two kinds, and a class is functional module information, and this information has been cured in functional module, comprises module's address, module type numbering, module data type, and module channels number, module data amount types etc., are shown in accompanying drawing 2; Another kind of is functional module data, and this information is real time data, as distributed system collects the controlled quentity controlled variable information of data message or required transmission.
After CPU module's address assigning process finishes, device enters the data transmit-receive stage, and CPU module is obtained functional module information and functional module data.The transmitting-receiving of I2C bus data exists the data transmission of two kinds of processes: main transmitter is to sending data from receiver and sending data from transmitter to main receiver.These two kinds of processes all comprise two stages, are initial phase and data transfer phase.
In data transmit-receive process, the information that now functional module receives CPU module is carried out address configuration to self module, next functional module is understood sending function module information, and byte of the every acceptance of CPU module is just returned to a response bits, until functional module information is sent.If first functional module is 8 tunnel 0 ~ 5V voltage analog load modules, its sending function module information comprises module's address, module type numbering, module data type, module channels number, module data amount type etc., for " 0,x02 01 AI 05 V ", after CPU module is received the module information of this functional module, just this functional module is defined, when dissimilar module interpolation is deleted or replaces, CPU module can be received different functional module information, thus the intelligent recognition function of implement device.After clear and definite each functional module information, functional module can sending module real time data to CPU module be processed and return to control information or feedback information by CPU module, thus the intelligent control function of implement device.
embodiment 3:
Different from above-described embodiment 2, furtherly, address assignment line 9 is for after functional module 2 judgements are certainly as tail end module, and CPU module 1 distributes different addresses to each functional module 2 according to groove position.Reset line 6, input and latch line 7, output refresh line 8 are the general data line of the IO port that is connected to this functional module CPU.Reset line is for CPU module 1 each functional module 2 of reset; Input and latch line 7 notifies each functional module 2 input cycles for CPU module 1, and each functional module 2 is no longer revised the current data interlock that will input simultaneously in internal memory, and the input that guarantees each module is the data of synchronization; Output refresh line 8 is input to the current data that will export after each functional module 2 for CPU module 1, and output refresh line 8 is effective, and the data that each module will be exported simultaneously output to port.
The utility model protection domain is not limited to above-described embodiment.
Claims (6)
1. an I
2c bus Intelligent Recognition control device, is characterized in that, comprises a CPU module (1) and at least one functional module (2);
Described CPU module (1) realizes power supply by 24V power lead (3) and functional module (2); Described 24V power lead (3) is common external 24V stabilized voltage supply, and 24V+ is positive source, and 24VGND is power cathode;
Described CPU module (1) realizes the identification of module tail end and address assignment between CPU module (1) and functional module (2) by multidiameter delay data line; Described CPU module (1) is passed through I
2c connection (4) is realized the communication between the obtaining and install of module information of described functional module (2);
Described multidiameter delay data line comprises the reset line (6), the input and latch line (7) with input and latch function that have tail end discriminant line (5) that whether self module of identification is tail end function, have reset function, have the output refresh line (8) of output refresh function and have the address assignment line (9) of address allocation function;
Described tail end discriminant line (5) input end is connected to the anodal 24V+ of this module 24V power lead (3), and output terminal is connected to the IO port of this functional module CPU, is connected with the tail end discriminant line of next module; Current functional module tail end discriminant line is connected with the 24V+ of the 24V power lead of next module, if tail end, tail end discriminant line is low level, and this tail end signal is transferred to this module CPU, then passes through I
2c connection feeds back to CPU module (1) by tail end information, take that this judges by detecting tail end discriminant line signal whether this module is tail end module.
2. I as claimed in claim 1
2c bus Intelligent Recognition control device, it is characterized in that, described address assignment line (9) input end is connected to an IO port of this functional module CPU, and output terminal is connected to another IO port of this functional module CPU, and is connected with the input end of the address assignment line of next functional module.
3. I as claimed in claim 1
2c bus Intelligent Recognition control device, is characterized in that, described CPU module (1) and functional module (2) are with I
2the intelligent controller of C interface; Described I
2c connection (4) is the I being comprised of serial time clock line SCL and two lines of serial data line SDA
2c bus, forms inner I
2c bus, CPU module (1) is as I
2c host node, functional module (2) is as I
2c is from node.
4. I as claimed in claim 2
2c bus Intelligent Recognition control device, is characterized in that, described address assignment line (9) is for after functional module (2) judgement is certainly as tail end module, and CPU module (1) distributes different addresses to each functional module (2) according to groove position.
5. I as claimed in claim 1
2c bus Intelligent Recognition control device, is characterized in that, described reset line (6), input and latch line (7), output refresh line (8) are the general data line of the IO port that is connected to this functional module CPU.
6. the I as described in one of claim 1 to 5
2c bus Intelligent Recognition control device, is characterized in that, described reset line (6), for CPU module (1) each functional module (2) that resets; Described input and latch line (7) notifies each functional module (2) input cycle to start for CPU module (1), each functional module (2) is no longer revised the current data interlock that will input simultaneously in internal memory, and the input that guarantees each module is the data of synchronization; Output refresh line (8) is input to the current data that will export after each functional module (2) for CPU module (1), and output refresh line (8) is effective, and the data that each module will be exported simultaneously output to port.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320569322.9U CN203480293U (en) | 2013-09-15 | 2013-09-15 | Intelligent I<2>C bus identification controlling apparatus |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320569322.9U CN203480293U (en) | 2013-09-15 | 2013-09-15 | Intelligent I<2>C bus identification controlling apparatus |
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| CN203480293U true CN203480293U (en) | 2014-03-12 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519763A (en) * | 2018-03-30 | 2018-09-11 | 新华三技术有限公司 | Control circuit and apparatus control method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108519763A (en) * | 2018-03-30 | 2018-09-11 | 新华三技术有限公司 | Control circuit and apparatus control method |
| CN108519763B (en) * | 2018-03-30 | 2019-09-13 | 新华三技术有限公司 | Control circuit and apparatus control method |
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Legal Events
| Date | Code | Title | Description |
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| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20200107 Address after: 430223 No.22, University Garden Road, Donghu New Technology Development Zone, Wuhan City, Hubei Province Patentee after: Wuhan Changhai electric propulsion and chemical power supply Co.,Ltd. Address before: 430064, Hubei, Wuhan province Hongshan District lion Street School car school Patentee before: The 712nd Research Institute of China Shipbuilding Industry Corporation |
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| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20140312 |