CN203467027U - Circuit used for realizing controllable silicon dimming and high power factor - Google Patents
Circuit used for realizing controllable silicon dimming and high power factor Download PDFInfo
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- CN203467027U CN203467027U CN201320540247.3U CN201320540247U CN203467027U CN 203467027 U CN203467027 U CN 203467027U CN 201320540247 U CN201320540247 U CN 201320540247U CN 203467027 U CN203467027 U CN 203467027U
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Abstract
The utility model discloses a circuit used for realizing controllable silicon dimming and a high power factor. According to the utility model, through a first sampling circuit and a second sampling circuit, primary voltage signal sampling is realized; the average output current and output voltage of a load LED is nothing to do with and a load; good input voltage adjustment rate and load adjustment rate are acquired; constant current output control of the load LED is realized; after the circuit used for realizing controllable silicon dimming and the high power factor is added into the existing flyback LED drive circuit based on primary side feedback, the primary input current can track an alternating current input sine waveform and the average output current of the load LED can change with the change of a controllable silicon trigger angle; and the high power factor and controllable silicon dimming are realized.
Description
Technical field
The utility model relates to a kind of for realizing the circuit of controllable silicon light modulation and High Power Factor, particularly relate to a kind of based on former limit feedback for realizing the circuit of controllable silicon light modulation and High Power Factor.
Background technology
Under the background improving constantly in global energy shortage, environmental requirement, green energy conservation illumination is all greatly developed in countries in the world.LED illumination is as a kind of revolutionary energy-saving illumination technology, just in develop rapidly.Yet the requirement of LED driving power is also improving constantly.High efficiency, High Power Factor, EMI standard, high Current Control precision, high reliability are isolated, met to safety, volume is little, cost is low etc. just becoming the key grading index of LED driving power.In addition,, due to the direct replace incandescent of needs LED lamp, LED driving power also must be able to adapt to traditional controllable silicon dimmer and carry out light modulation.
The existing inverse-excitation type LED drive circuit based on former limit feedback, as shown in Figure 1, comprising: AC power; LC filter; Elementary absorbing circuit; The transformer being formed by armature winding, secondary winding and auxiliary winding; Be connected in the secondary circuit of described secondary winding; Be connected in the auxiliary power supply circuit of described auxiliary winding; Power switch pipe M1; Power switch pipe current sampling resistor R4 and LED Drive and Control Circuit.
LED Drive and Control Circuit in Fig. 1 (claiming in the utility model that this control circuit is critical conduction mode flyback constant-current control module) comprising: the first comparator, the second comparator, trigger, grid drive and lead-edge-blanking circuit.This LED Drive and Control Circuit, when work, needs the extraction information relevant with output voltage and peak primary currents, and conducting and the cut-off of by the GATE signal of GATE port, exporting modulation signal power ratio control switching tube M1, carrys out the electric current of constant load LED.In the system shown in Fig. 1, the above-mentioned information relevant with output voltage and peak primary currents can be extracted by the signal CS of CS port and the signal DEMAG of DEMAG port.The average current that can derive load LED according to correlation theory meets formula below:
Wherein,
for load LED average output current, N is the turn ratio of the main secondary winding of transformer, I
pkfor peak primary currents,
for the ON time of power switch pipe M1,
for the deadline of power switch pipe M1.
The first comparator in Fig. 1 is relatively realized peak primary currents I by sampling CS signal and benchmark Vref3
pkbe a fixed value, the second comparator is relatively realized by sampling DEMAG signal and benchmark Vref4
being a fixed value, like this, is load LED average output current
will be one not with the fixed value of input voltage and load variations, thereby realize constant current, drive.But such control mode cannot realize high power factor and controllable silicon light modulation.Because if realize high power factor, primary current waveform must be followed the tracks of and exchange input sine wave shape; If realize input controllable silicon light modulation, load LED average output current must change along with the variation of SCR Trigger Angle.
In sum, in order to realize high power factor and controllable silicon light modulation, also need on the basis of the existing inverse-excitation type LED drive circuit based on former limit feedback, increase extra control circuit.
Summary of the invention
Technical problem to be solved in the utility model is, provide a kind of for realizing the circuit of controllable silicon light modulation and High Power Factor, after this circuit adds, can make the existing inverse-excitation type LED drive circuit based on former limit feedback can realize high power factor and controllable silicon light modulation.
For solving the problems of the technologies described above, the technical solution adopted in the utility model is: a kind of for realizing the circuit of controllable silicon light modulation and High Power Factor, this circuit comprises: the first sample circuit, the second sample circuit, the first switch, described the first switch comprises first grid, first terminal and the second terminal, second switch, described second switch comprises second grid, third terminal and the 4th terminal, the 3rd switch, described the 3rd switch comprises the 3rd grid, the 5th terminal and the 6th terminal, transistor seconds, described transistor seconds comprises the 4th grid, the 7th terminal and the 8th terminal, the 3rd transistor, described the 3rd transistor comprises the 5th grid, the 9th terminal and the tenth terminal, the 4th transistor, described the 4th transistor comprises the 6th grid, the 11 terminal and the 12 terminal, digital to analog converter, counter, inverter, the first operational amplifier, the second operational amplifier, the 7th resistance, the 5th electric capacity, the first comparator, the first trigger, delay circuit, the 5th resistance, the 6th resistance, the 8th resistance, the second comparator, wherein, after described the first sample circuit sampling external voltage signal processing, be sent to the positive input terminal of described the second operational amplifier, the negative input end of described the second operational amplifier is connected to described the 12 terminal, the output of described the second operational amplifier is connected to described the 6th grid, after described the second sample circuit sampling external voltage signal processing, be sent to the positive input terminal of described the first operational amplifier, the negative input end of described the first operational amplifier is connected to described the tenth terminal, the output of described the first operational amplifier is connected to described the 5th grid, described the 9th terminal is connected to described the second terminal, described the 11 terminal is connected to described the 4th terminal, described first terminal and third terminal are connected to described the 8th terminal after merging, described the 7th terminal receives externally fed voltage, described the 4th grid is connected to respectively described the 8th terminal and described digital to analog converter, described first grid is connected to respectively the input of described inverter, the non-end of Q of the 3rd grid and outside the second trigger, described second grid is connected to the output of described inverter, described the tenth terminal is connected to the positive input terminal of described the second comparator, described the tenth terminal and the 12 terminal are respectively by described the 5th resistance and the 6th grounding through resistance, described digital to analog converter is connected to respectively described counter, one end of the 5th terminal and the 7th resistance, the other end of described the 7th resistance is connected to respectively one end of the 8th resistance and the negative input end of outside the 3rd comparator, the other end ground connection of described the 8th resistance, described the 6th terminal is connected to respectively one end of described the 5th electric capacity and the negative input end of the first comparator, the other end ground connection of described the 5th electric capacity, the positive input terminal of described the first comparator is connected to the first reference voltage, the negative input end of described the second comparator is connected to the second reference voltage, described the first comparator exports described the first trigger to, the output of described the second comparator is connected to respectively the CLK end of described counter and one end of delay circuit, the D termination of described the first trigger is received externally fed voltage, the non-end of Q of described the first trigger is connected to the UP/DN end of described counter, the CLR end of described the first trigger is connected to the other end of described delay circuit.
Preferably, described for realizing the circuit of controllable silicon light modulation and High Power Factor, described the first sample circuit comprises: the 9th resistance, the tenth resistance, the 11 resistance, the 5th transistor, the 6th electric capacity and the second inverter, one end of described the tenth resistance is connected to the drain electrode of outside the first transistor, the other end of described the tenth resistance is connected to respectively one end of described the 11 resistance and one end of the 9th resistance, the other end ground connection of described the 11 resistance, the other end of described the 9th resistance is connected to described the 5th transistorized one end, described the 5th transistorized other end is connected to respectively one end of described the 6th electric capacity and the positive input terminal of described the second operational amplifier, described the 5th transistorized grid is connected to the output of described the second inverter, the input of described the second inverter is connected to the grid of outside the first transistor, the other end ground connection of described the 6th electric capacity, described the second sample circuit comprises: the 12 resistance and the 13 resistance, one end of described the 12 resistance is connected to the output of outside LC filter, the other end of described the 12 resistance is connected to respectively one end of positive input terminal and the 13 resistance of described the first operational amplifier, the other end ground connection of described the 13 resistance.
Preferably, described for realizing the circuit of controllable silicon light modulation and High Power Factor, described the 5th transistor is N-type field effect transistor.
Preferably, described for realizing the circuit of controllable silicon light modulation and High Power Factor, described the first sample circuit comprises: the 9th resistance, the tenth resistance, the 11 resistance and the 6th electric capacity, one end of described the tenth resistance is connected to the drain electrode of outside the first transistor, the other end of described the tenth resistance is connected to respectively one end of described the 11 resistance and one end of the 9th resistance, the other end ground connection of described the 11 resistance, the other end of described the 9th resistance is connected to respectively one end of described the 6th electric capacity and the positive input terminal of the second operational amplifier, the other end ground connection of described the 6th electric capacity, described the second sample circuit comprises: the 12 resistance, the 13 resistance, the 14 resistance, the 5th transistor and the 7th electric capacity, one end of described the 12 resistance is connected to the output of outside LC filter, the other end of described the 12 resistance is connected to respectively described the 5th transistorized one end, the 13 one end of resistance and one end of the 14 resistance, the other end ground connection of described the 13 resistance, described the 5th transistorized other end ground connection, described the 5th transistorized grid is connected to the grid of outside the first transistor, the other end of described the 14 resistance is connected to respectively one end of positive input terminal and the 7th electric capacity of described the first operational amplifier, the other end ground connection of described the 7th electric capacity.
Preferably, described for realizing the circuit of controllable silicon light modulation and High Power Factor, described the first sample circuit comprises: the tenth resistance and the 11 resistance, one end of described the tenth resistance is connected to the output of outside LC filter, the other end of described the tenth resistance is connected to respectively one end of described the 11 resistance and the positive input terminal of the second operational amplifier, the other end ground connection of described the 11 resistance, described the second sample circuit comprises: the 12 resistance, the 13 resistance, the 14 resistance, the 5th transistor and the 7th electric capacity, one end of described the 12 resistance is connected to the output of outside LC filter, the other end of described the 12 resistance is connected to respectively described the 5th transistorized one end, the 13 one end of resistance and one end of the 14 resistance, the other end ground connection of described the 13 resistance, described the 5th transistorized other end ground connection, described the 5th transistorized grid is connected to the grid of outside the first transistor, the other end of described the 14 resistance is connected to respectively one end of positive input terminal and the 7th electric capacity of described the first operational amplifier, the other end ground connection of described the 7th electric capacity.
Preferably, described for realizing the circuit of controllable silicon light modulation and High Power Factor, described the first sample circuit comprises: the 9th resistance, the tenth resistance, the 11 resistance, the 5th transistor, the 6th electric capacity and the second inverter, one end of described the tenth resistance is connected to the drain electrode of outside the first transistor, the other end of described the tenth resistance is connected to respectively one end of described the 11 resistance and one end of the 9th resistance, the other end ground connection of described the 11 resistance, the other end of described the 9th resistance is connected to described the 5th transistorized one end, described the 5th transistorized other end is connected to respectively one end of described the 6th electric capacity and the positive input terminal of described the second operational amplifier, described the 5th transistorized grid is connected to the output of described the second inverter, the input of described the second inverter is connected to the grid of outside the first transistor, the other end ground connection of described the 6th electric capacity, described the second sample circuit comprises: the 12 resistance, the 13 resistance, the 14 resistance and the 7th electric capacity, one end of described the 12 resistance is connected to the drain electrode of outside the first transistor, the other end of described the 12 resistance connects respectively the 13 one end of resistance and one end of the 14 resistance, the other end ground connection of described the 13 resistance, the other end of described the 14 resistance is connected to respectively one end of positive input terminal and the 7th electric capacity of described the first operational amplifier, the other end ground connection of described the 7th electric capacity.
Preferably, described also comprises for realizing the circuit of controllable silicon light modulation and High Power Factor: critical conduction mode flyback constant-current control module, and this module comprises: the 3rd comparator, the second trigger, grid driving, the 4th comparator and lead-edge-blanking circuit, wherein, the negative input end of described the 3rd comparator is connected on the junction point of described the 7th resistance and the 8th resistance, the positive input terminal of described the 3rd comparator is connected to one end of described lead-edge-blanking circuit, the output of described the 3rd comparator is connected to the D end of described the second trigger, the S end of described the second trigger is connected to the output of described the 4th comparator, the Q end of described the second trigger is connected to the input that described grid drives, the non-end of Q of described the second trigger is connected to described first grid, the negative input end of described the 4th comparator is for the voltage voltage division signal of the outside auxiliary winding of sampling, the positive input terminal of described the 4th comparator receives the 4th reference voltage, the output that described grid drives is connected to the grid of outside the first transistor, the other end of described lead-edge-blanking circuit is connected to the source electrode of described outside the first transistor.
Preferably, describedly for realizing the circuit of controllable silicon light modulation and High Power Factor, also comprise: rectifier bridge; LC filter; Elementary absorbing circuit; The transformer being formed by armature winding, secondary winding and auxiliary winding; Be connected in the secondary circuit of described secondary winding; Be connected in the auxiliary power supply circuit of described auxiliary winding; The first transistor; The 4th resistance; Described rectifier bridge, LC filter, elementary absorbing circuit and transformer are connected in series successively, and the drain electrode of described the first transistor is connected to described armature winding, and the source electrode of described the first transistor is by the 4th grounding through resistance.
Preferably, describedly for realizing the circuit of controllable silicon light modulation and High Power Factor, also comprise: controllable silicon dimmer, described controllable silicon dimmer is connected to the front end of described rectifier bridge.
Preferably, describedly for realizing the circuit of controllable silicon light modulation and High Power Factor, also comprise: AC power, described AC power is connected to the front end of described controllable silicon dimmer.
The utility model has the advantages that, the utility model is by the first sample circuit and the second sample circuit elementary voltage signal of sampling, realized for the average output current of load LED and output voltage and load irrelevant, thereby obtained good input voltage regulation and load regulation, realized the constant current output of load LED is controlled; Simultaneously, the utility model is added to the existing inverse-excitation type LED drive circuit based on former limit feedback for the circuit of realizing controllable silicon light modulation and High Power Factor after, elementary input current can be followed the tracks of exchange input sine wave shape and can be along with SCR Trigger Angle to the average output current of load LED
variation and change, thereby realized higher power factor and controllable silicon light modulation.
Accompanying drawing explanation
Fig. 1 is the existing inverse-excitation type LED drive circuit based on former limit feedback;
Fig. 2 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the first embodiment;
Fig. 3 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the first alternate embodiment;
Fig. 4 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the second alternate embodiment;
Fig. 5 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the 3rd alternate embodiment;
Fig. 6 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the 4th alternate embodiment.
Embodiment
For further disclosing the technical solution of the utility model, be hereby described with reference to the accompanying drawings execution mode of the present utility model:
Basic conception of the present utility model is as follows: Fig. 2 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the first embodiment, and figure comprises: AC power 116; Controllable silicon dimmer 117; Rectifier bridge; LC filter; Elementary absorbing circuit; The transformer being formed by armature winding, secondary winding and auxiliary winding; Be connected in the secondary circuit of described secondary winding; Be connected in the auxiliary power supply circuit of described auxiliary winding; Power switch pipe M1 is the first transistor M1; Power switch pipe M1 current sampling resistor R4 and LED Drive and Control Circuit, the grid of described power switch pipe M1 is connected with the GATE port of LED Drive and Control Circuit, the drain electrode of described power switch pipe M1 is connected with described armature winding, and the source electrode of described power switch pipe M1 is by described power switch pipe M1 current sampling resistor R4 ground connection.Wherein, described LED Drive and Control Circuit comprises peak current reference generator module and critical conduction mode flyback constant-current control module, described peak current reference generator module is of the present utility model for realizing the circuit of controllable silicon light modulation and High Power Factor, the input VC1 of described peak current reference generator module and VC2 are for sampling elementary voltage signal, and the output Vref3 of this circuit offers the peak current benchmark that critical conduction mode flyback constant-current control module needs.Described critical conduction mode flyback constant-current control module is that the input DEMAG of existing LED Drive and Control Circuit is for the voltage voltage division signal of the described auxiliary winding of sampling, the input CS of described critical conduction mode flyback constant-current control module is for the voltage signal on sampled power switching tube M1 current sampling resistor R4, and the output GATE of described critical conduction mode flyback constant-current control module is for driving power switching tube M1.
[the first embodiment] particularly, as shown in Figure 2, described peak current reference generator module is that the utility model comprises for realizing the circuit of controllable silicon light modulation and High Power Factor: a kind of for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, this circuit comprises: the first sample circuit 101, the second sample circuit 118, the first interrupteur SW 1, described the first interrupteur SW 1 comprises first grid, first terminal and the second terminal, second switch SW2, described second switch SW2 comprises second grid, third terminal and the 4th terminal, the 3rd interrupteur SW 3, described the 3rd interrupteur SW 3 comprises the 3rd grid, the 5th terminal and the 6th terminal, transistor seconds M2, described transistor seconds M2 comprises the 4th grid, the 7th terminal and the 8th terminal, the 3rd transistor M3, described the 3rd transistor M3 comprises the 5th grid, the 9th terminal and the tenth terminal, the 4th transistor M4, described the 4th transistor M4 comprises the 6th grid, the 11 terminal and the 12 terminal, digital to analog converter 103, counter 104, inverter 102, the first operational amplifier 105, the second operational amplifier 106, the 7th resistance R 7, the 5th capacitor C 5, the first comparator 107, the first trigger 110, delay circuit 109, the 5th resistance R 5, the 6th resistance R 6, the 8th resistance R 8, the second comparator 108, wherein, after described the first sample circuit 101 sampling external voltage signals processing, be sent to the positive input terminal of described the second operational amplifier 106, the negative input end of described the second operational amplifier 106 is connected to described the 12 terminal, the output of described the second operational amplifier 106 is connected to described the 6th grid, after described the second sample circuit 118 sampling external voltage signals processing, be sent to the positive input terminal of described the first operational amplifier 105, the negative input end of described the first operational amplifier 105 is connected to described the tenth terminal, the output of described the first operational amplifier 105 is connected to described the 5th grid, described the 9th terminal is connected to described the second terminal, described the 11 terminal is connected to described the 4th terminal, described first terminal and third terminal are connected to described the 8th terminal after merging, described the 7th terminal receives externally fed voltage, described the 4th grid is connected to respectively described the 8th terminal and described digital to analog converter 103, described first grid is connected to respectively the input of described inverter 102, the non-end of Q of the 3rd grid and outside the second trigger 112, described second grid is connected to the output of described inverter 102, described the tenth terminal is connected to the positive input terminal of described the second comparator 108, described the tenth terminal and the 12 terminal are respectively by described the 5th resistance R 5 and the 6th resistance R 6 ground connection, described digital to analog converter 103 is connected to respectively described counter 104, one end of the 5th terminal and the 7th resistance R 7, the other end of described the 7th resistance R 7 is connected to respectively one end of the 8th resistance R 8 and the negative input end of outside the 3rd comparator 111, the other end ground connection of described the 8th resistance R 8, be that tie point place output the 3rd reference voltage V ref3 of described the 7th resistance R 7 and the 8th resistance R 8 is to the negative input end of outside the 3rd comparator 111, described the 6th terminal is connected to respectively one end of described the 5th capacitor C 5 and the negative input end of the first comparator 107, the other end ground connection of described the 5th capacitor C 5, the positive input terminal of described the first comparator 107 is connected to the first reference voltage V ref1, the negative input end of described the second comparator 108 is connected to the second reference voltage V ref2, described the first comparator 107 exports described the first trigger 110 to, the output of described the second comparator 108 is connected to respectively the CLK end of described counter 104 and one end of delay circuit 109, the D termination of described the first trigger 110 is received externally fed voltage, the non-end of Q of described the first trigger 110 is connected to the UP/DN end of described counter 104, the CLR end of described the first trigger 110 is connected to the other end of described delay circuit 109.
In addition, described critical conduction mode flyback constant-current control module comprises: the 3rd comparator 111, the second trigger 112, grid drive the 113, the 4th comparator 114 and lead-edge-blanking circuit 115, wherein, the negative input end of described the 3rd comparator 111 be connected on the junction point of described the 7th resistance R 7 and the 8th resistance R 8 be the negative input end of described the 3rd comparator 111 be connected to described peak current reference generator module output to receive the 3rd reference voltage V ref3, , the positive input terminal of described the 3rd comparator 111 is connected to one end of described lead-edge-blanking circuit 115, the output of described the 3rd comparator 111 is connected to the D end of described the second trigger 112, the S end of described the second trigger 112 is connected to the output of described the 4th comparator 114, the Q end of described the second trigger 112 is connected to described grid and drives 113 input, the non-end of Q of described the second trigger 112 is connected to described first grid, the negative input end of described the 4th comparator 114 is for the voltage voltage division signal of the outside auxiliary winding of sampling, the positive input terminal of described the 4th comparator 114 receives the 4th reference voltage V ref4, the output of described grid driving 113 is connected to the grid of outside the first transistor M1, the other end of described lead-edge-blanking circuit 115 is connected to the source electrode of described outside the first transistor M1.
[the first alternate embodiment] Fig. 3 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the first alternate embodiment; this figure be only the utility model for realizing the first sample circuit 101 of circuit and an example of the second sample circuit 118 of controllable silicon light modulation and High Power Factor, it does not limit the protection range of claim.In Fig. 3, described the first sample circuit 101 comprises: the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 5th transistor M5, the 6th capacitor C 6 and the second inverter, one end of described the tenth resistance R 10 is connected to the drain electrode of outside the first transistor M1, the other end of described the tenth resistance R 10 is connected to respectively one end of described the 11 resistance R 11 and one end of the 9th resistance R 9, the other end ground connection of described the 11 resistance R 11, the other end of described the 9th resistance R 9 is connected to one end of described the 5th transistor M5, the other end of described the 5th transistor M5 is connected to respectively one end of described the 6th capacitor C 6 and the positive input terminal of described the second operational amplifier 106, the grid of described the 5th transistor M5 is connected to the output of described the second inverter, the input of described the second inverter is connected to the grid of outside the first transistor M1, the other end ground connection of described the 6th capacitor C 6, described the second sample circuit 118 comprises: the 12 resistance R 12 and the 13 resistance R 13, one end of described the 12 resistance R 12 is connected to the output of outside LC filter, the other end of described the 12 resistance R 12 is connected to respectively described first positive input terminal of operational amplifier 105 and one end of the 13 resistance R 13, the other end ground connection of described the 13 resistance R 13.
As shown in Figure 3, the utility model is as follows for realizing the course of work of circuit of controllable silicon light modulation and High Power Factor: after sampling primary voltage VC2 and VC1, carry out division arithmetic again and obtain the reference voltage V ref3 that system needs.In Fig. 3: be the sample circuit that N-type field effect transistor M5, the 6th capacitor C 6 and the second inverter have formed VC2 by the 9th resistance R 9, the tenth resistance R the 10, the 11 resistance R 11, the 5th transistor M5, this circuit role is envelope detected, the signal of sampling be prime power switching tube M1 drain electrode voltage signal (be denoted as: Vdrain), its Output rusults is:
, wherein, k is constant herein,
for armature winding input voltage,
for alternating current phases, N is the turn ratio of the main secondary winding of transformer,
output voltage for secondary LED two ends.The VC1 sample circuit being formed by the 12 resistance R 12 and the 13 resistance R 13, this circuit role is that dividing potential drop detects, the signal of sampling is that elementary input voltage signal (is denoted as V
in), its Output rusults is:
.The circuit function that the first operational amplifier 105, the 3rd transistor M3 and the 5th resistance R 5 form be to convert the voltage signal of voltage-dividing detection circuit output to current signal I
3, the circuit function that the second operational amplifier 106, the 4th transistor M4 and the 6th resistance R 6 form be to convert the voltage signal of envelope detected circuit output to current signal I
4.Visible in figure, when the first interrupteur SW 1 and the 3rd interrupteur SW 3 conducting, second switch SW2 closes, and vice versa.First, when the first interrupteur SW 1 and the 3rd beginning SW3 conducting, when second switch SW2 closes, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
3copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
.
Wherein,
for the gain of digital to analog converter 103, its value is subject to control from 0 to 255/256 variation of counter 104.
When the first interrupteur SW 1 and the 3rd interrupteur SW 3 are closed, second switch SW2 conducting, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
4copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
,
Here, herein
,
.
As Fig. 3, the peak current of prime power switching tube M1 forms feedback voltage by the 4th resistance R 4 of sampling and enters by CS port, after lead-edge-blanking circuit 115, compare with reference voltage V ref3, when this voltage is during higher than Vref3, the high signal of the 3rd comparator 111 output is to the D port of the second trigger 112, the second trigger 112 output low signals drive 113 to grid, and grid drives 113 output low signals to close prime power switching tube M1.After the output voltage of assisting winding to sample is by the second resistance R 2 and the 3rd resistance R 3 dividing potential drops, be input to DEMAG port, this voltage is by the 4th comparator 114 and reference voltage V ref4 comparison, when this voltage is during higher than reference voltage V ref4, the high signal of the 4th comparator 114 output is to the D port of the second trigger 112, the high signal of the second trigger 112 output drives 113 to grid, grid drives the high signal of 113 output to open prime power switching tube M1, and each cycle goes round and begins again afterwards.Obtaining thus load LED average output current can be expressed as:
。
[the second alternate embodiment] Fig. 4 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the second alternate embodiment; this figure be only the utility model for realizing the first sample circuit 101 and 118 1 examples of the second sample circuit of the circuit of controllable silicon light modulation and High Power Factor, it does not limit the protection range of claim.In Fig. 4, described the first sample circuit 101 comprises: the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11 and the 6th capacitor C 6, one end of described the tenth resistance R 10 is connected to the drain electrode of outside the first transistor M1, the other end of described the tenth resistance R 10 is connected to respectively one end of described the 11 resistance R 11 and one end of the 9th resistance R 9, the other end ground connection of described the 11 resistance R 11, the other end of described the 9th resistance R 9 is connected to respectively one end of described the 6th capacitor C 6 and the positive input terminal of the second operational amplifier 106, the other end ground connection of described the 6th capacitor C 6, described the second sample circuit 118 comprises: the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 5th transistor M5 and the 7th capacitor C 7, one end of described the 12 resistance R 12 is connected to the output of outside LC filter, the other end of described the 12 resistance R 12 is connected to respectively one end of described the 5th transistor M5, the 13 one end of resistance R 13 and one end of the 14 resistance R 14, the other end ground connection of described the 13 resistance R 13, the other end ground connection of described the 5th transistor M5, the grid of described the 5th transistor M5 is connected to the grid of outside the first transistor M1, the other end of described the 14 resistance R 14 is connected to respectively the positive input terminal of described the first operational amplifier 105 and one end of the 7th capacitor C 7, the other end ground connection of described the 7th capacitor C 7.
As shown in Figure 4, the utility model is as follows for realizing the course of work of circuit of controllable silicon light modulation and High Power Factor: after sampling primary voltage VC2 and VC1, obtain the reference voltage V ref3 that system needs carrying out division arithmetic.In Fig. 4: the sample circuit that has been formed VC2 by the 9th resistance R 9, the tenth resistance R the 10, the 11 resistance R 11, the 6th capacitor C 6, this circuit role is low-pass filtering, the signal of sampling be prime power switching tube M1 drain electrode voltage signal (be denoted as: Vdrain), its Output rusults is:
, wherein, k is constant herein,
for armature winding input voltage, N is the turn ratio of the main secondary winding of transformer,
for the output voltage at secondary LED two ends, d is for getting its a certain section after quadraturing.By the 12 resistance R the 12, the 13 resistance R the 13, the 14 resistance R 14, the 7th capacitor C 7 and the 5th transistor M5, it is the VC1 sample circuit that N-type field effect transistor M5 forms, this circuit role is copped wave, and the signal of sampling is that elementary input voltage signal (is denoted as V
in), its Output rusults is:
.The circuit function that the first operational amplifier 105, the 3rd transistor M3 and the 5th resistance R 5 form be to convert the voltage signal of chopper circuit output to current signal I
3, the circuit function that the second operational amplifier 106, the 4th transistor M4 and the 6th resistance R 6 form be to convert the voltage signal of low-pass filter circuit output to current signal I
4.Visible in figure, when the first interrupteur SW 1 and the 3rd interrupteur SW 3 conducting, second switch SW2 closes, and vice versa.First, when the first interrupteur SW 1 and the 3rd beginning SW3 conducting, when second switch SW2 closes, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
3copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
.
Wherein
for the gain of digital to analog converter, its value is subject to control from 0 to 255/256 variation of counter 104.
When the first interrupteur SW 1 and the 3rd interrupteur SW 3 are closed, second switch SW2 conducting, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
4copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
,
Here,
,
.
As Fig. 4, the peak current of prime power switching tube M1 forms feedback voltage by the 4th resistance R 4 of sampling and enters by CS port, after lead-edge-blanking circuit 115, compare with reference voltage V ref3, when this voltage is during higher than reference voltage V ref3, the high signal of the 3rd comparator 111 output is to the D port of the second trigger 112, the second trigger 112 output low signals drive 113 to grid, and grid drives 113 output low signals to close prime power switching tube M1.After the output voltage of assisting winding to sample is by the second resistance R 2 and the 3rd resistance R 3 dividing potential drops, be input to DEMAG port, this voltage is by the 4th comparator 114 and reference voltage V ref4 comparison, when this voltage is during higher than reference voltage V ref4, the high signal of the 4th comparator 114 output is to the D port of the second trigger 112, the high signal of the second trigger 112 output drives 113 to grid, grid drives the high signal of 113 output to open prime power switching tube M1, and each cycle goes round and begins again afterwards.Obtaining thus load LED average output current can be expressed as:
。
[the 3rd alternate embodiment] Fig. 5 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the 3rd alternate embodiment; this figure be only the utility model for realizing the first sample circuit 101 and 118 1 examples of the second sample circuit of the circuit of controllable silicon light modulation and High Power Factor, it does not limit the protection range of claim.In Fig. 5, described the first sample circuit 101 comprises: the tenth resistance R 10 and the 11 resistance R 11, one end of described the tenth resistance R 10 is connected to the output of outside LC filter, the other end of described the tenth resistance R 10 is connected to respectively one end of described the 11 resistance R 11 and the positive input terminal of the second operational amplifier 106, the other end ground connection of described the 11 resistance R 11, described the second sample circuit 118 comprises: the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 5th transistor M5 and the 7th capacitor C 7, one end of described the 12 resistance R 12 is connected to the output of outside LC filter, the other end of described the 12 resistance R 12 is connected to respectively one end of described the 5th transistor M5, the 13 one end of resistance R 13 and one end of the 14 resistance R 14, the other end ground connection of described the 13 resistance R 13, the other end ground connection of described the 5th transistor M5, the grid of described the 5th transistor M5 is connected to the grid of outside the first transistor M1, the other end of described the 14 resistance R 14 is connected to respectively the positive input terminal of described the first operational amplifier 105 and one end of the 7th capacitor C 7, the other end ground connection of described the 7th capacitor C 7.
As shown in Figure 5, the utility model is as follows for realizing the course of work of circuit of controllable silicon light modulation and High Power Factor: after sampling primary voltage VC2 and VC1, obtain the reference voltage V ref3 that system needs carrying out division arithmetic.In Fig. 5: consisted of the sample circuit of VC2 the 9th resistance R 9 and the tenth resistance R 10, this circuit role is that dividing potential drop detects, the signal of sampling be elementary input voltage signal (be denoted as: Vin), its Output rusults is:
, wherein k is constant,
for armature winding input voltage.By the 12 resistance R the 12, the 13 resistance R the 13, the 14 resistance R 14, the 7th capacitor C 7 and the 5th transistor M5, it is the VC1 sample circuit that N-type field effect transistor M5 forms, this circuit role is copped wave, and the signal of sampling is that elementary input voltage signal (is denoted as V
in), its Output rusults is:
.The circuit function that the first operational amplifier 105, the 3rd transistor M3 and the 5th resistance R 5 form be to convert the voltage signal of chopper circuit output to current signal I
3, the circuit function that the second operational amplifier 106, the 4th transistor M4 and the 6th resistance R 6 form be to convert the voltage signal of voltage-dividing detection circuit output to current signal I
4.Visible in figure, when the first interrupteur SW 1 and the 3rd interrupteur SW 3 conducting, second switch SW2 closes, and vice versa.First, when the first interrupteur SW 1 and the 3rd beginning SW3 conducting, when second switch SW2 closes, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
3copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
Wherein
for the gain of digital to analog converter, its value is subject to control from 0 to 255/256 variation of counter 104.
When the first interrupteur SW 1 and the 3rd interrupteur SW 3 are closed, second switch SW2 conducting, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
4copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
.
Here,
,
.
As Fig. 5, the peak current of prime power switching tube M1 forms feedback voltage by the 4th resistance R 4 of sampling and enters by CS port, after lead-edge-blanking circuit 115, compare with reference voltage V ref3, when this voltage is during higher than reference voltage V ref3, the high signal of the 3rd comparator 111 output is to the D port of the second trigger 112, the second trigger 112 output low signals drive 113 to grid, and grid drives 113 output low signals to close prime power switching tube M1.After the output voltage of assisting winding to sample is by the second resistance R 2 and the 3rd resistance R 3 dividing potential drops, be input to DEMAG port, this voltage is by the 4th comparator 114 and reference voltage V ref4 comparison, when this voltage is during higher than reference voltage V ref4, the high signal of the 4th comparator 114 output is to the D port of the second trigger 112, the high signal of the second trigger 112 output drives 113 to grid, grid drives the high signal of 113 output to open prime power switching tube M1, and each cycle goes round and begins again afterwards.Obtaining thus load LED average output current can be expressed as:
。
[the 4th alternate embodiment] Fig. 6 is the circuit diagram of the inverse-excitation type LED drive circuit based on former limit feedback that comprises the utility model the 4th alternate embodiment; this figure be only the utility model for realizing the first sample circuit 101 and 118 1 examples of the second sample circuit of the circuit of controllable silicon light modulation and High Power Factor, it does not limit the protection range of claim.In Fig. 6, described the first sample circuit 101 comprises: the 9th resistance R 9, the tenth resistance R 10, the 11 resistance R 11, the 5th transistor M5, the 6th capacitor C 6 and the second inverter, one end of described the tenth resistance R 10 is connected to the drain electrode of outside the first transistor M1, the other end of described the tenth resistance R 10 is connected to respectively one end of described the 11 resistance R 11 and one end of the 9th resistance R 9, the other end ground connection of described the 11 resistance R 11, the other end of described the 9th resistance R 9 is connected to one end of described the 5th transistor M5, the other end of described the 5th transistor M5 is connected to respectively one end of described the 6th capacitor C 6 and the positive input terminal of described the second operational amplifier 106, the grid of described the 5th transistor M5 is connected to the output of described the second inverter, the input of described the second inverter is connected to the grid of outside the first transistor M1, the other end ground connection of described the 6th capacitor C 6, described the second sample circuit 118 comprises: the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14 and the 7th capacitor C 7, one end of described the 12 resistance R 12 is connected to the drain electrode of outside the first transistor M1, the other end of described the 12 resistance R 12 connects respectively the 13 one end of resistance R 13 and one end of the 14 resistance R 14, the other end ground connection of described the 13 resistance R 13, the other end of described the 14 resistance R 14 is connected to respectively the positive input terminal of described the first operational amplifier 105 and one end of the 7th capacitor C 7, the other end ground connection of described the 7th capacitor C 7.
As shown in Figure 6, the utility model is as follows for realizing the course of work of circuit of controllable silicon light modulation and High Power Factor: after sampling primary voltage VC2 and VC1, obtain the reference voltage V ref3 that system needs carrying out division arithmetic.In Fig. 6: obtain the reference voltage V ref3 that system needs carrying out division arithmetic after sampling primary voltage VC2 and VC1.In Fig. 6: the sample circuit that has been formed VC2 by the 9th resistance R 9, the tenth resistance R the 10, the 11 resistance R 11, the 5th transistor M5, the 6th capacitor C 6 and the second inverter, this circuit role is envelope detected, the signal of sampling be prime power switching tube M1 drain electrode voltage signal (be denoted as: Vdrain), its Output rusults is:
, wherein k is constant,
for armature winding input voltage, N is the turn ratio of the main secondary winding of transformer,
output voltage for secondary LED two ends.The VC1 sample circuit being formed by the 12 resistance R the 12, the 13 resistance R the 13, the 14 resistance R 14 and the 7th capacitor C 7, this circuit role is low-pass filtering, the signal of sampling be prime power switching tube M1 drain electrode voltage signal (be denoted as: Vdrain), its Output rusults is:
, wherein k is constant,
for armature winding input voltage, N is the turn ratio of the main secondary winding of transformer,
output voltage for secondary LED two ends.The circuit function that the first operational amplifier 105, the 3rd transistor M3 and the 5th resistance R 5 form be to convert the voltage signal of low-pass filter circuit output to current signal I
3, the circuit function that the second operational amplifier 106, the 4th transistor M4 and the 6th resistance R 6 form be to convert the voltage signal of envelope detected circuit output to current signal I
4.Visible in figure, when the first interrupteur SW 1 and the 3rd interrupteur SW 3 conducting, second switch SW2 closes, and vice versa.First, when the first interrupteur SW 1 and the 3rd beginning SW3 conducting, when second switch SW2 closes, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
3copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
Wherein
for the gain of digital to analog converter, its value is subject to control from 0 to 255/256 variation of counter 104.
。
When the first interrupteur SW 1 and the 3rd interrupteur SW 3 are closed, second switch SW2 conducting, transistor seconds M2 is that P type field effect transistor M2 is by electric current I
4copy is to digital to analog converter 103, and the output current of digital to analog converter 103 is:
.
Here,
,
.
As Fig. 6, the peak current of prime power switching tube M1 forms feedback voltage by the 4th resistance R 4 of sampling and enters by CS port, after lead-edge-blanking circuit 115, compare with reference voltage V ref3, when this voltage is during higher than reference voltage V ref3, the high signal of the 3rd comparator 111 output is to the D port of the second trigger 112, the second trigger 112 output low signals drive 113 to grid, and grid drives 113 output low signals to close prime power switching tube M1.After the output voltage of assisting winding to sample is by the second resistance R 2 and the 3rd resistance R 3 dividing potential drops, be input to DEMAG port, this voltage is by the 4th comparator 114 and reference voltage V ref4 comparison, when this voltage is during higher than reference voltage V ref4, the high signal of the 4th comparator 114 output is to the D port of the second trigger 112, the high signal of the second trigger 112 output drives 113 to grid, grid drives the high signal of 113 output to open prime power switching tube M1, and each cycle goes round and begins again afterwards.Obtaining thus load LED average output current can be expressed as:
Known based on above analysis, compare with the existing inverse-excitation type LED drive circuit based on former limit feedback, adding described peak current reference generator module is that the utility model is for after realizing the circuit of controllable silicon light modulation and High Power Factor, as shown in Figure 2, the output of described rectifier bridge does not need the electric capacity that capacitance is larger to carry out filtering, the output Vin of described rectifier bridge follows the tracks of and exchanges input sine wave shape, can be expressed as:
Therefore, load LED average output current can be expressed as:
Wherein,
for load LED average output current, N is the turn ratio of the main secondary winding of transformer, I
pkfor peak primary currents.
The effect of the described peak current reference generator module in Fig. 2 is exactly sample VC1 and VC2 signal carry out division arithmetic, and the sampled voltage signal of the Vref3 signal after division arithmetic and switching tube current sampling resistor R4 compares, and object is to draw:
K is constant, draws like this:
From above-mentioned, can find: load LED average output current and output voltage and load are irrelevant, can obtain so good input voltage regulation and load regulation, realize output LED constant current and control.
By formula (3), elementary sample rate current can be expressed as:
If that VC2 sampling is the output signal Vin after rectifier, by formula (1) substitution formula (5), can be obtained:
Wherein,
for constant, by formula (6), find that elementary input current can be followed the tracks of and exchange input sine wave shape, can realize high power factor like this.
Suppose that controllable silicon dimmer can be from
arrive
adjust its Trigger Angle, formula (4) can obtain:
From formula (7), can find out that load LED average output current must be along with SCR Trigger Angle
variation and change, thereby can realize input controllable silicon light modulation.
In sum, at the existing inverse-excitation type LED drive circuit based on former limit feedback, add the utility model for after realizing the circuit of controllable silicon light modulation and High Power Factor, when having met good input voltage adjustment characteristic and adjustment of load characteristic, can show high power factor and controllable silicon light modulation.
More than, by description of listed embodiment, basic conception of the present utility model and basic principle have been set forth.But the utility model is never limited to above-mentioned listed execution mode, every equivalent variations of doing based on the technical solution of the utility model, improvement and deliberately become of inferior quality behavior, all should belong to protection range of the present utility model.
Claims (10)
1. for realizing a circuit for controllable silicon light modulation and High Power Factor, it is characterized in that, this circuit comprises: the first sample circuit (101), the second sample circuit (118), the first switch (SW1), described the first switch (SW1) comprises first grid, first terminal and the second terminal, second switch (SW2), described second switch (SW2) comprises second grid, third terminal and the 4th terminal, the 3rd switch (SW3), described the 3rd switch (SW3) comprises the 3rd grid, the 5th terminal and the 6th terminal, transistor seconds (M2), described transistor seconds (M2) comprises the 4th grid, the 7th terminal and the 8th terminal, the 3rd transistor (M3), described the 3rd transistor (M3) comprises the 5th grid, the 9th terminal and the tenth terminal, the 4th transistor (M4), described the 4th transistor (M4) comprises the 6th grid, the 11 terminal and the 12 terminal, digital to analog converter (103), counter (104), inverter (102), the first operational amplifier (105), the second operational amplifier (106), the 7th resistance (R7), the 5th electric capacity (C5), the first comparator (107), the first trigger (110), delay circuit (109), the 5th resistance (R5), the 6th resistance (R6), the 8th resistance (R8), the second comparator (108), wherein, after described the first sample circuit (101) sampling external voltage signal processing, be sent to the positive input terminal of described the second operational amplifier (106), the negative input end of described the second operational amplifier (106) is connected to described the 12 terminal, the output of described the second operational amplifier (106) is connected to described the 6th grid, after described the second sample circuit (118) sampling external voltage signal processing, be sent to the positive input terminal of described the first operational amplifier (105), the negative input end of described the first operational amplifier (105) is connected to described the tenth terminal, the output of described the first operational amplifier (105) is connected to described the 5th grid, described the 9th terminal is connected to described the second terminal, described the 11 terminal is connected to described the 4th terminal, described first terminal and third terminal are connected to described the 8th terminal after merging, described the 7th terminal receives externally fed voltage, described the 4th grid is connected to respectively described the 8th terminal and described digital to analog converter (103), described first grid is connected to respectively the input of described inverter (102), the non-end of Q of the 3rd grid and outside the second trigger (112), described second grid is connected to the output of described inverter (102), described the tenth terminal is connected to the positive input terminal of described the second comparator (108), described the tenth terminal and the 12 terminal are respectively by described the 5th resistance (R5) and the 6th resistance (R6) ground connection, described digital to analog converter (103) is connected to respectively described counter (104), one end of the 5th terminal and the 7th resistance (R7), the other end of described the 7th resistance (R7) is connected to respectively one end of the 8th resistance (R8) and the negative input end of outside the 3rd comparator (111), the other end ground connection of described the 8th resistance (R8), described the 6th terminal is connected to respectively one end of described the 5th electric capacity (C5) and the negative input end of the first comparator (107), the other end ground connection of described the 5th electric capacity (C5), the positive input terminal of described the first comparator (107) is connected to the first reference voltage (Vref1), the negative input end of described the second comparator (108) is connected to the second reference voltage (Vref2), described the first comparator (107) exports described the first trigger (110) to, the output of described the second comparator (108) is connected to respectively the CLK end of described counter (104) and one end of delay circuit (109), the D termination of described the first trigger (110) is received externally fed voltage, the non-end of Q of described the first trigger (110) is connected to the UP/DN end of described counter (104), the CLR end of described the first trigger (110) is connected to the other end of described delay circuit (109).
2. according to claim 1 for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, described the first sample circuit (101) comprising: the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11), the 5th transistor (M5), the 6th electric capacity (C6) and the second inverter, one end of described the tenth resistance (R10) is connected to the drain electrode of outside the first transistor (M1), the other end of described the tenth resistance (R10) is connected to respectively one end of described the 11 resistance (R11) and one end of the 9th resistance (R9), the other end ground connection of described the 11 resistance (R11), the other end of described the 9th resistance (R9) is connected to one end of described the 5th transistor (M5), the other end of described the 5th transistor (M5) is connected to respectively one end of described the 6th electric capacity (C6) and the positive input terminal of described the second operational amplifier (106), the grid of described the 5th transistor (M5) is connected to the output of described the second inverter, the input of described the second inverter is connected to the grid of outside the first transistor (M1), the other end ground connection of described the 6th electric capacity (C6), described the second sample circuit (118) comprising: the 12 resistance (R12) and the 13 resistance (R13), one end of described the 12 resistance (R12) is connected to the output of outside LC filter, the other end of described the 12 resistance (R12) is connected to respectively one end of positive input terminal and the 13 resistance (R13) of described the first operational amplifier (105), the other end ground connection of described the 13 resistance (R13).
3. according to claim 2ly for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, described the 5th transistor (M5) is N-type field effect transistor.
4. according to claim 1 for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, described the first sample circuit (101) comprising: the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11) and the 6th electric capacity (C6), one end of described the tenth resistance (R10) is connected to the drain electrode of outside the first transistor (M1), the other end of described the tenth resistance (R10) is connected to respectively one end of described the 11 resistance (R11) and one end of the 9th resistance (R9), the other end ground connection of described the 11 resistance (R11), the other end of described the 9th resistance (R9) is connected to respectively one end of described the 6th electric capacity (C6) and the positive input terminal of the second operational amplifier (106), the other end ground connection of described the 6th electric capacity (C6), described the second sample circuit (118) comprising: the 12 resistance (R12), the 13 resistance (R13), the 14 resistance (R14), the 5th transistor (M5) and the 7th electric capacity (C7), one end of described the 12 resistance (R12) is connected to the output of outside LC filter, the other end of described the 12 resistance (R12) is connected to respectively one end of described the 5th transistor (M5), the 13 one end of resistance (R13) and one end of the 14 resistance (R14), the other end ground connection of described the 13 resistance (R13), the other end ground connection of described the 5th transistor (M5), the grid of described the 5th transistor (M5) is connected to the grid of outside the first transistor (M1), the other end of described the 14 resistance (R14) is connected to respectively one end of positive input terminal and the 7th electric capacity (C7) of described the first operational amplifier (105), the other end ground connection of described the 7th electric capacity (C7).
5. according to claim 1 for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, described the first sample circuit (101) comprising: the tenth resistance (R10) and the 11 resistance (R11), one end of described the tenth resistance (R10) is connected to the output of outside LC filter, the other end of described the tenth resistance (R10) is connected to respectively one end of described the 11 resistance (R11) and the positive input terminal of the second operational amplifier (106), the other end ground connection of described the 11 resistance (R11), described the second sample circuit (118) comprising: the 12 resistance (R12), the 13 resistance (R13), the 14 resistance (R14), the 5th transistor (M5) and the 7th electric capacity (C7), one end of described the 12 resistance (R12) is connected to the output of outside LC filter, the other end of described the 12 resistance (R12) is connected to respectively one end of described the 5th transistor (M5), the 13 one end of resistance (R13) and one end of the 14 resistance (R14), the other end ground connection of described the 13 resistance (R13), the other end ground connection of described the 5th transistor (M5), the grid of described the 5th transistor (M5) is connected to the grid of outside the first transistor (M1), the other end of described the 14 resistance (R14) is connected to respectively one end of positive input terminal and the 7th electric capacity (C7) of described the first operational amplifier (105), the other end ground connection of described the 7th electric capacity (C7).
6. according to claim 1 for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, described the first sample circuit (101) comprising: the 9th resistance (R9), the tenth resistance (R10), the 11 resistance (R11), the 5th transistor (M5), the 6th electric capacity (C6) and the second inverter, one end of described the tenth resistance (R10) is connected to the drain electrode of outside the first transistor (M1), the other end of described the tenth resistance (R10) is connected to respectively one end of described the 11 resistance (R11) and one end of the 9th resistance (R9), the other end ground connection of described the 11 resistance (R11), the other end of described the 9th resistance (R9) is connected to one end of described the 5th transistor (M5), the other end of described the 5th transistor (M5) is connected to respectively one end of described the 6th electric capacity (C6) and the positive input terminal of described the second operational amplifier (106), the grid of described the 5th transistor (M5) is connected to the output of described the second inverter, the input of described the second inverter is connected to the grid of outside the first transistor (M1), the other end ground connection of described the 6th electric capacity (C6), described the second sample circuit (118) comprising: the 12 resistance (R12), the 13 resistance (R13), the 14 resistance (R14) and the 7th electric capacity (C7), one end of described the 12 resistance (R12) is connected to the drain electrode of outside the first transistor (M1), the other end of described the 12 resistance (R12) connects respectively the 13 one end of resistance (R13) and one end of the 14 resistance (R14), the other end ground connection of described the 13 resistance (R13), the other end of described the 14 resistance (R14) is connected to respectively one end of positive input terminal and the 7th electric capacity (C7) of described the first operational amplifier (105), the other end ground connection of described the 7th electric capacity (C7).
7. according to claim 1 for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, this circuit also comprises: critical conduction mode flyback constant-current control module, and this module comprises: the 3rd comparator (111), the second trigger (112), grid drive (113), the 4th comparator (114) and lead-edge-blanking circuit (115); wherein, the negative input end of described the 3rd comparator (111) is connected on the junction point of described the 7th resistance (R7) and the 8th resistance (R8), the positive input terminal of described the 3rd comparator (111) is connected to one end of described lead-edge-blanking circuit (115), the output of described the 3rd comparator (111) is connected to the D end of described the second trigger (112), the S end of described the second trigger (112) is connected to the output of described the 4th comparator (114), the Q end of described the second trigger (112) is connected to the input that described grid drives (113), the non-end of Q of described the second trigger (112) is connected to described first grid, the negative input end of described the 4th comparator (114) is for the voltage voltage division signal of the outside auxiliary winding of sampling, the positive input terminal of described the 4th comparator (114) receives the 4th reference voltage (Vref4), described grid drives the output of (113) to be connected to the grid of outside the first transistor (M1), the other end of described lead-edge-blanking circuit (115) is connected to the source electrode of described outside the first transistor (M1).
8. according to claim 7ly for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, this circuit also comprises: rectifier bridge; LC filter; Elementary absorbing circuit; The transformer being formed by armature winding, secondary winding and auxiliary winding; Be connected in the secondary circuit of described secondary winding; Be connected in the auxiliary power supply circuit of described auxiliary winding; The first transistor (M1); The 4th resistance (R4); Described rectifier bridge, LC filter, elementary absorbing circuit and transformer are connected in series successively, and the drain electrode of described the first transistor (M1) is connected to described armature winding, and the source electrode of described the first transistor (M1) is by the 4th resistance (R4) ground connection.
9. according to claim 8ly for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, this circuit also comprises: controllable silicon dimmer (117), described controllable silicon dimmer (117) is connected to the front end of described rectifier bridge.
10. according to claim 9ly for realizing the circuit of controllable silicon light modulation and High Power Factor, it is characterized in that, this circuit also comprises: AC power (116), described AC power (116) is connected to the front end of described controllable silicon dimmer (117).
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| CN201320540247.3U CN203467027U (en) | 2013-09-02 | 2013-09-02 | Circuit used for realizing controllable silicon dimming and high power factor |
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|---|---|---|---|
| CN201320540247.3U CN203467027U (en) | 2013-09-02 | 2013-09-02 | Circuit used for realizing controllable silicon dimming and high power factor |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103415128A (en) * | 2013-09-02 | 2013-11-27 | 陈畅 | Circuit for realizing controllable silicon dimming and high-power factor |
| CN109475029A (en) * | 2018-12-18 | 2019-03-15 | 深圳市稳先微电子有限公司 | Dimming driving circuit, light modulation driving chip and the control circuit of LED light |
| CN111383433A (en) * | 2019-11-08 | 2020-07-07 | 浙江凯耀照明有限责任公司 | Two-wire non-polarity half-duplex communication and power supply circuit |
-
2013
- 2013-09-02 CN CN201320540247.3U patent/CN203467027U/en not_active Withdrawn - After Issue
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103415128A (en) * | 2013-09-02 | 2013-11-27 | 陈畅 | Circuit for realizing controllable silicon dimming and high-power factor |
| CN109475029A (en) * | 2018-12-18 | 2019-03-15 | 深圳市稳先微电子有限公司 | Dimming driving circuit, light modulation driving chip and the control circuit of LED light |
| CN111383433A (en) * | 2019-11-08 | 2020-07-07 | 浙江凯耀照明有限责任公司 | Two-wire non-polarity half-duplex communication and power supply circuit |
| CN111383433B (en) * | 2019-11-08 | 2021-09-21 | 浙江凯耀照明有限责任公司 | Two-wire non-polarity half-duplex communication and power supply circuit |
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