CN203466849U

CN203466849U - IPv4 and IPv6 dual stack conversion device

Info

Publication number: CN203466849U
Application number: CN201320607336.5U
Authority: CN
Inventors: 卞晓光; 程国辉; 张升伟; 毕波; 金元文; 赵霓; 李素智; 林志超
Original assignee: Liaoning Planning And Designing Institute Of Posts And Telecommunication Co Ltd
Current assignee: Liaoning Planning And Designing Institute Of Posts And Telecommunication Co Ltd
Priority date: 2013-09-30
Filing date: 2013-09-30
Publication date: 2014-03-05
Anticipated expiration: 2023-09-30

Abstract

An IPv4 and IPv6 dual stack conversion device belongs to the technical field of telecommunication equipment manufacture. The IPv4 and IPv6 dual stack conversion device is composed of a microprocessor, a read-only memory, a read-write memory, a clock circuit, an Ethernet adaption chip, a serial port controller and a field bus adapter chip, wherein the microprocessor is connected with the read-only memory, the read-write memory, the clock circuit, the Ethernet adaption chip, the serial port controller and the field bus adapter chip. Subscriber identity and protocol stack conversion script contents are stored in the read-only memory; after being started, the microprocessor reads configuration script and identification information, then transmits data through an internet access, where a chip is configured, of the device, and carries out unpacking and analyzing on the data and protocol messages, and the real-time interactive data is processed through the address line and the data line of the read-write memory. The Ethernet adaption chip and the field bus adapter chip provide communication ports and support a CAN2.0B network protocol, so that the requirement of the microprocessor communication protocol is met. The IPv4 and IPv6 dual stack conversion device helps to solve the problem that end office network equipment does not support an IPv6 protocol stack; and the loading speed is fast.

Description

The two stack conversion equipments of IPv4 and IPv6

Technical field:

The utility model belongs to telecommunication apparatus manufacturing technology field, is a kind of conversion equipment of transfer of data.

Background technology:

And traditional IPv4/IPv6 protocol stack realize to need the main storage of a particular system, for storing the IP packet of wait-for-response, if once overtimely can recall data packet retransmission from storage.The solution of conventional hardware is obviously unreasonable with the packet that main memory store is to be retransmitted.When system need to be retransmitted IP packet, if a system save data, rather than the combination of bag itself, just do not need a large amount of memory spaces, for storing the packet of not replying.Field-installed retransmission data bag, although increased the load of processor, has postponed the transmission time of packet, and performance and the functional requirement of system suitably reduce, to realize a balance between cost.All packets in embedded system all read in internal memory, then determine whether to delete also will to take the main memory of a large amount of preciousnesses.Therefore, take the mechanism that is applicable to, at one time, to determine whether that this packet is dropped, saved spent a large amount of system resource and the time of main storage read data packet.If the relative position of predefined frame each part in program, can carry out addressing, easily to improve access speed.

The main hardware platform of this scheme adopts 8 or the microprocessor of 16 bit, in network facet, select more common network controller, aspect software, only need meet the function that network enabled connects and processes simple data, can take special-purpose embedded system.Although adopt 8/16 bit microprocessor framework to stablize in traditional scheme but lack autgmentability, disposal ability to aspects such as the flexible parsing of data pack protocol, analysis conversions is poor, aspect predefine protocol stack frame format, expending many time, time the be everlasting storage capacity of main storage make balanced with preliminary treatment link, this has also reduced entire system performance, cannot be in faster transmission speed, more developed and extensive use in the network of high-transmission quality requirement.

Summary of the invention:

The technical problems to be solved in the utility model is to disclose a kind of IPv4 and the two stack conversion equipments of IPv6.

The scheme of the utility model technical solution problem is to adopt microprocessor, read-only memory, read-write memory, clock circuit, the adaptive chip of Ethernet, serial ports controller and PROFIBUS interface chip form IPv4 and the two stack conversion equipments of IPv6, the Address of microprocessor and Data pin are connected respectively Address and the Data pin of read-only memory and read-write memory, clock circuit connects the ELTCLK of microprocessor, XTAL, EXTAL and RISC pin, the adaptive chip of Ethernet connects the PA0 of microprocessor, PA1, PD0 and PD1 pin, serial ports controller connects PC0 and the PC1 pin of microprocessor, PROFIBUS interface chip connects the RxD1 of microprocessor, TxD1, RxD2 and TxD2 pin, wherein microprocessor is MPC860, read-only memory is FLASH ROM, read-write memory is SDRAM, the adaptive chip of Ethernet is RTL8139, PROFIBUS interface chip is SJA1000.

User ID and protocol stack translation content for script are stored in read-only memory, and microprocessor reads configuration script and identification information by Address, Data pin after starting, and completes the original upload of functional module, and complete the storage of configuration item command unit; Microprocessor completes after original upload, by installing the network interface of configuring chip, transmits data and data, protocol massages are unpacked, resolved, and real-time, interactive data are processed by address wire and the data wire of read-write memory; To the more intense functional requirement of the splicing of data message, dismounting and real-time, need pass through external clock circuit extraction; The adaptive chip of Ethernet and PROFIBUS interface chip provide communication port and support the procotol of CAN2.0B, meet microprocessor communication protocol requirement.

The utility model is by the preliminary treatment to network exit turnover packet, adopt the mode of rapid deployment to complete the support to IPv4/v6 dual stack, improved the treatment effeciency of other network equipments, consider protocol stack and the opening of programming code and the modularization setting of hardware chip that hardware device is supported simultaneously, be convenient to secondary development and following distributed deployment growth requirement.

This device has carried out the test of operator's broad band bearing networking stage, reaches better effects, solves the problem that end office's network equipment is not supported IPv6 protocol stack; And in big customer's private network, complete pilot and dispose, having solved terminal Access Layer only supports IPv6 equipment cannot be incorporated to a difficult problem for private network, simultaneously by the opening of this device port, the rapid loading of protocol stack, high-speed packet forward (100Mpps level, scalable to 10Gpps level), the function such as network topology identification can meet more macroreticular scale and business demand, and predefine efficiency network link optimized algorithm provides hardware interface conversion and the enabling capabilities of the network equipment comparatively efficiently for following GreenNet development.

Accompanying drawing explanation:

Accompanying drawing 1 is the utility model electronics connection layout.

Embodiment:

The utility model is by microprocessor 1, read-only memory 2, read-write memory 3, clock circuit 4, the adaptive chip 5 of Ethernet, serial ports controller 6 and PROFIBUS interface chip 7 form, the Address of microprocessor 1 and Data pin are connected respectively Address and the Data pin of read-only memory 2 and read-write memory 3, clock circuit 4 connects the ELTCLK of microprocessor 1, XTAL, EXTAL and RISC pin, the adaptive chip 5 of Ethernet connects the PA0 of microprocessor 1, PA1, PD0 and PD1 pin, serial ports controller 6 connects PC0 and the PC1 pin of microprocessor 1, PROFIBUS interface chip 7 connects the RxD1 of microprocessor 1, TxD1, RxD2 and TxD2 pin, wherein microprocessor 1 is MPC860, read-only memory 2 is FLASH ROM, read-write memory 3 is SDRAM, the adaptive chip 5 of Ethernet is RTL8139, PROFIBUS interface chip 7 is SJA1000.

Claims

1. two stack conversion equipments of an IPv4 and IPv6, it is characterized in that: it is by adopting microprocessor, read-only memory, read-write memory, clock circuit, the adaptive chip of Ethernet, serial ports controller and PROFIBUS interface chip form, the Address of microprocessor and Data pin are connected respectively Address and the Data pin of read-only memory and read-write memory, clock circuit connects the ELTCLK of microprocessor, XTAL, EXTAL and RISC pin, the adaptive chip of Ethernet connects the PA0 of microprocessor, PA1, PD0 and PD1 pin, serial ports controller connects PC0 and the PC1 pin of microprocessor, PROFIBUS interface chip connects the RxD1 of microprocessor, TxD1, RxD2 and TxD2 pin.

2. according to claim 1 pair of stack conversion equipment, is characterized in that: microprocessor is MPC860, and read-only memory is FLASH ROM, and read-write memory is SDRAM, and the adaptive chip of Ethernet is RTL8139, and PROFIBUS interface chip is SJA1000.