CN203406795U - Neutral point clamp/H bridge five-level high-voltage frequency converter - Google Patents

Abstract

The utility model discloses a neutral point clamp/H bridge five-level high-voltage frequency converter which comprises a pre-charge circuit, a 18-way pulse transformer, a rectifier bridge, a five-level NPC/H-bridge unit, a pulse driving board, and a control panel, wherein the pre-charge circuit is connected with the five-level NPC/H-bridge unit through the18-way pulse transformer and the rectifier bridge, and the control panel is connected with the five-level NPC/H-bridge unit through the pulse driving board. A controller comprises an FPGA and a DSP. According to the utility model, the equivalent switching frequency of an inverter is low, the harmonic content of an output voltage is high, and the switching loss of the devices are serious under the condition that the switching frequencies of devices are the same. Moreover, the frequency converter can be expanded to an inverter at any level grade.

Description

A kind of neutral-point-clamped/H bridge five-level high-voltage frequency converter

Technical field

The utility model belongs to the technical field of high voltage converter, particularly, relates to a kind of neutral-point-clamped/H bridge (NPC/H) five-level high-voltage frequency converter.

background technology

Multi-level frequency conversion device is applied to the high pressure high-power transmission fields such as steel rolling, coal, railway, boats and ships, water conservancy more and more widely, and dv/dt is little for its voltage change ratio, and output voltage current harmonic content is low, and the voltage withstand class of device for power switching is low.The existing mesohigh big-power transducer three level NPC topological structures that adopt, its output phase voltage is three level progression more.In addition also there is H bridge cascade connection type topological structure, by cascade, can obtain different output-voltage levels progression.

Space voltage vector modulation method (Space Vector Pulse Width Modulation, SVPWM) be a kind of pulse-width modulation (Pulse Width Modulation of multi-electrical level inverter, PWM) control method, the realization of many level SVPWMs also has diverse ways.Conventionally adopt seven segmentation SVPWM, but the shortcoming of the method is: algorithm is complicated, and amount of calculation is large, needs the special heat dissipation problem of considering switching device.And in the situation that devices switch frequency is identical, the inverter equivalent switching frequency of this algorithm is low, harmonic wave of output voltage content is high, and devices switch loss is high.

utility model content

Because the above-mentioned defect of prior art, technical problem to be solved in the utility model is to provide a kind of neutral-point-clamped/H bridge (NPC/H) five-level high-voltage frequency converter, it is in the situation that devices switch frequency is identical, inverter equivalent switching frequency is low, harmonic wave of output voltage content is high, and devices switch loss is high; And can expand to the inverter of any level progression.

For achieving the above object, the utility model provides a kind of neutral-point-clamped/H bridge five-level high-voltage frequency converter, comprises pre-charge circuit ,18 road pulse transformer, rectifier bridge, five level NPC/H-bridge unit, pulsed drive plate and control board; Wherein, described pre-charge circuit is connected with described five level NPC/H-bridge unit with described rectifier bridge through described No. 18 pulse transformers, and described control board is connected with described five level NPC/H-bridge unit by described pulsed drive plate; Described controller comprises FPGA and DSP.

According to above-mentioned neutral-point-clamped/H bridge five-level high-voltage frequency converter, wherein, described five level NPC/H-bridge unit comprise DC side power supply and inverter circuit

Further, according to above-mentioned neutral-point-clamped/H bridge five-level high-voltage frequency converter, wherein, described DC side power supply consists of input side phase shifting transformer, rectifier and DC bus capacitor.

Further, according to above-mentioned neutral-point-clamped/H bridge five-level high-voltage frequency converter, wherein, described inverter circuit forms H bridge by two NPC brachium pontis, and each NPC brachium pontis consists of four IGBT and two diodes.

According to above-mentioned neutral-point-clamped/H bridge five-level high-voltage frequency converter, wherein, comprise 3 five level NPC/H-bridge unit.

Neutral-point-clamped/H bridge five-level high-voltage frequency converter according to above-mentioned, wherein, comprises 12 blocks of pulsed drive plates.

According to above-mentioned neutral-point-clamped/H bridge five-level high-voltage frequency converter, wherein, described DSP is for algorithm computing, and described FPGA is for generation of the IGBT in five level NPC/H-bridge unit described in pulse-triggered.

According to above-mentioned neutral-point-clamped/H bridge five-level high-voltage frequency converter, wherein, each pulsed drive plate is for triggering two IGBT of described five level NPC/H-bridge unit

Therefore, neutral-point-clamped/H bridge of the present utility model (NPC/H) five-level high-voltage frequency converter is in the situation that devices switch frequency is identical, and inverter equivalent switching frequency is low, and harmonic wave of output voltage content is high, and devices switch loss is high; And can expand to the inverter of any level progression.

Accompanying drawing explanation

Fig. 1 is the single-phase electrical structure diagram of five level neutral point clamp/H bridges in the utility model;

Fig. 2 is the electrical structure diagram of five level neutral point clamp/H bridge high voltage converters of the present utility model;

Fig. 3 is the system construction drawing of five level neutral point clamp/H bridge high voltage converters of the present utility model;

Fig. 4 is the flow chart of DSP algorithm in the utility model;

Fig. 5 is five-electrical level inverter I sector polar plot in the utility model;

Fig. 6 (a) is seven segmentation switching sequence figure in the utility model;

Fig. 6 (b) is syllogic switching sequence figure in the utility model;

Fig. 7 is that in the utility model, switching sequence produces rule figure;

Fig. 8 is the exemplary plot of syllogic switching sequence design in the utility model;

Fig. 9 is the drive waveforms figure of the device for power switching under balanced mode in the utility model;

Figure 10 is five level neutral point clamp/H bridge high voltage converter output phase voltage and line voltage oscillograms of the present utility model.

Embodiment

Below with reference to accompanying drawing, the technique effect of design of the present utility model, concrete structure and generation is described further, to understand fully the purpose of this utility model, feature and effect.

Figure 1 shows that the single-phase electrical structure diagram of five level neutral point clamp/H bridges in the utility model.Wherein, input side is electrical network, and outlet side is load motor.Input side phase shifting transformer charges to DC bus capacitor by rectifier, forms DC side power supply.Inverter circuit forms H bridge by two NPC brachium pontis, and each brachium pontis has four igbts (IGBT) and two diodes to form.Inverter circuit adopts SVPWM control strategy, controls the switching time of each igbt (IGBT), forms five level phase voltages.Correspondingly, three phase converter electrical structure diagram as shown in Figure 2.

Fig. 3 is the system construction drawing of five level neutral point clamp/H bridge high voltage converters of the present utility model, and it comprises that pre-charge circuit ,18 road pulse transformer, rectifier bridge, five level NPC/H-bridge unit, 12 pulsed drive plates, DSP+FPGA control boards form.Line voltage, after pre-charge circuit ，Jing No. 18 pulse transformers, obtains the DC voltage of five level NPC/H-bridge unit by rectifier bridge rectification, the driving signal that DSP+FPGA control board obtains is driven and triggered IGBT by 12 blocks of pulsed drive plates.Control system adopts DSP+FPGA structure, and wherein, DSP is responsible for algorithm computing, and concrete algorithm flow chart as shown in Figure 4.FPGA is responsible for producing pulse-triggered IGBT.Each drive plate triggers two IGBT, therefore needs altogether 12 blocks of pulsed drive plates.

General Definition reference voltage vector is:

V _ref＝V _refe ^jθ(1)

In formula (1), V _reffor voltage vector V _refmould value, the space angle that θ is reference voltage vector, in the utility model, five-electrical level inverter I sector polar plot as shown in Figure 5.So-called SVPWM method, removes to approach reference voltage vector V by the mean vector of inverter output phase voltage exactly _ref.

In order to simplify reference vector V _refthe calculating of synthetic and action time, utilize the angle between five level fundamental space vectors in alpha-beta plane to be this geometrical property of multiple of 60, adopt 60 ° of coordinate systems, i.e. g-h coordinate system.

As shown in Figure 5, as reference vector V _refwhile being arranged in triangle ABC, according to the on off state of triangular apex, distribute the switching sequence of SVPWM.As shown in Fig. 6 (a) and Fig. 6 (b), these on off states can be arranged and form seven segmentation switching sequences, for example: [2,1 respectively,-1] → [2,0 ,-1] → [1,0,-1] → [1,0 ,-2] → [1,0,-1] → [2,0 ,-1] → [2,1,-1], or syllogic switching sequence [2,1 ,-1] → [2,0 ,-1] → [1,0 ,-1].In order to reduce switching device switching frequency, switching sequence design has constraints: the change of on off state only relates to two switching devices of a brachium pontis, i.e. a break-over of device, another device cut-off.

Introduce the performing step of syllogic switching sequence below.The state-transition of considering two sampling periods, the switching sequence in first sampling period is [S _a1, S _b1, S _c1] → [S _a2, S _b2s _c2] → [S _a3, S _b3, S _c3], the switching sequence in second sampling period be [S ' _a1, S ' _b1, S ' _c1] → [S ' _a2, S ' _b2, S ' _c2] → [S ' _a3, S ' _b3, S ' _c3].When starting state of second switching sequence [S ' _a1, S ' _b1, S ' _c1] send out state [S with the end of first switching sequence _a3, S _b3, S _c3] when different, will there is Redundanter schalter state.In order to reduce on off state S ' _a1, s ' _b1, S ' _c1] and [S _a3, S _b3, S _c3] difference, must reduce Redundanter schalter state.For this reason, can be based on [S _a3, S _b3, S _c3] select neatly next starting state [S ' _a1, S ' _b1, S ' _c1].If known the end in previous sampling period, send out state [S _a3, S _b3, S _c3], syllogic switching sequence that just can flexible design, specific design step is as follows:

Step 1, select next starting state:

For on off state arbitrarily, define its on off state value and be:

$S=\underset{i=a,b,c}{\mathrm{\Σ}}{S}_i---\left(1\right)$

In addition, define the variation that two parameters are described switching sequence, on off state changes total amount Δ S and single-phase switch state variation value δ S:

$\mathrm{\ΔS}=\underset{i=a,b,c}{\mathrm{\Σ}}|S_{i1}^{\′}-S_{i3}^{\′}|---\left(2\right)$

$\mathrm{\δS}=\underset{i=a,b,c}{\max }|S_{i1}^{\′}-S_{i3}^{\′}|---\left(3\right)$

Then, starting state of second switching sequence can draw according to following principle:

1) find out all on off states in next triangle with minimum on off state variation total amount Δ S.This principle can effectively solve Redundanter schalter state.If contain more than one state, carry out so next step 2);

2) select to have the on off state of minimum single-phase switch state variation value δ S.Level progression when this principle can limit large voltage jump changes.Conventionally, starting vector can be calculated by above two steps.If also have unnecessary state, carry out so next step 3);

3) starting state of selecting to have minimum on off state value S completes algorithm.

Step 2, design switching sequence:

For for simplicity, each on off state value in a triangle according to descending successively label for 1. to 5..For example, on off state corresponding to tri-vectors of the A in Fig. 5, B and C, label is corresponding on off state [2,1 ,-1] 1., and label is corresponding on off state [1 ,-1 ,-2] 5..State value in same triangle is continuous integer, and such label is conducive to realize algorithm of the present utility model.

As shown in Figure 7, the straight line that contains round dot and arrow represents switching sequence, and round dot position represents starting state.Switching sequence draws according to starting state, and the straight line that contains arrow, through 3 on off states, forms syllogic switching sequence.In the triangle 10 of I sector, contain 5 kinds of switching sequences.Which as for select these 5 kinds of switching sequences, need to determine according to starting state.For example, if starting state label for 1., the label that switching sequence is corresponding so for 1. → 2. → 3., if starting state label for 4., the label that switching sequence is corresponding so for 4. → 3. → 2..

As shown in Figure 8, as reference vector V _refwhile rotating in the triangle of I sector, if each little triangle of outermost all has a sampled point, the syllogic switching sequence designing according to the utility model so can be expressed as:

△7：[2，-1，-1]→[2，-1，-2]→[2，-2，-2]

△6：[1，-2，-2]→[1，-1，-2]→[2，-1，-2]

△12：[2，-1，-2]→[2，0，-2]→[2，0，-1]

△11：[2，0，-1]→[2，0，-2]→[1，0，-2]

△15：[1，0，-2]→[2，0，-2]→[2，1，-2]

△14：[2，1，-2]→[2，1，-1]→[2，2，-1]

△16：[2，2，-1]→[2，2，-2]→[2，1，-2]

Can find out, when reference vector rotates on triangle border, not occur Redundanter schalter state.In addition, the change of the on off state in each employing cycle only has the variation of a level progression, i.e. each brachium pontis switching device conducting another switching device just ends.Meet the constraints of on off state.

Step 3, switching sequence decoding:

If regard on off state as digital coding, demodulator can be regarded as and converts digital coding to drive signal decoding table so.For example, if A is encoded to 2 mutually, decoded result is so: the switching device S in Fig. 1 _a13, S _a14, S _a21, S _a22conducting, the cut-off of rest switch device.

Decoding table is 5 kinds of possible digital coding-2, and-1,0,1 and 2 produce gate electrode drive signals.Digital coding-1,0,1 has different circuit states.Inappropriate decoding design may cause: 1) irrational voltage jump, and such as a brachium pontis jumps to-1 from 1, the variation that comprises two level progression, causes commutation failure and too high dv/dt; 2) uneven switching sequence pattern will cause switching device loss and heating imbalance.

Digital coding 1 and-1 correspondence two kinds of different circuit states, and digital coding 0 correspondence three kinds of different circuit states.The topological structure of five level NPC/H inverters always has 12 kinds of coding/decoding methods.Wherein there are 2 kinds of methods can meet constraints of the present utility model.Table 1 and table 2 represent respectively decoding table A and the decoding table B of A phase.The decoding table of B phase and C phase is mutually identical with A.V _noand V _xorepresent DC capacitor voltage E.For five level NPC/H inverters as shown in Figure 1, S _a=V _xo-V _no.

Table 1 five level NPC/H inverter decoding table A

Table 2 five level NPC/H inverter decoding table B

Can point out, because the angle of flow of the switching device of NPC type inverter is not identical, cause different conduction losses.Being used alternatingly these two kinds of coding/decoding methods can address these problems effectively.Emulation obtains the drive waveforms under two switching device balanced modes of A phase as shown in Figure 9, and every 2 first-harmonics alternately once.In addition, arrangement can make the switching frequency of switching device all identical like this.Therefore, switching loss can be evenly distributed to all switching devices.Figure 10 represents five level neutral point clamp/H bridge high voltage converter output phase voltage and line voltage oscillograms, and DC capacitor voltage is E, and frequency converter output phase voltage is five level, and amplitude is 2E; Line voltage is nine level, and its amplitude is 4E.

More than describe preferred embodiment of the present utility model in detail.The ordinary skill that should be appreciated that this area just can be made many modifications and variations according to design of the present utility model without creative work.Therefore, all technical staff in the art comply with design of the present utility model on the basis of existing technology by the available technical scheme of logical analysis, reasoning, or a limited experiment, all should be in the determined protection range by claims.

Claims (8)

1. neutral-point-clamped/H bridge five-level high-voltage frequency converter, its feature is, comprises pre-charge circuit ,18 road pulse transformer, rectifier bridge, five level NPC/H-bridge unit, pulsed drive plate and control board; Wherein, described pre-charge circuit is connected with described five level NPC/H-bridge unit with described rectifier bridge through described No. 18 pulse transformers, and described control board is connected with described five level NPC/H-bridge unit by described pulsed drive plate; Described controller comprises FPGA and DSP.

2. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 1, is characterized in that, wherein, described five level NPC/H-bridge unit comprise DC side power supply and inverter circuit.

3. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 2, is characterized in that, wherein, described DC side power supply consists of input side phase shifting transformer, rectifier and DC bus capacitor.

4. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 2, is characterized in that, wherein, described inverter circuit forms H bridge by two NPC brachium pontis, and each NPC brachium pontis consists of four IGBT and two diodes.

5. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 1, is characterized in that, comprises 3 five level NPC/H-bridge unit.

6. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 1, is characterized in that, comprises 12 blocks of pulsed drive plates.

7. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 1, is characterized in that, described DSP is for algorithm computing, and described FPGA is for generation of the IGBT in five level NPC/H-bridge unit described in pulse-triggered.

8. neutral-point-clamped/H bridge five-level high-voltage frequency converter according to claim 1, is characterized in that, each pulsed drive plate is for triggering two IGBT of described five level NPC/H-bridge unit.

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