CN203398119U - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN203398119U
CN203398119U CN201320118382.9U CN201320118382U CN203398119U CN 203398119 U CN203398119 U CN 203398119U CN 201320118382 U CN201320118382 U CN 201320118382U CN 203398119 U CN203398119 U CN 203398119U
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China
Prior art keywords
semiconductor chip
electrode
chip
contact area
semiconductor device
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CN201320118382.9U
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Chinese (zh)
Inventor
F.希尔勒
K.霍赛尼
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The utility model provides a semiconductor device, comprising a carrier including a chip island and lead wires; a semiconductor chip including a first electrode located on a first surface of the semiconductor chip and a second electrode located on a second surface, opposite to the first surface, of the semiconductor chip and electrically connected to the chip island; and a clamping piece including a first contact region and a second contact region, wherein the first contact region is disposed on the lead wires, the second contact region is disposed on the first electrode of the semiconductor, and the clamping piece further comprises projections in the second contact region and a transverse extension part extending out of the edge of the semiconductor chip in a direction parallel to the surface of the semiconductor chip.

Description

Semiconductor device
Technical field
The utility model relates to a kind of semiconductor device, especially, relates to a kind of encapsulation of semiconductor device.
Background technology
In power semiconductor field, a most important problem is the heat dissipation with the power device of vertical power load.The power requirement improving constantly that the reduction of chip size causes causes such device in the utilization energetically of the thermal site at chip surface place.Heating region is mainly at chip surface area place, and is interconnected to encapsulation outer lead.Do not having the continuous increase in these place, districts temperature of chip end face in enough cooling situations can affect the electric function of device, and in the worst case, can cause the damage at the chip active structure of these location.Especially, this problem for example can occur in, in the electronic device (super junction device) with complicated and sensitive structure, and super junction device has high current density load and for having the high-voltage applications of very fast switching time.
Therefore, the central theme of this respect is the special heat dissipation for this type of local pyrexia region in the chip mounting technique of super junction device and cooling, and super junction device has their hot formation zone in the epitaxial loayer at chip end face place.
In chip package technology, after chips incorporate, in these regions at end face place, be connected to encapsulation outer lead.For chip being connected to the common interconnection technique of package lead, be use aluminum lead combination or the welding of the diameter wire that is greater than 100 μ m or be bonded in the planar metallic structure between chip and package lead.But these interconnection techniques make the dissipation of heat have limitation to encapsulation outside, thereby the current density load of limiting device.
The difference design of existence in order to address this problem.In them one is based on using more than 500 μ m thicker diameter wire so that chip is connected to lead-in wire, and other schemes are used thicker interconnected metallic structures.But two schemes are all expensive, and have problems aspect putting into practice.
Utility model content
The purpose of this utility model is one or more in addressing the above problem.
Design of the present utility model is for example, at the metal contact area at intermediate plate adhering zone place and at chip edge, laterally to increase metal structure to increase the heat dissipation of encapsulation based on increasing metal structure (intermediate plate (clip)).
According to one side of the present utility model, semiconductor device is provided, comprising:
Carrier, it comprises chip island and lead-in wire;
Semiconductor chip, it comprises the second electrode on the second surface relative with first surface of the first electrode on semiconductor chip first surface and semiconductor chip, the second electrode is electrically connected to chip island; And
Intermediate plate, it comprises the first contact area and the second contact area, described the first contact area is placed on described lead-in wire, and described the second contact area is placed on described first electrode of described semiconductor chip, wherein, described intermediate plate also comprises the horizontal expansion portion that extends beyond the edge of described semiconductor chip in projection in described the second contact area direction parallel with surface with described semiconductor chip.
Preferably, described the second contact area is circular.
Preferably, described intermediate plate has hole in described the second contact area.
Preferably, described semiconductor chip also comprises the third electrode on the described first surface that is arranged in described semiconductor chip.
Preferably, described semiconductor chip is placed on described chip island, and the second electrode surface on described second surface is to described chip island.
Preferably, described semiconductor device is further included between the first contact area of described intermediate plate and described lead-in wire and the grafting material between the second contact area of described intermediate plate and the first electrode of described semiconductor chip.
Preferably, described semiconductor device is further included in the grafting material between the second electrode of described chip island and described semiconductor chip.
Preferably, described semiconductor device further comprises for encapsulating the encapsulating material of described semiconductor device.
Preferably, described semiconductor chip comprises super junction transistors.
Preferably, described semiconductor chip comprises compensating basin, and described compensating basin comprises p district and n district.
Preferably, described semiconductor chip is also included in the MOS transistor unit on described compensating basin.
Preferably, described semiconductor chip also comprises substrate and the resilient coating between described substrate and described compensating basin.
On the other hand, the utility model increases projection at vertical metal structure division in metallic plate, and at chip edge, increases the horizontal expansion part of metallic plate, especially, combines with super knot technology, especially has the contact area of circle substantially with optional hole.
be different fromplanar structure, the projection of metal structure (intermediate plate) and the design of horizontal expansion portion have increased metal structure to the contact surface of the welding region on chip end face.This additional surface with projection design has promoted heat dissipation from the end face of super knot.Except this effect, the metal structure of the horizontal expansion on described chip edge is made further contribution to the heat dissipation of described super junction device.
The additional vertical area of intermediate plate metal structure and the combination of transverse area that are welded on chip end face place make effective increase of the heat dissipation of super junction device become possibility.
In technological process, chip is attached to chip carrier through soft welding procedure or Diffusion Welding or conducting resinl, for example lead frame.After die attach technique, scolder by be dispensed on chip top side can welding region on, and be distributed on encapsulation outer lead top side.Next technique is that intermediate plate metal structure is placed on chip and package lead.Described intermediate plate metal structure is not only for chip electrode being electrically connected to encapsulation outer lead, and is the bridge to the heat dissipation of encapsulation outer lead for chip end face.Last technique is to use the device package of encapsulating material (for example moulding compound).
Meanwhile, we advise using less, circular contact area (being stamped in intermediate plate) to be to have being uniformly distributed of contact area on chip substantially.Hole can be stamped in described circular contact area further to reduce stress.
Accompanying drawing explanation
Accompanying drawing is included to provide the further understanding to embodiment, and is merged in and forms this specification part.Figure illustrates embodiment, and together with this description, is used for explaining the principle of embodiment.The expection advantage of other embodiment and many embodiment will easily be understood, because they become better understood by reference to the following specifically describes.The element of figure may not relative to each other be drawn in proportion.Identical Reference numeral is indicated corresponding similar portions.
Fig. 1 illustrates the schematic section of three non-limiting examples of super junction transistors.
Fig. 2 a-2b is the schematic diagram that illustrates three electrodes of super junction transistors.
Fig. 3 a-3c and 4 schematically illustrates the step of the method for manufacturing semiconductor device.
Fig. 5 schematically illustrates according to the sectional view of the semiconductor device that in Fig. 3 a-3c and 4, illustrated method forms.
Embodiment
In the following specifically describes, to being formed at this part of accompanying drawing, carry out reference, and in the accompanying drawings, by illustrated mode, show wherein and can put into practice specific embodiment of the present utility model.In this respect, with reference to (one or more) Tu orientation user of being described to term, such as " top ", " bottom ", " the ”,“ back side above ", " front ", " below " etc.Because the parts of embodiment can be positioned in a plurality of different azimuth, so direction term is used to illustrated object and restriction anything but.Should be understood that, can utilize other embodiment, and can in the situation that not deviating from scope of the present utility model, carry out change structural or in logic.The following specifically describes so will on limited significance, not carry out, and scope of the present utility model is defined by claims.
Should be understood that, the feature of various exemplary embodiments as herein described can combination with one another, unless indicated in addition particularly.
As adopted in this specification, term " coupling " and/or " electric coupling " do not mean that element must directly be coupled; Element may be provided between institute's " coupling " or " electric coupling " element between two parties.
Be described below the device that comprises one or more semiconductor chips.Semiconductor chip can have different types, can manufacture by different technology, and can comprise for example integrated circuit, photoelectric circuit or electromechanical circuits or passive device.Integrated circuit can for example be designed to logical integrated circuit, analog integrated circuit, composite signal integrated circuits, power integrated circuit, memory circuitry or integrated passive devices.In addition, semiconductor chip can be configured to so-called MEMS (MEMS (micro electro mechanical system)), and can comprise micro mechanical structure, such as electric bridge, film or tongue structure.Semiconductor chip can be configured to transducer or actuator, for example, and pressure sensor, acceleration transducer, rotation sensor, magnetic field sensor, emf sensor, microphone etc.Semiconductor chip do not need specially by semi-conducting material for example Si, SiC, SiGe, GaAs manufacture, can also comprise and not be semi-conductive inorganic and/or organic material, such as for example, insulator, plastics or metal.And, semiconductor chip can be encapsulation or not encapsulation.
Especially, can relate to the semiconductor chip with vertical stratification, that is to say that semiconductor chip can manufacturedly make electric current in the direction on the main surface perpendicular to semiconductor chip, to flow.There is the semiconductor chip of vertical stratification on two main surface, that is to say on its end face and bottom surface and there is electrode.Especially, power semiconductor chip can have vertical stratification.Vertical power semiconductor chip can for example be configured to power MOSFET (mos field effect transistor), IGBT (igbt), JFET (junction gate fet), power bipolar transistor or power diode.By example, it is upper that the source electrode of power MOSFET and gate electrode can be positioned at a main surface, and the drain electrode of power MOSFET is disposed on another main surface.In addition, following device can comprise that integrated circuit is with the integrated circuit of power ratio control semiconductor chip.
Semiconductor chip can have electrode (or contact element or contact pad), and described electrode allows to electrically contact with the integrated circuit being included in semiconductor chip.Electrode can comprise the one or more metal levels that are applicable to semi-conducting material.Metal level can be manufactured with any desired geometry and any desired material composition.The metal level layer that for example form is overlay area.Any desired metal or metal alloy, for example, aluminium, titanium, gold, silver, copper, palladium, platinum, nickel, chromium or nickel vanadium can be used as described material.Metal level do not need for homogeneity or by a kind of material only, manufactured, that is to say, various compositions and the concentration of the material comprising in metal level are possible.
Semiconductor chip can be placed on carrier.Carrier can be a part for lead frame or printed circuit board (PCB) (PCB) substrate, can have any shape, size and material.Lead frame can comprise chip island and lead-in wire.During the manufacture of device, chip island and lead-in wire can be connected to each other.Chip island and lead-in wire can also be made by one.Chip island and lead-in wire can be connected to each other by jockey, like this can be in manufacture process some in separating chips island and lead-in wire.The separated of chip island and lead-in wire can be carried out by mechanical sawing, laser beam, cutting, punching press, grinding, etching or any other suitable method.Lead frame can conduct electricity.They can fully be manufactured by metal or metal alloy, and described metal and metal alloy be copper, copper alloy, iron nickel, aluminium, aluminium alloy, steel, stainless steel or other suitable materials particularly.Lead frame can with electric conducting material, for example copper, silver, iron nickel or nickel phosphorus be electroplated.The lead-in wire of lead frame can be for example crooked during manufacture in S shape mode.Printed circuit board base board can have the conductive pad that copper is connected in bottom side and top side.
One or more intermediate plates can be used in device, parts are electrically coupled to one another.For example, the electrode of semiconductor chip can be electrically coupled to external contact element, for example, is coupled to the lead-in wire of lead frame by intermediate plate.Each intermediate plate has at least two contact areas, is used for this intermediate plate to be attached at least two parts of device.Contact area comprises the projection of the parts extension being attached to towards intermediate plate.
The device the following describes comprises external contact element (or external contact pad or outside outer lead), and described external contact element can have any shape and size.External contact element can be from device external reference, and therefore can allow to electrically contact semiconductor chip from device outside.For this reason, can have can be from the external contact surface of device external reference for external contact element.In addition, external contact element can be heat conduction, and can be with acting on dissipate and to be produced by semiconductor chip hot heat sink.External contact element can consist of any desired electric conducting material, for example, the metal such as copper, aluminium or gold, metal alloy or conduction organic material, consist of.Some in external contact element can be chip island or the lead-in wires of lead frame.
Device can comprise encapsulating material, for example, covers the moulding material of at least part of parts of this device.Moulding material can be any suitable thermoplastic or thermosets.Various technology can be used uses this moulding material coating member, for example compression forming of described various technology, injection moulding, powder compacting or liquid molding.
Device can have the surface of installation.Surface is installed and can be used for device to be installed on another parts, described another parts are circuit board for example, as PCB (printed circuit board (PCB)).External contact element and particularly external contact surface can be placed in installs surface above, to allow that this device is electrically coupled to device, is mounted parts thereon.Solder deposition (such as soldered ball) or other suitable Connection Elements can be used to set up device and be mounted being electrically connected between parts thereon, particularly mechanical connection with this device.
Fig. 5 schematically illustrates according to the sectional view of the semiconductor device of embodiment of the present utility model.This semiconductor device comprises carrier 10, and described carrier 10 consists of at least one chip island 11 and one or more encapsulation outer lead 12.This semiconductor device further comprises semiconductor chip 15, and it has the first electrode 16 and the second electrode 17 (Fig. 2 a-2b).The first electrode is disposed on the first surface 19 of semiconductor chip 15, and the second electrode is disposed on the second surface 20 of semiconductor chip 15.Second surface 20 is relative with first surface 19.The metal structure (for example intermediate plate) 25 with the first contact area 26 and the second contact area 27 is placed and makes the first contact area 26 be placed on lead-in wire 12 tops, and the second contact area 27 is placed on the first electrode top of semiconductor chip 15.Projection 28 is for example extended from the second contact area 27.
Preferably, metal structure 25 comprises horizontal expansion portion 29, to increase the heat dissipation of encapsulation.Horizontal expansion portion 29 extends beyond the metal structure 25 marginal portion at semiconductor chip 15 edge in the direction parallel with semiconductor chip surface.Horizontal expansion portion 29 can have any shape and size.
Alternatively, semiconductor chip 15 can have third electrode 18 (Fig. 2) on its first surface 19.In this case, the first and second electrodes are load electrodes, and third electrode is control electrode.Can between the third electrode of semiconductor chip 15 and additional lead-in wire, set up electrical interconnection.This interconnection can be made by wire bond.Alternatively, replace wire bond, additional intermediate plate can be placed on third electrode and additional lead-in wire.Additional intermediate plate can have the similar projection in its contact area of projection 28 with intermediate plate 25.
Carrier 10 can be manufactured by metal or metal alloy, and described metal or metal alloy is copper, copper alloy, iron nickel, aluminium, aluminium alloy or other electric conducting materials particularly.In one embodiment, carrier is lead frame, and lead frame 10 is by with electric conducting material, for example copper, silver, iron nickel or nickel phosphorus are electroplated.The shape of lead frame 10 is not limited to any size or geometry.Lead frame 10 can be manufactured by perforation, grinding or stamped sheet metal.
Semiconductor chip 15 can be configured to power transistor, for example, and power MOSFET, IGBT, JFET or power bipolar transistor or power diode.The in the situation that of power MOSFET or JFET, the first electrode is source electrode, and the second electrode is drain electrode, and third electrode is gate electrode.The in the situation that of IGBT, the first electrode is emission electrode, and the second electrode is collector electrode, and third electrode is gate electrode.The in the situation that of power bipolar transistor, the first electrode is emission electrode, and the second electrode is collector electrode, and third electrode is base electrode.The in the situation that of power diode, the first and second electrodes are negative electrode and anode, and do not have third electrode.
Semiconductor chip 15 uses grafting material 30 to connect by Diffusion Welding, soft soldering or conducting resinl is installed on chip island 11.
For example, for Diffusion Welding, scolder is for example deposited on the upper surface of the second electrode 17 or chip island 11 by sputter or other suitable physics or chemical deposition.Scolder can consist of AuSn, AgSn, CuSn, Sn, AuIn, AgIn, AuSi or CuIn.During diffusion technology for welding, scolder produces the metal bond between chip island 11 and semiconductor chip 15.
Use grafting material 31 connects by Diffusion Welding, soft soldering or conducting resinl is attached to intermediate plate 25 at the first electrode of lead-in wire 12 and semiconductor chip 15.
Fig. 5 also schematically illustrates the grafting material 31 at least part of first electrode of semiconductor chip 15 and the upper surface of lead-in wire 12 respectively.
For example, for Diffusion Welding, deposit solder after the solder joints between chip island 11 and semiconductor chip 15 forms.Scolder deposits by the technology that use is printed, distributed or any other is suitable.In one embodiment, scolder be deposited over respectively lead-in wire the 12 and first electrode contact area on (intermediate plate will be placed on here).In one embodiment, the first electrode of semiconductor chip 15 scribbles and allow to produce the nickel of solder joints or the layer of copper or any other metal or metal alloy in diffusion technology for welding.In addition, the layer of silver or gold or palladium or silver-colored billon or palladium-silver billon can be deposited on nickel dam or copper layer.The layer of silver or gold or palladium or silver-colored billon or palladium-silver billon can prevent nickel dam or the oxidation of copper layer.During diffusion technology for welding, scolder is between the first contact area 26 and lead-in wire 12 and produce metal bond between the second contact area 27 and the first electrode 16.
Intermediate plate 25 can be manufactured by metal or metal alloy, and described metal or metal alloy is copper, copper alloy, iron nickel or other electric conducting materials particularly.The shape of intermediate plate 25 is not limited to any size or geometry.Intermediate plate 25 can have as illustrated shape exemplarily in Fig. 5, but any other shape is also possible.Intermediate plate 25 is manufactured by punching press, perforation, extruding, cutting, sawing, grinding or any other suitable technology.The contact area 26,27 and the horizontal expansion portion that comprise projection 28 manufacture by punching press, perforation, etching or any other suitable technology.
The semiconductor chip of encapsulating material 52 package arrangement on carrier 10.According to embodiment, for example, part goes between and 12 can be uncovered.Again for example, segment chip island 11 can cover without encapsulating material 52, particularly the lower surface of chip island 11.Encapsulating material 52 can cover the top surface of intermediate plate 25 as illustrated in Figure 5.In one embodiment, the top surface of encapsulating material 52 can form plane with the top surface of intermediate plate 25.
Encapsulating material 52 can consist of any suitable thermoplastic or thermosets, and especially, this encapsulating material can be comprised of the material conventionally using in contemporary semiconductor packaging.Various technology can be used the parts of using encapsulating material 52 to carry out covering device, for example compression forming of described various technology, injection moulding, powder compacting or liquid molding.
Be apparent that for a person skilled in the art, described device is only exemplary embodiment, and many variations are possible.Although the device in Fig. 5 in illustrated embodiment comprises just what a semiconductor chip, this device can comprise two or more semiconductor chips and/or passive device.Semiconductor chip can be different at aspects such as function, size, manufacturing technologies with passive device.For example, semiconductor chip and/or other power semiconductor chip of control semiconductor chip 15 can be included in this device.
According to an embodiment, semiconductor chip 15 is configured to super junction transistors.Super junction device has the mobile semiconductor transistor of vertical current typically.This technology is based on comprising the alternately compensating basin in p-He n-district.Compensating basin is connected to the mosfet transistor unit that has source electrode and control grid.Drain electrode is in bottom surface and be highly doped substrate.Having heteroid resilient coating can be between compensating basin and substrate.
It should be understood that super junction transistors is only the example of semiconductor chip 15 and as mentioned above, semiconductor chip 15 is not limited to super junction transistors.
Fig. 1 illustrates the schematic section of three non-limiting examples of super junction transistors.Show for realizing the different possibilities in compensating basin and selectable buffer district.These examples are nonrestrictive, and can combine by any way.For simplicity, show the only cross section of a part for active area, the region of normal load electric current is carried in described active area.The part that transistorized for example edge termination system, break area or grid connect is not illustrated by explicitly in Fig. 1.Shown device has the semiconductor body that comprises compensating basin, and compensating basin comprises 130He n district, p district (p post) (n post) 134, wherein said compensation, and the difference of the doping between p-and n-post can be uniformly in vertical direction or change.
Compensating basin is connected to and comprises source electrode 118, tagma 138 and the MOS transistor unit of controlling grid 114.In shown example, grid is built as the planar gate electrodes on the top that is positioned at semiconductor body and passes through gate oxide 140Yu tagma electric insulation.Yet grid can also be implemented in the groove etching in semiconductor body.
Transistorized drain electrode 128 is connected to highly doped substrate 124.Optional resilient coating 126 can be between substrate and compensating basin.Resilient coating has the conduction type identical with substrate but has more low-doped.The doping of resilient coating can change in vertical direction.As example, the doped level of having described resilient coating in the cross section shown in Fig. 1 centre changes step by step.For example, resilient coating can comprise a plurality of sublayers, and as the first sublayer and the second sublayer, and the doping of the second sublayer is higher than the doping of the first sublayer.Be re-used as example, in the right-hand cross section illustrating of Fig. 1, having described being entrained in the direction from gate oxide 140 to resilient coating 126 of n district (n post) 134 little by little increases.
Metal layer 110 is electrically connected to source electrode contact, and it builds common source polar cushion at chip end face.Each cell gate 114 connects to be structured in end face by polysilicon to be had metallized public grid and contacts, so that have mono-, identical or different metallized two electrodes 16,18(for source electrode one for grid) be placed in device end face, and be isolated from each other by Si oxide and/or silicon nitride passivation layer.Drain electrode contact is structured in the device back side, and is used as metallization 128 coverings of the second electrode 17 of super junction device.
Fig. 2 a-2b illustrates the layout into the electrode of the super junction transistors of the example of semiconductor chip 15.Fig. 2 a illustrates the diagrammatic top view of super junction transistors, and Fig. 2 b illustrates the schematic section of super junction transistors, three electrode ，Ji source electrodes (the first electrode 16), drain electrode (the second electrode 17) and gate electrode (third electrode 18) are shown.
Fig. 3 a-3c and Fig. 4 schematically illustrate the embodiment of the method for illustrated semiconductor device in shop drawings 5.Wherein, super junction transistors is taken as the example of semiconductor chip 15.
First, provide lead frame, it comprises at least one chip island 11 and a plurality of encapsulation outer lead 12.The backplate of semiconductor chip 15 (the second electrode) is used welding compound or glue or Diffusion Welding and is attached on the chip island 11 of leadframe carrier, as shown in Fig. 3 a-3c.The thickness of grafting material 30 can be optimised, to better chip is coupled to lead frame additionally to improve electrical conductive behavior and heat conduction behavior.The end face electrode of semiconductor chip 15 (the first electrode or third electrode) comprises for being interconnected to the metal area of restriction of the outer lead 12 of lead frame.In upper surface Chu Gai metal area, by welding procedure or adhesion technique, being connected to lead frame by metal structure (intermediate plate) goes between.Meanwhile, Fig. 3 a also shows the partial cross section figure of the similar semiconductor chip 15 in the Yu Tu1 left side.
Jiang Chaojie back side chips incorporate is after carrier, and intermediate plate metal structure is interconnected to package lead by the chip end face that comprises the first electrode and third electrode (if yes), as shown in Figure 4.Thereby formed the electrical connection from chip to package outside.The joint of intermediate plate metal structure can connect or Diffusion Welding or conducting resinl realization through soft soldering.In order better chip to be coupled to metal intermediate plate additionally to improve electrical conductive behavior and heat conduction behavior, the thickness of optimizing grafting material 31 is important.Fig. 4 also shows the horizontal expansion portion that extends beyond the intermediate plate of semiconductor chip 15 in the parallel direction in the surface with semiconductor chip 15.
Next step after the combination of metal intermediate plate is the encapsulation of device.Moulding is by device package technique with protection electronic device in plastic material.Encapsulating material 52 is plasticity housing composition, non-conducting material, and it provides the insulation at encapsulation bottom surface and chip surface place electrode.As shown in Figure 5, the back side that plasticity housing component portion ground covers encapsulation is so that the heat management of product is better.
Lead-in wire 12, and especially, chip island 11 is as the external contact element of device, wherein, go between 12 and chip island 11 be coupled to respectively the first electrode, the second electrode and the optional third electrode of semiconductor chip 15.The part surface of lead-in wire 12 and the exposed surface of chip island 11 can be used as external contact surface, so that this device is electrically coupled to miscellaneous part, for example, circuit board (as PCB).
In addition, although may be with respect to only special characteristic or the aspect that discloses embodiment of the present utility model in several execution modes, but this category feature or aspect can combine with one or more other features or the aspect of other execution modes as can expecting, and are favourable for any given application or application-specific.In addition, at term, " comprise ", " having ", " having " or its other variants be used in specifically describe or the scope of claim in, this type of term is intended to for comprising " to contain " similarly mode with term.In addition, it should be understood that embodiment of the present utility model can use discrete circuit, partly integrated circuit or fully-integrated circuit or programmer to realize.Similarly, term " exemplary " only means as example, rather than preferably or best.It is also understood that, the feature described in this article and/or element are illustrated for simple and understandable order with specific dimensions relative to each other, and actual size can be different from illustrated size in this article widely.
Although in this article specific embodiment is illustrated and is described, but those of ordinary skill in the art will be appreciated that, in the situation that not deviating from scope of the present utility model, various interchangeable and/or equivalent execution modes can replace specific embodiment shown and that describe.The application is intended to be encompassed in any change or the variation of specific embodiment discussed herein.Therefore, be intended that, the utility model is only by claim and equivalents thereof.

Claims (12)

1. a semiconductor device, comprising:
Carrier, it comprises chip island and lead-in wire;
Semiconductor chip, it comprises the second electrode on the second surface relative with first surface of the first electrode on this semiconductor chip first surface and this semiconductor chip, the second electrode is electrically connected to chip island; And
Intermediate plate, it comprises the first contact area and the second contact area, described the first contact area is placed on described lead-in wire, described the second contact area is placed on described first electrode of described semiconductor chip, wherein, described intermediate plate also comprises the horizontal expansion portion that extends beyond the edge of described semiconductor chip in projection in described the second contact area direction parallel with surface with described semiconductor chip.
2. semiconductor device according to claim 1, wherein, described the second contact area is circular.
3. semiconductor device according to claim 1, wherein, described intermediate plate has hole in described the second contact area.
4. semiconductor device according to claim 1, wherein, described semiconductor chip also comprises the third electrode on the described first surface that is arranged in described semiconductor chip.
5. semiconductor device according to claim 1, wherein, described semiconductor chip is placed on described chip island, and the second electrode surface on described second surface is to described chip island.
6. semiconductor device according to claim 1, is further included between described first contact area of described intermediate plate and described lead-in wire and the grafting material between described second contact area of described intermediate plate and described first electrode of described semiconductor chip.
7. semiconductor device according to claim 1, is further included in the grafting material between described second electrode of described chip island and described semiconductor chip.
8. semiconductor device according to claim 1, wherein, further comprises for encapsulating the encapsulating material of described semiconductor chip.
9. according to the semiconductor device described in any one in claim 1-8, wherein, described semiconductor chip comprises super junction transistors.
10. semiconductor device according to claim 1, wherein, described semiconductor chip comprises compensating basin, described compensating basin comprises p district and n district.
11. semiconductor device according to claim 10, wherein, described semiconductor chip is also included in the MOS transistor unit on described compensating basin.
12. semiconductor device according to claim 11, wherein, described semiconductor chip also comprises substrate and the resilient coating between described substrate and described compensating basin.
CN201320118382.9U 2013-03-15 2013-03-15 Semiconductor device Expired - Lifetime CN203398119U (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410185A (en) * 2021-06-04 2021-09-17 深圳真茂佳半导体有限公司 Power semiconductor device packaging structure and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113410185A (en) * 2021-06-04 2021-09-17 深圳真茂佳半导体有限公司 Power semiconductor device packaging structure and manufacturing method thereof
CN113410185B (en) * 2021-06-04 2021-12-14 深圳真茂佳半导体有限公司 Power semiconductor device packaging structure and manufacturing method thereof

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