CN203377889U - Power detection system used for CDMA2000 and EVDO mixed signal - Google Patents
Power detection system used for CDMA2000 and EVDO mixed signal Download PDFInfo
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- CN203377889U CN203377889U CN201320435241.XU CN201320435241U CN203377889U CN 203377889 U CN203377889 U CN 203377889U CN 201320435241 U CN201320435241 U CN 201320435241U CN 203377889 U CN203377889 U CN 203377889U
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Abstract
The utility model discloses a power detection system used for a CDMA2000 and EVDO mixed signal comprising a radio frequency down-conversion device, a digitalization processing device, and a digital control device. The digital control device can be used to send a control command to control the radio frequency down-conversion device to carry out the down-conversion processing of the mixed signal in order to achieve an intermediate frequency signal. The digitalization processing device can be used to convert the intermediate frequency signal into the digital signal, and then can be used to carry out the related detection of the digital signal to determine a pilot frequency synchronization signal of an EVDO signal pilot frequency position in the mixed signal. Because of the full power emission of the EVDO carrier wave, the signal power of the pilot frequency position is the power of the carrier wave, and the calculated power of the mixed signal pilot frequency position is actually the real power emitted by the station, and at last, the sampling point of the signal power of the pilot frequency position can be determined according to the pilot frequency synchronization signal, and the power of the mixed signal pilot frequency position can be determined by accumulating the sampling point. By adopting the above mentioned technical scheme, the power detection of the CDMA2000 and EVDO mixed signal cannot be lower or fluctuated.
Description
Technical field
The utility model relates to the signal power detection field, particularly relates to the power detecting system of a kind of CDMA2000 and EVDO mixed signal.
Background technology
For directly putting, tower is put or base such as puts at the amplifier apparatus, can the power that detect accurately received base station signal be the prerequisite that can equipment bring into play maximum power amplification effect.Current CDMA(Code-Division Multiple Access, code division multiple access) generally all there is EVDO(Evolution-Data Optimized in 2000 base stations, evolution data optimization) situation that carrier wave and CDMA2000 carrier wave coexist, for the CDMA2000 carrier wave, because spread spectrum class signal power is comparatively steady, power detection is comparatively simple, and the signal of a period of time of need to adding up is averaging and gets final product; Because the forward link of EVDO system is time division multiplexing, a forward physical layer grouping can send at most 16 time slots, when time slot during in idle condition, only send MAC(Multiple Access Channel, multiple access access channel) channel and pilot channel, therefore actual transmit signal can along with business the number and cut in and out, this is for the detection of CDMA2000 system, the mode of accumulative total a period of time power averaging can cause actual power less than normal, when situation is serious, the equipment long-term work, in deeply starting to control state, causes equipment generation operation irregularity situation.
The power detecting system of general CDMA2000 and EVDO mixed signal, be mainly the power detection about base station signal, and prerequisite is at known carrier wave type and frequency, adopts the power-sensing circuit mode to complete the power of each carrier wave; Yet directly putting, tower is put or the base place system on, and do not know carrier type or frequency, so there is larger error in the mixed signal power detection.
The utility model content
Based on this, be necessary for existing CDMA2000 and the larger problem of EVDO mixed signal power detection error, a kind of testing result power detecting system of CDMA2000 and EVDO mixed signal comparatively accurately is provided.
The power detecting system of a kind of CDMA2000 and EVDO mixed signal comprises: radio frequency down-conversion device, digitizing treater, numerical control device;
Described radio frequency down-conversion device comprises gain control unit, phase locked-loop unit and converter unit, and described gain control unit is connected with described converter unit respectively with described phase locked-loop unit, and described phase locked-loop unit is connected with described numerical control device;
Described digitizing treater comprises AD conversion unit and digital signal processing unit, described AD conversion unit is connected with described converter unit, described digital signal processing unit and described numerical control device respectively, described digital signal processing unit is connected with described numerical control device, described digital signal processing unit is by described digital signal being carried out to the mode of coherent detection, the pilot tone synchronizing signal of determining carrier type and producing EVDO signal pilot position in described mixed signal;
Described numerical control device sends control command to described radio frequency down-conversion device and described digitizing treater, receives the data result of described radio frequency down-conversion device and described digitizing treater feedback.
The power detecting system of above-mentioned CDMA2000 and EVDO mixed signal, sending control command by numerical control device controls radio frequency down-conversion device and mixed signal is carried out to down-converted obtains intermediate-freuqncy signal, described digitizing treater converts described intermediate-freuqncy signal to digital signal, again described digital signal is carried out to coherent detection, determine the pilot tone synchronizing signal of EVDO signal pilot position in described mixed signal.Due to the emission of EVDO carrier wave full power, at the i.e. power of carrier wave for this reason of the signal power at pilot frequency locations place, therefore in fact the power that calculates mixed signal pilot frequency locations place be exactly the actual power that signal is sent in base station, finally according to described pilot tone synchronizing signal, determine the sampling number of pilot frequency locations place signal power, cumulative sampled point is determined the power at mixed signal pilot frequency locations place.This mode has overcome the problem of the power detection of CDMA2000 and EVDO mixed signal inaccurate and big rise and fall less than normal.
The accompanying drawing explanation
The power detecting system that Fig. 1 is CDMA2000 and EVDO mixed signal is the module connection layout of a kind of embodiment wherein;
Fig. 2 is that EVDO exists business and the structure of time slot figure during situation during without business;
The graph of a relation that Fig. 3 is PN biased exponent and PN pattern;
The FPGA inside testing process schematic diagram of a kind of embodiment wherein in the power detecting system that Fig. 4 is CDMA2000 and EVDO mixed signal;
The power detecting system that Fig. 5 is CDMA2000 and EVDO mixed signal is the module connection layout of another kind of embodiment wherein.
Embodiment
In a kind of embodiment therein, the power detecting system of a kind of CDMA2000 and EVDO mixed signal comprises: radio frequency down-conversion device 110, digitizing treater 120, numerical control device 130 as shown in Figure 1;
Described radio frequency down-conversion device 110 comprises gain control unit 112, phase locked-loop unit 114 and converter unit 116, described gain control unit 112 is connected with described converter unit 116 respectively with described phase locked-loop unit 114, and described phase locked-loop unit 114 is connected with described numerical control device 130.In the present embodiment, before described gain control unit 112 enters frequency-variable module for mixed signal, excessive for anti-stop signal, need to be controlled the power of input signal, it is input in the next stage circuit within the specific limits.Described phase locked-loop unit 114 is carried out frequency-conversion processing for the signal of controlling processing through overpower and the local oscillation signal that phase-locked loop produces, and signal is shifted on two different frequent points.Described numerical control device 130 can be configured and the transmission of control signal and the reception of result whole system by the MCU control chip.
Described digitizing treater 120 comprises AD conversion unit 122 and digital signal processing unit 124, described AD conversion unit 122 is connected with described converter unit 116, described digital signal processing unit 124 and described numerical control device 130 respectively, described digital signal processing unit is connected with described numerical control device, described digital signal processing unit 124 is by described digital signal being carried out to the mode of coherent detection, the pilot tone synchronizing signal of determining carrier type and producing EVDO signal pilot position in described mixed signal.Described digital signal processing unit 124, the digital signal obtained and a series of control signals that receive numerical control device 130, section produces testing circuit by the Hardware of algorithm within it, testing process is controlled by numerical control device 130, after detection completes, by bus, data are delivered to numerical control device 130.
Described numerical control device 130 sends control command to described radio frequency down-conversion device 110 and described digitizing treater 120, receives the data result of described radio frequency down-conversion device 110 and 120 feedbacks of described digitizing treater.
In the present embodiment, the frame structure of EVDO can be as shown in Figure 2, and the cycle of one frame is 26.67ms(32768 chip period), corresponding spreading rate is 1.2288Mchip/s, altogether by 32 half time slots, 16 time slots form.Proper polynomial for the PN sequence of EVDO carrier detect is:
P
I(x)=x
15+x
13+x
9+x
8+x
7+x
5+1
P
Q(x)=x
15+x
12+x
11+x
10+x
6+x
5+x
4+x
3+1
Corresponding generator polynomial is:
i(n)=i(n-15)⊕i(n-10)⊕i(n-9)⊕i(n-8)⊕i(n-7)⊕i(n-5)
q(n)=q(n-15)⊕q(n-12)⊕q(n-11)⊕q(n-10)⊕q(n-6)⊕q(n-5)⊕q(n-4)⊕q(n-3)
Wherein, symbol ⊕ means that mould 2 adds computing.The PN short code is 32768 chip lengths, with frequently between base station, utilizing PN sequence biased exponent to be distinguished, biased exponent has 512 kinds may, between base station, to differ be 64 integral multiple to the PN sequence, here choosing local PN sequence adopts and differs 64 chips and get final product, because pilot length in half time slot of EVDO is 96 chips, can be according to Fig. 3, choose the PN code that 16 an integral multiple continuous local PN combined sequence can capture carrier wave, peak value according to correlated results, not only can judge carrier type, can obtain the pilot tone synchronizing signal, be convenient to power calculation; For the CDMA2000 carrier wave, it is simple that this process is wanted, and because pilot channel exists always, the local PN sequence of choosing can intercept one section at random, and computational process is consistent.
For the ease of understanding, set forth in conjunction with specific embodiments, in the present embodiment, can set in advance local frequency is f
2, the specific implementation process of digital signal can be as follows: the radiofrequency signal received is that CDMA2000 and EVDO mixed signal are assumed to s (f after overpower is controlled
1), local frequency is f
2, after down-converted, signal is s (f
1-f
2) and s (f
1+ f
2), after mixing, signal is processed through low pass filter, filtering high fdrequency component s (f
1+ f
2), after filtering, signal is s (f
1-f
2), after amplifier, signal frequency point is constant, and amplitude increases, generating digital signal s (n) after ADC processes.
As shown in Figure 4, with FPGA(Field-Programmable Gate Array, i.e. field programmable gate array) device is example, performing step is: because the processing of primary link is all multiple operations, in order to save FPGA device inside resource, it is I/Q that I, Q are closed to road.S21 is the Digital Down Convert unit, by NCO(Numerical Controlled Oscillator, numerically-controlled oscillator) unit and complex multiplier two parts form, NCO(Direct Digital Synthesizer wherein, Direct Digital Synthesizer) unit is by common DDS module composition, DDS module frequency control word is channel number to be detected, and complex multiplier completes the calculating of complex signal and I/Q, and signal is I after setting up
1/ Q
1.The extraction processing unit that S22 is signal, suitably reduce the consumption that data sampling rate can effectively reduce resource, the extraction process of signal needs CIC (Cascaded Integrator – Comb, cascade integral-pectination) filter, FIR (Finite Impulse Response, limit for length's unit impulse response is arranged) shaping filter etc., data I after over-sampling
d/ Q
d.S23 is the signal power computing unit, and the length that the signal power counting period is chosen half time slot of EVDO gets final product, and, by half time slot decile repeatedly, maximum signal power is regarded as the power of this carrier wave, and the benefit of doing like this can prevent that signal power is less than normal; Power calculation realizes at first asking for I
d/ Q
damplitude, cumulative set time averaged obtains.
The power detecting system of above-mentioned CDMA2000 and EVDO mixed signal, sending control command by numerical control device controls radio frequency down-conversion device and mixed signal is carried out to down-converted obtains intermediate-freuqncy signal, described digitizing treater converts described intermediate-freuqncy signal to digital signal, again described digital signal is carried out to coherent detection, determine the pilot tone synchronizing signal of EVDO signal pilot position in described mixed signal.Due to the emission of EVDO carrier wave full power, at the i.e. power of carrier wave for this reason of the signal power at pilot frequency locations place, therefore in fact the power that calculates mixed signal pilot frequency locations place be exactly the actual power that signal is sent in base station, finally according to described pilot tone synchronizing signal, determine the sampling number of pilot frequency locations place signal power, cumulative sampled point is determined the power at mixed signal pilot frequency locations place.This mode has overcome the problem of the power detection of CDMA2000 and EVDO mixed signal inaccurate and big rise and fall less than normal.
In a kind of embodiment therein, the power detecting system of described CDMA2000 and EVDO mixed signal, described digital signal processing unit comprises local PN sequence interception module, multiple correlation computing module, signal judge module and the pilot tone synchronizing signal generation module connected successively.
As shown in Figure 4, in the present embodiment, described digital signal is carried out to coherent detection can be realized by local PN sequence memory cell and correlation operator, local PN sequence can be stored in the RAM of FPGA, after detecting beginning, according to external control signal, RAM regularly sends now relevant local PN sequence; Correlation operator is actual to be designed for matched filter, at first receive the local PN sequence (1) that RAM sends, the local PN sequence of take is added reducing to input signal as filter coefficient, the core cell that correlation operator is this part, because the sequence of calculation related to is long, need to consider the service condition of resource and the real-time processing of data, herein the relevant real-time output that adopts pile line operation to guarantee data, adopt the cycle accumulor mode in inner cumulative process, at each I simultaneously
d/ Q
ddata complete the inferior accumulated value of D (down-sampled multiple) in the cycle cumulative, and middle cumulative data can form by the memory cell of FPGA inside, after data are relevant, are I
c/ Q
c.After relevant, data still form for complex sequences, S25 mainly completes the amplitude of complex sequences and calculates, can adopt CORDIC(Coordinate Rotation Digital Computer, the rotation of coordinate numerical calculation method) algorithm completes amplitude and calculates, and supposes that amplitude is A (n).Complete the comparison of range value in S26 inside after having calculated amplitude, at first, according to the power calculation result, table look-up and export the threshold T h set
1, compare A (n) and Th in frame data
1size, if A (n)>Th
1judge and have carrier wave so.S26 is the synchronous pulse signal genration unit of EVDO pilot tone, when at EVDO, obtaining A (n in detection time
1) Th
1, so according to A (n
1) the moment, suitable time-delay can obtain the synchronizing pilot signal s of input signal
sync.Above S21～S26 all can complete in FPGA inside, and key is how to reduce the consumption of resource.
As shown in Figure 5, in a kind of embodiment therein, the power detecting system of described CDMA2000 and EVDO mixed signal, described digitizing treater 120 also comprises filter processing unit 126 and signal power amplifying unit 128; Described filter processing unit 126 is connected with described converter unit 116, and described signal power amplifying unit 128 is connected with described AD conversion unit 122 with described filter processing unit 126 respectively.
In the present embodiment, signal is through the moving of frequency spectrum, and what in fact need is in low frequency part, now adopts described intermediate-freuqncy signal is carried out to filtering to process and can leach this signal.Described intermediate-freuqncy signal after device, need to be carried out intermediate-freuqncy signal certain power amplification and process the input as digitized processing after filtering.
In a kind of embodiment therein, the power detecting system of described CDMA2000 and EVDO mixed signal, also comprise the unit that repeats of the power of determining at least two group mixed signal pilot frequency locations places the power that cumulative mean obtains final mixed signal pilot frequency locations place.In order to be the power that the power detection of CDMA2000 and EVDO mixed signal more accurately can be determined at least two group mixed signal pilot frequency locations places, cumulative mean obtains the power at final mixed signal pilot frequency locations place in the present embodiment.
The above embodiment has only expressed several execution mode of the present utility model, and it describes comparatively concrete and detailed, but can not therefore be interpreted as the restriction to the utility model the scope of the claims.It should be pointed out that for the person of ordinary skill of the art, without departing from the concept of the premise utility, can also make some distortion and improvement, these all belong to protection range of the present utility model.Therefore, the protection range of the utility model patent should be as the criterion with claims.
Claims (4)
1. the power detecting system of a CDMA2000 and EVDO mixed signal, is characterized in that, comprising: radio frequency down-conversion device, digitizing treater, numerical control device;
Described radio frequency down-conversion device comprises gain control unit, phase locked-loop unit and converter unit, and described gain control unit is connected with described converter unit respectively with described phase locked-loop unit, and described phase locked-loop unit is connected with described numerical control device;
Described digitizing treater comprises AD conversion unit and digital signal processing unit, described AD conversion unit is connected with described converter unit, described digital signal processing unit and described numerical control device respectively, described digital signal processing unit is connected with described numerical control device, described digital signal processing unit is by described digital signal being carried out to the mode of coherent detection, the pilot tone synchronizing signal of determining carrier type and producing EVDO signal pilot position in described mixed signal;
Described numerical control device sends control command to described radio frequency down-conversion device and described digitizing treater, receives the data result of described radio frequency down-conversion device and described digitizing treater feedback.
2. the power detecting system of CDMA2000 according to claim 1 and EVDO mixed signal, it is characterized in that, described digital signal processing unit comprises local PN sequence interception module, multiple correlation computing module, signal judge module and the pilot tone synchronizing signal generation module connected successively.
3. the power detecting system of CDMA2000 according to claim 1 and 2 and EVDO mixed signal, is characterized in that, described digitizing treater also comprises filter processing unit and signal power amplifying unit; Described filter processing unit is connected with described converter unit, and described signal power amplifying unit is connected with described AD conversion unit with described filter processing unit respectively.
4. the power detecting system of CDMA2000 according to claim 1 and 2 and EVDO mixed signal, it is characterized in that, also comprise the unit that repeats of the power of determining at least two group mixed signal pilot frequency locations places the power that cumulative mean obtains final mixed signal pilot frequency locations place.
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|---|---|---|---|
| CN201320435241.XU CN203377889U (en) | 2013-07-19 | 2013-07-19 | Power detection system used for CDMA2000 and EVDO mixed signal |
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| CN201320435241.XU CN203377889U (en) | 2013-07-19 | 2013-07-19 | Power detection system used for CDMA2000 and EVDO mixed signal |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103391140A (en) * | 2013-07-19 | 2013-11-13 | 京信通信系统（中国）有限公司 | Method and system for detecting power of CDMA (code-division multiple access) 2,000 and EVDO (evolution-data optimized) mixed signals |
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2013
- 2013-07-19 CN CN201320435241.XU patent/CN203377889U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103391140A (en) * | 2013-07-19 | 2013-11-13 | 京信通信系统（中国）有限公司 | Method and system for detecting power of CDMA (code-division multiple access) 2,000 and EVDO (evolution-data optimized) mixed signals |
| CN103391140B (en) * | 2013-07-19 | 2015-10-14 | 京信通信系统（中国）有限公司 | The power detecting method of CDMA2000 and EVDO mixed signal and system |
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Granted publication date: 20140101 Termination date: 20210719 |