CN203289393U - Key switch circuit with hardware delay function - Google Patents
Key switch circuit with hardware delay function Download PDFInfo
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- CN203289393U CN203289393U CN201320322049XU CN201320322049U CN203289393U CN 203289393 U CN203289393 U CN 203289393U CN 201320322049X U CN201320322049X U CN 201320322049XU CN 201320322049 U CN201320322049 U CN 201320322049U CN 203289393 U CN203289393 U CN 203289393U
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Abstract
The utility model discloses a key switch circuit with a hardware delay function, which comprises a key circuit, wherein the key circuit comprises a key SW1, wherein one end of the key SW1 is connected with an open end A, the other end is connected with one ends of a capacitor C1 and a resistor R1, the other end of the resistor R1 is connected with an open end B, and the other end of the capacitor C1 is grounded. The key circuit further comprises a resistor R2 and a capacitor C2, wherein one end of the resistor R2 is connected with the key SW1, the other end is connected with an IC_PIN pin, one end of the capacitor C2 is connected with the IC_PIN pin, and the other end is grounded. When the key is pressed, the capacitor C2 charges or discharges, voltage of the IC_PIN pin changes to a level state which can be identified by a corresponding IC_PIN gradually, and a certain period of time is required. When the key rises, the capacitor C2 charges or discharges, the voltage of the IC_PIN pin changes to a level state which can be identified by a corresponding IC_PIN gradually, and a certain period to time is also required. Therefore, during the process of pressing or raising the key SW1, the key delay circuit disclosed by the utility model can both provide a period of delay time, thereby enabling the key circuit to meet requirements.
Description
Technical field
The utility model relates to the key circuit technical field, relates in particular to a kind of key switch circuit with hardware delay function.
Background technology
Key circuit commonly used has two kinds, as shown in Figure 1, key circuit comprises button SW1, the end of described button SW1 is connected with the A end, the other end is connected with the end that capacitor C 1 is connected with resistance R respectively, the other end of described resistance R 1 is connected with the B end, the other end ground connection of described capacitor C 1, and wherein capacitor C 1 is anti-shake electric capacity.
Fixing power end and earth terminal are adopted in above-mentioned A end and B two ends, a kind of is A termination power end, B holds ground connection, and as shown in Figure 2, in the key circuit of this moment, the IC_PIN pin is connected with the end of button SW1 through current-limiting resistance R0, the default conditions of this key circuit are low level, SW1 presses when button, and the IC_PIN pin is by moving power supply on button SW1, and low level transfers high level to, SW1 lifts when button, and the IC_PIN pin is replied the default conditions low level.Another kind is A end ground connection, B holds power end, as shown in Figure 5, resistance R 1 in this kind key circuit is the pull-up resistor of IC_PIN pin, and the default conditions of key circuit are high level, and SW1 presses when button, IC_PIN pin ground connection, high level step-down level, SW1 lifts when button, and the IC_PIN pin is replied the default conditions high level.
Key circuit commonly used can be realized the function of button accurately, but at button, presses in process and there is no the hardware delay function.The application scenario of button hardware time delay demand is arranged, and key circuit commonly used is no longer satisfied the demand.
The utility model content
The purpose of this utility model is to provide a kind of circuit with key switch of hardware delay function, is intended to solve the problem that button is pressed in process does not have time delay.
for solving the problems of the technologies described above, the technical solution of the utility model is: a kind of key switch circuit with hardware delay function comprises key circuit, described key circuit comprises button SW1, the end of described button SW1 is connected with open end A end, the other end is connected with the end that capacitor C 1 is connected with resistance R respectively, the other end of described resistance R 1 is connected with open end B end, the other end ground connection of described capacitor C 1, also comprise that an end is connected with described button SW1, the resistance R 2 that the other end is connected with the IC_PIN pin, and one end be connected with the IC_PIN pin, the capacitor C 2 of other end ground connection.
Optimal way is, described open end A termination power, described open end B end ground connection.
Optimal way is, series resistor R0 between described resistance R 2 and described IC_PIN pin.
Optimal way is that open end A holds ground connection, open end B termination power.
after adopting technique scheme, the beneficial effects of the utility model are: because the key switch circuit with hardware delay function described in the utility model comprises key circuit, described key circuit comprises button SW1, the end of described button SW1 is connected with open end A end, the other end is connected with the end that capacitor C 1 is connected with resistance R respectively, the other end of described resistance R 1 is connected with open end B end, the other end ground connection of described capacitor C 1, also comprise that an end is connected with described button SW1, the resistance R 2 that the other end is connected with the IC_PIN pin, and one end be connected with the IC_PIN pin, the capacitor C 2 of other end ground connection.After button was pressed, capacitor C 2 discharged and recharged, and the IC_PIN pin voltage slowly changes to the level state of corresponding IC_PIN identification, needs the regular hour.After button lifted, capacitor C 2 was put charging, and the IC_PIN pin voltage slowly changes to the level state of corresponding IC_PIN identification, also needs the regular hour.Therefore in the process that button is pressed or lifted, button delay circuit described in the utility model all can provide a delay time, and key circuit is satisfied the demands; The open access mode is provided simultaneously, according to low level or high level, needs and at the open end side a and b, select access power supply or ground.
Description of drawings
Fig. 1 is the key circuit figure of background technology;
Fig. 2 is that the default conditions of background technology are low level key circuit figure;
Fig. 3 is the circuit diagram of the utility model embodiment one;
Fig. 4 is the circuit diagram of the utility model embodiment two;
Fig. 5 is that the default conditions of background technology are the key circuit figure of high level;
Fig. 6 is the circuit diagram of the utility model embodiment three;
Embodiment
, in order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explain the utility model, and be not used in restriction the utility model.
Embodiment one:
As shown in Figure 3, a kind of key switch circuit with hardware delay function, comprise key circuit, this key circuit comprises button SW1, and the end of this button SW1 is connected with open end A end, and the other end is connected with the end that capacitor C 1 is connected with resistance R respectively, the other end of resistance R 1 is connected with open end B end, the other end ground connection of capacitor C 1, also comprise the resistance R 2 that an end is connected with button SW1, the other end is connected with the IC_PIN pin, and an end is connected with the IC_PIN pin, the capacitor C 2 of other end ground connection.Select in the present embodiment: described open end A termination power VDD, described open end B end ground connection, make this open key switch circuit become a kind of low level key circuit.
Button SW1 presses, and C2 charges by R2, and IC_PIN pin (for the pin of integrated chip) voltage slowly rises to the high level time delay for some time of IC_PIN identification.Button SW1 lifts process, and C1 discharges by R1, and C2 discharges by R1+R2, the delay time that the low level of IC_PIN pin level arrival IC_PIN identification need to be longer.Wherein the value of resistance R 2 and C2 is determined as the case may be.
Embodiment two:
As shown in Figure 4, basic identical with embodiment one, difference is that the resistance R 2 use resistance R0 in this circuit replace or resistance R 0 and resistance R 2 series connection merging, on the basis of circuit shown in Figure 2, be connected the other end ground connection of capacitor C 2 with an end of capacitor C 2 at the IC_PIN pin.
Button SW1 presses, and C2 charges by R0, and the IC_PIN pin voltage slowly rises to the high level time delay for some time of IC_PIN identification.Button SW1 lifts process, and C1 discharges by R1, and C2 discharges by R1+R0, the delay time that the low level of IC_PIN pin level arrival IC_PIN identification need to be longer.The present embodiment further reduces costs, and simplifies circuit.
Embodiment three:
As shown in Figure 6, a kind of key switch circuit with hardware delay function comprises key circuit, described key circuit comprises button SW1, the end of described button SW1 is connected with open end A end, the other end is connected with the end that capacitor C 1 is connected with resistance R respectively, the other end of described resistance R 1 is connected the other end ground connection of described capacitor C 1 with open end B end, also comprise an end and the resistance R 2 that described button SW1 is connected, the other end is connected with the IC_PIN pin, and an end is connected with the IC_PIN pin, the capacitor C 2 of other end ground connection.Select in the present embodiment: described open end A termination ground connection, described open end B end power vd D, make this open key switch circuit become a kind of high level key circuit.
Button SW1 presses, and C2 discharges by R2, and IC_PIN pin voltage slow decreasing is to the low level time delay for some time of IC_PIN identification.Button SW1 lifts process, and C1 charges by R1, and C2 charges by R1+R2, the delay time that the low level of IC_PIN pin level arrival IC_PIN identification need to be longer.
In the above embodiments, the delay time that lifts with press of button SW1 is different.
The above preferred embodiment of the present utility model,, not in order to limit the utility model, all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (4)
1. key switch circuit with hardware delay function, it is characterized in that: comprise key circuit, described key circuit comprises button SW1, the end of described button SW1 is connected with open end A end, the other end is connected with the end that capacitor C 1 is connected with resistance R respectively, the other end of described resistance R 1 is connected with open end B end, the other end ground connection of described capacitor C 1, also comprise an end and the resistance R 2 that described button SW1 is connected, the other end is connected with the IC_PIN pin, and an end is connected with the IC_PIN pin, the capacitor C 2 of other end ground connection.
2. the key switch circuit with hardware delay function according to claim 1, is characterized in that: described open end A termination power, described open end B end ground connection.
3. the key switch circuit with hardware delay function according to claim 2, is characterized in that: series resistor R0 between described resistance R 2 and described IC_PIN pin.
4. the key switch circuit with hardware delay function according to claim 1, is characterized in that: described open end A end ground connection, open end B termination power.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320322049XU CN203289393U (en) | 2013-06-05 | 2013-06-05 | Key switch circuit with hardware delay function |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320322049XU CN203289393U (en) | 2013-06-05 | 2013-06-05 | Key switch circuit with hardware delay function |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203289393U true CN203289393U (en) | 2013-11-13 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320322049XU Expired - Lifetime CN203289393U (en) | 2013-06-05 | 2013-06-05 | Key switch circuit with hardware delay function |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203289393U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103281060A (en) * | 2013-06-05 | 2013-09-04 | 青岛歌尔声学科技有限公司 | Key switch circuit with hardware delay function |
| CN109038709A (en) * | 2018-07-12 | 2018-12-18 | 深圳拓邦股份有限公司 | A kind of identification circuit of key, method and blender |
| CN109755819A (en) * | 2019-01-31 | 2019-05-14 | 杭州电子科技大学 | A kind of intelligent socket hardware circuit based on ONENET cloud platform |
-
2013
- 2013-06-05 CN CN201320322049XU patent/CN203289393U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103281060A (en) * | 2013-06-05 | 2013-09-04 | 青岛歌尔声学科技有限公司 | Key switch circuit with hardware delay function |
| CN109038709A (en) * | 2018-07-12 | 2018-12-18 | 深圳拓邦股份有限公司 | A kind of identification circuit of key, method and blender |
| CN109755819A (en) * | 2019-01-31 | 2019-05-14 | 杭州电子科技大学 | A kind of intelligent socket hardware circuit based on ONENET cloud platform |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20131113 |