CN203287892U - External interface circuit of automatic test system - Google Patents

External interface circuit of automatic test system Download PDF

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Publication number
CN203287892U
CN203287892U CN2013203110377U CN201320311037U CN203287892U CN 203287892 U CN203287892 U CN 203287892U CN 2013203110377 U CN2013203110377 U CN 2013203110377U CN 201320311037 U CN201320311037 U CN 201320311037U CN 203287892 U CN203287892 U CN 203287892U
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CN
China
Prior art keywords
chip
interface
serial
test system
serial interface
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2013203110377U
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Chinese (zh)
Inventor
张家亮
刘奕
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHENGDU 30KAITIAN COMMUNICATION INDUSTRY Co Ltd
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CHENGDU 30KAITIAN COMMUNICATION INDUSTRY Co Ltd
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Priority to CN2013203110377U priority Critical patent/CN203287892U/en
Application granted granted Critical
Publication of CN203287892U publication Critical patent/CN203287892U/en
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Abstract

The utility model relates to an external interface circuit of an automatic test system. The external interface circuit of the automatic test system comprises a control processor, a serial interface chip, an RJ45 interface to serial interface chip, a cascading chip and a plurality of RJ45 interfaces, wherein the RJ45 interfaces are respectively connected with the RJ45 interface to serial interface chip through the cascading chip, the other ends of the RJ45 interfaces are connected with a tested client side, the RJ45 interface to serial interface chip is connected with the control processor through a bus, the control processor is connected with the serial interface chip through a bus, and the serial interface chip is connected with a test control terminal through a bus. According to the external interface circuit of the automatic test system, data are transmitted through the cascading RJ45 interfaces, and the test control terminal carries out cascading control on the tested client side; an RS485 serial communication interface chip is adopted in the serial interface chip, so the serial interface chip has good data driving capacity and ESD protection capacity; the interface signal level of an RS485 is lower than that of an RS323, therefore the chip of the interface circuit is not easily damaged, and the service life of the circuit is prolonged.

Description

Automatization test system external interface circuit
Technical field
The utility model relates to automatization test system external interface circuit.
Background technology
Automatic test is be converted into a kind of process that machine is carried out with the behavioral test that artificially drives.Traditional, after having designed test case and having passed through evaluation, carry out step by step test by the tester according to the rules of describing in test case, obtain the comparison of actual result and expected result, and automatic test, by machine, automatically performed, saved manpower, time or hardware resource, improved testing efficiency.
Interface circuit is the passage that test macro and outer computer carry out data transmission, is the important component part of test macro.Traditional test interface can only carry out limited data test, can't meet high request user's demand; In addition, adopt RS323 to carry out serial communication, easily damage the chip of interface circuit, and noise immunity is not strong.
The utility model content
The purpose of this utility model is to overcome the deficiencies in the prior art, the automatization test system external interface circuit that a kind of data-driven ability is strong, the ESD protective capacities is strong is provided, it carries out data transmission by the RJ45 interface of a plurality of cascades, has realized the cascade control of test control terminal to tested client.
the purpose of this utility model is achieved through the following technical solutions: automatization test system external interface circuit, it comprises control processor, serial interface chip, the RJ45 interface turns serial port chip, cascade chip and a plurality of RJ45 interface, a plurality of RJ45 interfaces turn serial port chip by cascade chip with the RJ45 interface respectively and are connected, the other end of RJ45 interface connects tested client, the RJ45 interface turns serial port chip and is connected with control processor by bus, control processor is connected with serial interface chip by bus, serial interface chip is by bus connecting test control terminal.
Further, described serial interface chip comprises RS485 serial communication interface chip.
The beneficial effects of the utility model are: the RJ45 interface by a plurality of cascades carries out data transmission, has realized the cascade control of test control terminal to tested client; Serial interface chip adopts RS485 serial communication interface chip, has good data-driven ability and ESD protective capacities; The interface signal level of RS485 is compared with RS323 and is decreased, thus the chip of fragile interface circuit not.
Description of drawings
Fig. 1 is structural representation block diagram of the present utility model.
Embodiment
Below in conjunction with accompanying drawing, the technical solution of the utility model is described in further detail, but protection domain of the present utility model is not limited to the following stated.
As shown in Figure 1, automatization test system external interface circuit, it comprises that control processor, serial interface chip, RJ45 interface turn serial port chip, cascade chip and a plurality of RJ45 interface, a plurality of RJ45 interfaces turn serial port chip by cascade chip with the RJ45 interface respectively and are connected, the other end of RJ45 interface connects tested client, the RJ45 interface turns serial port chip and is connected with control processor by bus, control processor is connected with serial interface chip by bus, and serial interface chip is by bus connecting test control terminal.
Further, described serial interface chip comprises RS485 serial communication interface chip.

Claims (2)

1. automatization test system external interface circuit, it is characterized in that: it comprises that control processor, serial interface chip, RJ45 interface turn serial port chip, cascade chip and a plurality of RJ45 interface, a plurality of RJ45 interfaces turn serial port chip by cascade chip with the RJ45 interface respectively and are connected, the other end of RJ45 interface connects tested client, the RJ45 interface turns serial port chip and is connected with control processor by bus, control processor is connected with serial interface chip by bus, and serial interface chip is by bus connecting test control terminal.
2. automatization test system external interface circuit according to claim 1, it is characterized in that: described serial interface chip comprises RS485 serial communication interface chip.
CN2013203110377U 2013-05-31 2013-05-31 External interface circuit of automatic test system Expired - Fee Related CN203287892U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2013203110377U CN203287892U (en) 2013-05-31 2013-05-31 External interface circuit of automatic test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2013203110377U CN203287892U (en) 2013-05-31 2013-05-31 External interface circuit of automatic test system

Publications (1)

Publication Number Publication Date
CN203287892U true CN203287892U (en) 2013-11-13

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN2013203110377U Expired - Fee Related CN203287892U (en) 2013-05-31 2013-05-31 External interface circuit of automatic test system

Country Status (1)

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CN (1) CN203287892U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106791826A (en) * 2017-03-02 2017-05-31 深圳创维-Rgb电子有限公司 A kind of test system, method and apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106791826A (en) * 2017-03-02 2017-05-31 深圳创维-Rgb电子有限公司 A kind of test system, method and apparatus

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Date Code Title Description
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20131113

Termination date: 20190531

CF01 Termination of patent right due to non-payment of annual fee