CN203275920U - Linear CCD data acquisition circuit with wireless data transmission function - Google Patents
Linear CCD data acquisition circuit with wireless data transmission function Download PDFInfo
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- CN203275920U CN203275920U CN 201320059853 CN201320059853U CN203275920U CN 203275920 U CN203275920 U CN 203275920U CN 201320059853 CN201320059853 CN 201320059853 CN 201320059853 U CN201320059853 U CN 201320059853U CN 203275920 U CN203275920 U CN 203275920U
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Abstract
The utility model discloses a linear CCD data acquisition circuit with a wireless data transmission function. The linear CCD data acquisition circuit is composed of a sequence signal output circuit, an analog signal amplification circuit, a USB interface circuit, an analog-digital conversion circuit and a wireless circuit. The sequence signal output circuit generates various sequence signals. The USB interface circuit stores parallel output signals, performs USB communication with a host computer in a USB mode, and performs serial communication with a CC2430 wireless singlechip microcontroller in a wireless mode. The singlechip microcontroller is controlled to change output clock frequency so as to change the output frequency of TCD1252AP or send the stored sampling data to CC2430. The analog-digital conversion circuit amplifies the output analog signal. The wireless circuit changes a clock signal output by the wireless circuit through serial communication. The linear CCD data acquisition circuit supports data transmission of USB2.0 protocol and the host computer, overcomes bottlenecks of an interface circuit in line with serial protocol standard, supports a wireless operating mode, sends out the data collected by a linear CCD timely, and thus is not limited by storage space of a linear array CCD data acquisition circuit system.
Description
Technical field
The utility model belongs to radio sensing network, analog-digital hybrid circuit design and embedded system circuit design field.
Background technology
The Linear Array CCD Data Acquisition circuit is the requisite electronic section of spectrometer, and therefore designing linear array ccd data Acquisition Circuit has very high practical value.
At present common Linear Array CCD Data Acquisition circuit has following deficiency: 1, the employing of the interface circuit of most Linear Array CCD Data Acquisition circuit and host computer meet RS ?the serial protocol chip of 232 standards, and the maximum baud rate that meets this standard of common singlechip chip support is only 115200 bps, transfer rate is lower, form difference with the high handling property of host computer, become the bottleneck of data transmission; 2, adopt the chip such as Flash as temporary storage spare in most Linear Array CCD Data Acquisition circuit, can be subjected to like this restriction of storage size.
Summary of the invention
The utility model provides a kind of Linear Array CCD Data Acquisition circuit, and this circuit is subjected to the deficiency of storage space limitations during the too low and independent image data of speed when also having overcome to the host computer the transmission of data except possessing the Linear Array CCD Data Acquisition function.
Realize that technical scheme of the present invention is:
The Linear Array CCD Data Acquisition circuit is comprised of clock signal output circuit and amplifying circuit of analog signal, usb circuit, analog to digital conversion circuit, radio-circuit.
The acp chip of sequential circuit be model be EPL7064SLC44 ?10 CPLD (CPLD), by the output clock of wireless singlechip CC2430 is counted produce drive required clock signal, the model of line array CCD device TCD1252AP be the USB chip operation of CY7C68013A ?128AC under SlaveFIFO (from genotype first in first out memory block, FIFO refers to the first in first out memory block) pattern clock signal and the sampled clock signal of modulus conversion chip AD9220.
The acp chip of usb circuit be model be CY7C68013A ?the USB chip of 128AC, be used for the parallel output signal of AD9920 is changed, stored and exports, if this circuit working is under the USB pattern, be packaged as the blocks of data transformat of usb protocol, then carry out usb communication with host computer; If this circuit working under wireless mode, carries out serial communication with the CC2430 wireless singlechip, control it and change the output clock frequency with the output frequency of change TCD1252AP or give CC2430 with the sampling data transmitting of storage.
The acp chip of analog to digital conversion circuit is modulus conversion chip AD8031, and the outputting analog signal of TCD1252AP is carried out anti-phase amplification, makes it to meet 0～5 volt of the convertible scope of AD9220.
The acp chip of radio-circuit is wireless chip CC2430, by serial communication change self export to EPL7064SLC44 ?10 clock signal, under wireless mode, receive CY7C68013A ?the sampled data of 128AC storage, and send by antenna.
The beneficial effects of the utility model:
The utility model designed complete Linear Array CCD Data Acquisition circuit, and chip and the electronic component of having selected each sub-circuits to adopt have provided detailed connected mode, effect and the mode of operation of clear and definite each chip and element.
The utility model supports USB2.0 agreement and host computer to carry out data transmission fully, upwards make the transfer rate of the interface circuit of Linear Array CCD Data Acquisition circuit and host computer satisfy the requirement of the high handling property of host computer fully, the data that the CCD sampling is obtained can in time be packed, thereby have overcome the bottleneck of the interface circuit that meets the serial protocol standard.
The utility model is supported wireless mode of operation fully, can the data that line array CCD collects in time be sent, thereby is not subjected to the restriction of the storage size of Linear Array CCD Data Acquisition Circuits System.
Description of drawings
Fig. 1 is TCD1252AP type line array CCD connecting circuit figure of the present utility model.
Fig. 2 is the connecting circuit figure of AD8031 of the present utility model.
Fig. 3 is jtag interface connecting circuit figure of the present utility model.
Fig. 4 be EPL7064SLC44 of the present utility model ?10 connecting circuit figure.
Fig. 5 be CY7C68013A of the present utility model ?the peripheral circuit diagram of 128AC.
Fig. 6 is the connecting circuit figure of USB interface of the present utility model.
Fig. 7 be CY7C68013A of the present utility model ?the connecting circuit figure of 128AC.
Fig. 8 is the connecting circuit figure of AD9220 of the present utility model.
Fig. 9 is filtering circuit figure of the present utility model.
Figure 10 is the filtering circuit figure of AD9220 of the present utility model.
Figure 11 is generation reference voltage circuit figure of the present utility model.
Figure 12 is LT1117 connecting circuit figure of the present utility model.
Figure 13 is radio-circuit part schematic diagram of the present utility model.
Embodiment
The present invention is described further below in conjunction with the drawings and specific embodiments.
Figure 1 ?Figure 13 be the Linear Array CCD Data Acquisition circuit diagram that has wireless data transmission function in the utility model, shown a kind of embodiment of the present utility model.
Fig. 1, Fig. 2, Fig. 3, Fig. 4 are required various clock signal output circuits and amplifying circuit of analog signal of generation Linear Array CCD Data Acquisition circuit of the present utility model.model be EPL7064SLC44 ?the counting clock pin 43 (seeing Fig. 4) of 10 CPLD chip connect the I/O output pin 11 (seeing Figure 13) of CC2430, pin 31, 33, 24, 19 produce the required a few road clock signal Fi1 (phase place 1) of driving TCD1252AP type line array CCD (Fig. 1), Fi2 (phase place 2), SH (shift gate), RS (restarting door), pin 5 produces the sampled clock signal of modulus conversion chip AD9220 (seeing Fig. 8), pin one, 44, 18, 37, 36 produce EZ ?the clock signal RESET (restart) of USB chip CY7C68013A (seeing Fig. 7) under the SlaveFIFO pattern, SLWREN (SlaveFIFO write-enable), SLWR (SlaveFIFO writes), FADDR1 (fifo address 1), FADDR0 (fifo address 0), PKTEND (packet end), be used for controlling the read-write of CY7C68013A FIFO, pin 32, 38, 13, 7 connect respectively the respective pins (seeing Fig. 3) on jtag interface, be used for EPL7064SLC44 ?the download of 10 programs.The output signal of line array CCD device TCD1252 is as the input signal of signal amplification chip AD8031, the output pin 7 of AD8031 and input pin 3 form reverse amplification circuit by resistance R _ f and R7, be used for input signal OS is amplified (seeing Fig. 2), pin two practice midwifery living reference voltage circuit reference voltage pin VIN ?(seeing Figure 11).
Fig. 5, Fig. 6, Fig. 7 are usb circuits of the present utility model.CY7C68013A ? 128AC 44, 45, 46, 47, 54, 55, 56, 57, 103, 104, 405 pins (seeing Fig. 7) connect respectively the BIT12 of modulus conversion chip AD9220 (seeing Fig. 8)～BIT1 pin, be used for reading the digital signal that AD9220 produces, pin one 01, 99 connect respectively and draw resistance R 2, R3, be used for guaranteeing that the level of these two pins can not dragged down and is waken up or restarts, pin 82 connect EPL7064SLC44 ?10 SH signal (seeing Fig. 4) for generation of interruption, pin 51, 52 connect respectively the pin one 3 of CC2430, 14, be used for carrying out with CC2430 the serial communication (seeing Figure 13) that software flow is controlled, pin one 8, 19 connect respectively pin 3 and the pin 2 (seeing Fig. 6) of USBHeder (USB interface), be used for carrying out usb communication with host computer.the pin 1 of USBHeader meets voltage transitions chip LT1117 (seeing Figure 12), be used for this circuit working and provide electric energy for whole circuit in the USB pattern, pin 36, 37, 101, 73 connect respectively CY7C68013A ?the resistance R 8 of peripheral circuit of 128AC, R9, R2, R1 (seeing Fig. 5), CY7C68013A ?the 128AC chip support USB2.0, maximum transmission rate is 480Mbps (MBPS) in theory, also can reach tens of Mbps during normal operation, therefore can satisfy the highest output frequency that TCD1252 and AD9220 combination can reach fully, do not make the data of generation become the bottleneck of Linear CCD data acquisition system to the transfer rate of host computer.
Fig. 8, Fig. 9, Figure 10, Figure 11, Figure 12 are analog to digital conversion circuits of the present utility model.modulus conversion chip AD9220 (seeing Fig. 8) pin one 8, 24 connect by capacitor C 15, the filtering circuit that C16 is formed in parallel, pin two 0, 21 connect respectively by C12, C13, CAPB end and the CAPT end (seeing Fig. 9) of the filtering circuit that C14 forms, pin one 8, 24 connect by C15, the filtering circuit of the AD9220 that C16 (seeing Figure 10) forms, the filtering circuit of AD9220, ground connection after the external filter capacitor C9 of pin two 2, the operating voltage input pin 15 of access AD9220 mimic channel after the voltage process C8 filtering of 5 volts, through E1, C10, the operating voltage input pin 28 of the digital circuit of access AD9220 after the filtering circuit that C11 forms, 17 of AD9220, 19, 25, the 27 direct ground connection of pin, the input pin of LT1117 (seeing Figure 12) connects the pin 1 of USBHeader (seeing Fig. 6), output pin is used as 3.3 volts of outputs after meeting filter capacitor E3.
Figure 13 is radio-circuit part of the present utility model.RED is the red LED pilot lamp, LED is green indicating lamp, and crystal oscillator Y1, Y2 are used to the CC2430 wireless singlechip that clock is provided, and forms radio transmitter by L100, L101, L102, C112 and PCR (emitting antenna), under the CC2430 peak power, wireless transmission distance can reach 200 meters.Pin one 3,14 is used for and CY7C68013A ?128AC carries out the serial communication that software flow is controlled, following two effects are arranged: 1. with resolve host computer issue CY7C68013A ?the control command of 128AC, thereby change the frequency of the CLK (output clock) of pin one 1 output, finally reach the purpose that changes the TCD1252 output frequency; 2. when this circuit working at wireless mode the time, be used for receiving CY7C68013A ?the sampled data of 128AC storage, and finally send with wireless form.Pin two 8,29,30,31,35,36,37,38,39,40 connects ground connection after the filtering circuit that is comprised of filter capacitor C102 and C103, pin 42,47 connects ground connection after the filtering circuit that is comprised of C121 and C134, and pin two 3,24 connects respectively ground connection after C134, C135.Pin one 0 connects and draws resistance R 100, can not be restarted to guarantee CC2430.
Obviously, above-described embodiment of the present utility model is only for the utility model example clearly is described, and is not to be restriction to embodiment of the present utility model.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here need not also can't give all embodiments exhaustive.And these belong to apparent variation or the change that connotation of the present utility model extends out and still belong to protection domain of the present utility model.
Claims (5)
1. Linear Array CCD Data Acquisition circuit, it is characterized in that, it comprises the clock signal output circuit, amplifying circuit of analog signal, analog to digital conversion circuit, usb circuit and radio-circuit, the acp chip of sequential circuit is that model is the CPLD of EPL7064SLC44-10, by the output clock of wireless singlechip CC2430 being counted to produce the required clock signal of driving line array CCD device TCD1252AP, model is that the USB chip operation of CY7C68013A-128AC is at the clock signal under the pattern of genotype first in first out memory block and the sampled clock signal of modulus conversion chip AD9220, the acp chip of usb circuit is that model is the USB chip of CY7C68013A-128AC, be used for the parallel output signal of AD9920 is changed, stored and exports, if this circuit working is under the USB pattern, be packaged as the blocks of data transformat of usb protocol, then carry out usb communication with host computer, when this circuit working was under wireless mode, CY7C68013A-128AC and CC2430 wireless singlechip carried out serial communication, controlled it and changed the output clock frequency with the output frequency of change TCD1252AP or give CC2430 with the sampling data transmitting of storage, the acp chip of analog to digital conversion circuit is modulus conversion chip AD8031, and the outputting analog signal of TCD1252AP is carried out anti-phase amplification, makes it to meet the convertible scope 0-5 volt of AD9220, the acp chip of radio-circuit is wireless chip CC2430, changes the clock signal of self exporting to EPL7064SLC44-10 by serial communication, under wireless mode, receives the sampled data of CY7C68013A-128AC storage, and sends by antenna.
2. Linear Array CCD Data Acquisition circuit according to claim 1, it is characterized in that, described model is the CPLD chip of EPL7064SLC44-10, its counting clock pin 43 connects the I/O output pin 11 of CC2430, pin 31, 33, 24, 19 produce required clock signal phase place 1 Fi1 of driving TCD1252AP type line array CCD, phase place 2 Fi2, shift gate SH, restart a RS, the pin 5 of CPLD chip produces the sampled clock signal of modulus conversion chip AD9220, pin one, 44, 18, 37, 36 produce EZ-USB chip CY7C68013A restarts RESET at the clock signal under the pattern of genotype first in first out memory block, SlaveFIFO write-enable SLWREN, SlaveFIFO writes SLWR, fifo address FADDR1 and FADDR0, packet finishes PKTEND, be used for controlling the read-write of CY7C68013A FIFO, pin 32, 38, 13, 7 connect respectively the respective pins on jtag interface, be used for the download of EPL7064SLC44-10 program, the output signal of line array CCD device TCD1252 is as the input signal of signal amplification chip AD8031, the output pin 7 of AD8031 and input pin 3 form reverse amplification circuit by resistance R _ f and R7, be used for input signal OS is amplified, pin two meets reference voltage pin VIN-.
3. Linear Array CCD Data Acquisition circuit according to claim 1, it is characterized in that, described usb circuit, 44 of CY7C68013A-128AC, 45, 46, 47, 54, 55, 56, 57, 103, 104, 405 pins connect respectively the BIT12-BIT1 pin of modulus conversion chip AD9220, be used for reading the digital signal that AD9220 produces, pin one 01, 99 connect respectively and draw resistance R 2, R3, be used for guaranteeing that the level of these two pins can not dragged down and is waken up or restarts, pin 82 connects the SH signal of EPL7064SLC44-10 for generation of interruption, pin 51, 52 connect respectively the pin one 3 of CC2430, 14, be used for carrying out with CC2430 the serial communication that software flow is controlled, pin one 8, 19 connect respectively pin 3 and the pin 2 of USB interface, be used for carrying out usb communication with host computer, the pin 1 of USB interface meets voltage transitions chip LT1117, be used for this circuit working in the USB pattern for whole circuit provides electric energy, the CY7C68013A-128AC chip is supported USB2.0.
4. Linear Array CCD Data Acquisition circuit according to claim 1, it is characterized in that, described analog to digital conversion circuit, modulus conversion chip AD9220 pin one 8, 24 connect by capacitor C 15, the filtering circuit that C16 is formed in parallel, pin two 0, 21 connect respectively by C12, C13, the CAPB end of the filtering circuit that C14 forms and CAPT end, ground connection after the external filter capacitor C9 of pin two 2, the operating voltage input pin 15 of access AD9220 mimic channel after the voltage process C8 filtering of 5 volts, through E1, C10, the operating voltage input pin 28 of the digital circuit of access AD9220 after the filtering circuit that C11 forms, 17 of AD9220, 19, 25, the 27 direct ground connection of pin, the input pin of LT1117 connects the pin 1 of USBHeader, output pin is used as 3.3 volts of outputs after meeting filter capacitor E3.
5. Linear Array CCD Data Acquisition circuit according to claim 1, it is characterized in that, described radio-circuit, RED is the red LED pilot lamp, LED is green indicating lamp, crystal oscillator Y1, Y2 is used to the CC2430 wireless singlechip that clock is provided, by L100, L101, L102, C112 and emitting antenna PCR form radio transmitter, pin one 3, 14 are used for carrying out with CY7C68013A-128AC the serial communication that software flow is controlled, following two effects are arranged: the control command of 1) issuing CY7C68013A-128AC to resolve host computer, thereby change the frequency of the clock of pin one 1 output, finally reach the purpose that changes the TCD1252 output frequency, 2) when this circuit working at wireless mode the time, be used for receiving the sampled data of CY7C68013A-128AC storage, and finally send with wireless form, pin two 8,29,30,31,35,36,37,38,39,40 connects ground connection after the filtering circuit that is comprised of filter capacitor C102 and C103, pin 42,47 connects ground connection after the filtering circuit that is comprised of C121 and C134, and pin two 3,24 connects respectively ground connection after C134, C135, pin one 0 connects and draws resistance R 100, can not be restarted to guarantee CC2430.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320059853 CN203275920U (en) | 2013-01-30 | 2013-01-30 | Linear CCD data acquisition circuit with wireless data transmission function |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320059853 CN203275920U (en) | 2013-01-30 | 2013-01-30 | Linear CCD data acquisition circuit with wireless data transmission function |
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| CN203275920U true CN203275920U (en) | 2013-11-06 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106645042A (en) * | 2017-01-12 | 2017-05-10 | 中国电子科技集团公司第四十四研究所 | CCD-based original position analyzer control method |
| CN105160176B (en) * | 2015-09-01 | 2018-03-27 | 华北电力大学（保定） | A kind of device and its monitoring method of the capacitor on-line monitoring based on wireless sensing |
-
2013
- 2013-01-30 CN CN 201320059853 patent/CN203275920U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105160176B (en) * | 2015-09-01 | 2018-03-27 | 华北电力大学（保定） | A kind of device and its monitoring method of the capacitor on-line monitoring based on wireless sensing |
| CN106645042A (en) * | 2017-01-12 | 2017-05-10 | 中国电子科技集团公司第四十四研究所 | CCD-based original position analyzer control method |
| CN106645042B (en) * | 2017-01-12 | 2019-03-22 | 中国电子科技集团公司第四十四研究所 | The control method of in-situ analyzer based on CCD |
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| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20131106 Termination date: 20140130 |