CN203217312U - Apparatus for simulating speed output - Google Patents
Apparatus for simulating speed output Download PDFInfo
- Publication number
- CN203217312U CN203217312U CN 201320229047 CN201320229047U CN203217312U CN 203217312 U CN203217312 U CN 203217312U CN 201320229047 CN201320229047 CN 201320229047 CN 201320229047 U CN201320229047 U CN 201320229047U CN 203217312 U CN203217312 U CN 203217312U
- Authority
- CN
- China
- Prior art keywords
- output
- processor
- driver
- speed
- analog rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Management, Administration, Business Operations System, And Electronic Commerce (AREA)
Abstract
The utility model is an apparatus and method for simulating speed output. The apparatus is composed of a first processor, a second processor, a BCD code conversion 7-section code converter, a gate array nixie tube address decoder, a nixie tube display, a first driver, a second driver, an I/O output interface module, an LED lamp, and a speed output mode selector switch. The speed output mode selector switch is connected with the first processor; an output terminal of the first processor is respectively connected with an input terminal of the first driver, an input terminal of the second driver, an input terminal of the BCD code conversion 7-section code converter, and input terminal of the gate array nixie tube address decoder; an output terminal of the first driver is connected with an input terminal of the I/O output interface module; an output terminal of the second driver is connected with the LED lamp; an output terminal of the BCD code conversion 7- section code converter and an output terminal of the gate array nixie tube address decoder are connected to the nixie tube display. Each two I/O units form a pair of signal outputs; and the second processor is used to employ an interruption mode to output a standard timing pulse signal, thereby reliably ensuring the speed precision.
Description
Technical field
The utility model relates to electronic technology field, is specifically related to a kind of device of analog rate output.
Background technology
Current intelligent transportation and electronic police product industry are in an extremely short time and develop in the stage rapidly.Just because of this reason, so relative later stage production and on-the-spot Installation and Debugging all lack effective instrument and means and guarantee the product produced and the quality of engineering.Lacking necessary application specific standard signal source debugs and tests.And at present for the sector, do not have instrument and the means of effective production and field adjustable yet.
In existing production and field adjustable, major part all is to finish the function debugging of minority with some simple indigenous methods.As the manual annular coil board of simulation or drive various motor vehicles and replace etc. of: self-control.Its fundamental purpose is exactly in the system debug process, provides to system that some simply have, no random signal.The method can not produce unified standard or continual and steady signal source, does not satisfy consistent, repeated signal output demand.These class methods are to satisfy and to guarantee progress and the quality of subsequent product production, installation.Do not have unified standard and reference device, provide effective reference data foundation for referencial use can not for production and field staff.
Therefore, in the work of reality, existing indigenous method is given to produce with the scene and has been brought many inconvenience and hard work.Particularly can't guarantee the product quality produced, also debugging has brought very big problem and hidden danger to fielded system.
Summary of the invention
At the deficiencies in the prior art, the utility model provides a kind of device of analog rate output, is used for the speed output of motor-driven vehicle going on the simulated roadway.
Technical solutions of the utility model are:
A kind of device of analog rate output comprises that first processor, second processor, binary-coded decimal change 7 segment encode converters, gate array charactron address decoder, charactron display, first driver, second driver, I/O output interface module, LED lamp, speed output mode selector switch;
Speed output mode selector switch connects first processor, the output terminal of first processor connects the input end of first driver respectively, the input end of second driver, binary-coded decimal changes the input end of 7 segment encode converters and the input end of gate array charactron address decoder, first output end of driver connects the input end of I/O output interface module, second output end of driver connects the LED lamp, binary-coded decimal changes the output terminal of 7 segment encode converters and the output terminal of gate array charactron address decoder all is connected to the charactron display, and the output terminal of second processor connects the input end of first processor.
Described first processor connects first reset circuit and first oscillatory circuit respectively.
Described second processor connects second reset circuit and second oscillatory circuit respectively.
Described speed output mode selector switch is the device for the output mode of the speed of selection, and the output mode of speed comprises fixing fast output mode and continuously variable speed output mode.
Described first processor is for the device by the toroidal signal of the process of the motor vehicle on its I/O port simulated roadway.
Described second processor is for adopting interrupt mode that the device of standard time clock pulse signal is provided to first processor.
The device of described analog rate output is made integrated circuit board by the 3U physical dimension, can insert in the 3U standard industry cabinet.
The step that the device that adopts described analog rate to export carries out analog rate output is as follows:
Step 1: first processor is with the whole zero clearings of the level of I/O port, and the level that is about to each I/O port is set to low level, and the timing of setting speed output and the speed of selection output mode, all LED lamps is all closed go out;
Every pair of I/O port of first processor constitutes a pair of analog rate output signal, namely simulates a motor vehicle on the track through two toroid windings, and every pair of I/O port signal is modeled to two toroidal rate signal outputs of the constant spacing on the track;
Step 2: the level of the port I/O1 of first processor is put high level, vehicle on the simulated roadway is through first toroid winding, this moment, this level signal exported its corresponding I/O output interface module to through first driver, and controlled its corresponding LED lamp and light;
Step 3: second processor provides standard clock signal to first processor, first processor with it as the timer counter least unit, when the first processor timer counter reaches timing, the level of I/O2 port that then will be adjacent with the I/O1 port is put high level, vehicle on the simulated roadway is through second toroid winding, this level signal exports its corresponding I/O output interface module to through second driver, and controls its corresponding LED lamp and light;
Step 4: first processor obtains the analog rate value of binary-coded decimal form according to first toroid winding to the second toroidal spacing on the track of the timing of corresponding analog rate output and setting;
Step 5: first processor exports the analog rate value of the binary-coded decimal form that obtains to binary-coded decimal through data bus changes 7 segment encode converters, converts 7 segment encode output valves to; First processor OPADD bus is carried out address decoding to gate array charactron address decoder simultaneously, gate array charactron address decoder output useful signal, and the binary-coded decimal of gating correspondence changes the significance bit of 7 segment encode converters, shows by the charactron display;
Step 6: first processor time-delay a period of time, the LED lamp of I/O1 port and I/O2 port being put low level and controlling two port correspondences closes and goes out, and finishes an analog rate output, and described delay time is set according to required analog rate;
Step 7: circulation execution in step 2 ~ step 6 is modeled to two toroidal rate signal outputs of the constant spacing on the track to every pair of I/O port of first processor.
Beneficial effect:
The utility model can be exported 4 tunnel I/O analog pulse signals independently, and each I/O can be modeled to a coil output.Through first processor control output, can make per two I/O constitute a pair of signal output (being equivalent to simulate two coils on the track).Adopt interrupt mode outputting standard timing pulse signal by another sheet separate processor, alleviated the burden of first processor, make the velocity accuracy that calculates obtain reliable assurance, the speed of production test and field adjustable is greatly improved, and can guarantee the quality of product and engineering.Practical application for the scene can improve its project progress.
Utilize low cheap general single-chip microcomputer to finish high-quality product, adopt two single-chip microcomputers respectively to finish different functional modules, make system's simplicity of design reasonable.Simultaneously, also can then can finish other function by two processors are programmed respectively.Reached the effect that a plate is used more.The utility model has the digital demonstration of velocity amplitude and I/O state LED lamp deixis, makes scene and operating personnel understand field condition intuitively.The utility model can pass through panel speed output mode selector switch, is set in easily under a kind of mode in two kinds of patterns of speed change and constant speed and works.Adopt the 3U physical dimension, can be inserted in the existing cabinet external structure housing of avoiding redeveloping easily.
Description of drawings
Fig. 1 is the apparatus structure block diagram of the analog rate output of the utility model embodiment;
Fig. 2 is the device circuit schematic diagram of the analog rate output of the utility model embodiment;
Fig. 3 makes the synoptic diagram of the device arrangements of integrated circuit board by the 3U physical dimension for the device of the analog rate output of the utility model embodiment;
Fig. 4 is the waveform synoptic diagram that the device of the analog rate output of the utility model embodiment is simulated a track;
Fig. 5 is the analog rate output procedure process flow diagram of the utility model embodiment.
Embodiment
Below in conjunction with accompanying drawing embodiment of the present utility model is elaborated.
As shown in Figure 1, a kind of device of analog rate output comprises that first processor, second processor, binary-coded decimal change 7 segment encode converters, gate array charactron address decoder, charactron display, first driver, second driver, I/O output interface module, LED lamp, speed output mode selector switch;
The device circuit of the analog rate output of present embodiment as shown in Figure 2, first processor is selected AT89C2051 type single-chip microcomputer for use, second processor is selected AT89C51 type single-chip microcomputer for use, binary-coded decimal changes 7 segment encode converters, and to select model for use be MC14511B, first driver and second driver are all selected Schmidt's driver 74HC14 for use, and it is DB15I/O that the I/O output interface module is selected model for use.
First processor is for the device by the toroidal signal of the process of the motor vehicle on its I/O port simulated roadway, 4 I/O signal outputs of first processor control i.e. 4 I/O output interface modules, track of per two I/O signal imitations, according to different velocity amplitudes, through calculating the timing ga(u)ge numerical value that needs, control the timing simulated maneuver vehicle speed output of each I/O again according to timing ga(u)ge numerical value, between two I/O signals, produced and be equivalent to vehicle by toroidal analog signal waveform, simultaneously, the corresponding speed value being converted into the binary-coded decimal form delivers to binary-coded decimal and changes 7 segment encode converters and carry out the digital indicating status that shows and control corresponding LED lamp behind the transcoding.
First processor connects first reset circuit and first oscillatory circuit respectively.First reset circuit provides power-on reset signal to first processor, makes inner each address of first processor and data register zero clearing, brings into operation from start address.First oscillatory circuit provides the clock source to first processor, according to this clock source, makes the first processor operation of executing instruction under unified pulse clock.
Second processor is to adopt interrupt mode output, and the device of standard clock signal is provided to first processor.
Second processor connects second reset circuit and second oscillatory circuit respectively.Second reset circuit provides power-on reset signal to second processor, makes inner each address of second processor and data register zero clearing, and program brings into operation from start address.Second oscillatory circuit provides the clock source to second processor, according to this clock source, makes the operation of executing instruction of second processor under unified pulse clock.
First processor and second processor all adopt single-chip microcomputer.
Binary-coded decimal changes the binary-coded decimal formatted data that 7 segment encode converters will send from the first processor data line, converts the 7 segment encode signals that charactron can show to.
The address signal that gate array charactron address decoder will be uploaded from the first processor address wire is decoded into the gating signal that corresponding binary-coded decimal changes 7 segment encode converters, makes each corresponding binary-coded decimal change 7 segment encode converters and can receive the data that obtain.
The output signal that the charactron display changes 7 segment encode converters according to the binary-coded decimal of correspondence is carried out data and is shown that pin low level lamp is bright, high level lamp go out (charactron is common cathode).
First driver strengthens driving force to the I/O signal of first processor output, also avoids the I/O of first processor directly to be connected with the outside simultaneously being damaged and disturbs.
Second driver strengthens driving force to the I/O signal of first processor output, and constitutes luminous display circuit with 4 LED lamps.
DB15 I/O output interface module is as the interface of first driver with the outside.
Four LED lamps (LED1, LED2, LED3, LED lamp) are as the I/O signal corresponding states demonstration effect of first processor output.
Speed output mode selector switch connects first processor, the output terminal of first processor connects the input end of first driver respectively, the input end of second driver, 6 binary-coded decimals change the input end of 7 segment encode converters and the input end of 6 gate array charactron address decoders, first output end of driver connects the input end of 4 I/O output interface modules, second output end of driver connects 4 LED lamps, 6 binary-coded decimals change the output terminal of 7 segment encode converters and the output terminal of 6 gate array charactron address decoders all is connected to 6 digital tube displays, and the output terminal of second processor connects the input end of first processor.
Speed output mode selector switch is that the output mode of speed comprises fixed speed output mode and continuously variable speed output mode for the device of the output mode of the speed of selection.In the present embodiment, the continuously variable speed output mode is set at continuously the speed output that increases progressively with 1 kilometer/hour speed increment, and the continuous velocity variation range circulates between 20 kilometers/hour to 255 kilometers/hour.The fixed speed output mode is set at 100 kilometers/hour speed outputs.
The device of analog rate output is made integrated circuit board by 3U standard industry casing structure size, as shown in Figure 3, can insert 3U standard industry cabinet.
Adopt flow process that the device of above-mentioned analog rate output carries out analog rate output as shown in Figure 5, step is as follows:
Step 1: first processor is with the whole zero clearings of the level of I/O port, and the level that is about to each I/O port is set to low level, and the timing of setting speed output and the speed of selection output mode, all LED lamps is all closed go out;
Every pair of I/O port of first processor constitutes a pair of analog rate output signal, namely simulates a motor vehicle on the track through two toroid windings, and every pair of I/O port signal is modeled to two toroidal rate signal outputs of the constant spacing on the track; In the present embodiment, I/O1, I/O2 constitute a pair of analog rate output signal, namely simulate a vehicle on the track through two toroid windings, I/O3, I/O4 constitute another to the analog rate output signal, namely simulate vehicle on another track through two toroid windings; In the present embodiment, first coil and the constant spacing of second coil on the track are 2 meters;
Step 2: the level of the port I/O1 of first processor is put high level, vehicle on the simulated roadway is through first toroid winding, this moment, this level signal exported its corresponding I/O output interface module to through first driver, and controlled its corresponding LED lamp and light;
Step 3: second processor provides standard clock signal to first processor, first processor with this as the timer counter least unit.When the first processor timer counter reaches timing, the level of I/O2 port that then will be adjacent with the I/O1 port is put high level, vehicle on the simulated roadway is through second toroid winding, this level signal exports its corresponding I/O output interface module to through second driver, and controls its corresponding LED lamp and light;
Step 4: first processor obtains the analog rate value of binary-coded decimal form according to first toroid winding to the second toroidal spacing on the timing of corresponding analog rate output and the track set.
Step 5: first processor exports the analog rate value of the binary-coded decimal form that obtains to binary-coded decimal through data bus changes 7 segment encode converters, converts 7 segment encode output valves to; First processor OPADD bus is carried out address decoding to gate array charactron address decoder simultaneously, gate array charactron address decoder output useful signal, and the binary-coded decimal of gating correspondence changes the significance bit of 7 segment encode converters, shows by the charactron display;
Step 6: first processor time-delay a period of time, the LED lamp of I/O1 port and I/O2 port being put low level and controlling two port correspondences closes and goes out, and finishes an analog rate output, and described delay time is set according to required analog rate;
Step 7: circulation execution in step 2 ~ step 6 is modeled to two toroidal rate signal outputs of the constant spacing on the track to I/O3, the I/O4 of first processor.
As shown in Figure 4, toroid winding 1 and toroid winding 2 are simulated as the actual installation layout in on-the-spot track, be above-mentioned first toroid winding and second toroid winding, I/O1, I/O2 be by first processor after first driver strengthens, receive the signal (if need simulation second track, can form the second track by I/O3, I/O4 with identical method) of DB15 I/O output interface module.
T1 is that the analog machine motor-car arrives the initial time that first toroid winding picks up counting, and first processor is set to high level ' 1 ' with corresponding I/O1 signal by low level ' 0 ' and exports by first driver at this moment.According to two toroid winding constant spacing S of the speed V that will simulate output and simulation, calculate actual timing T.
T=S/V kilometer/hour
Provide clock signal by second processor, after the first processor timer counter reaches T, through the output of first driver I/O2 is set to high level ' 1 ' by low level ' 0 ' by first processor again.After time-delay after a while (about 1 second), first processor all is set to low level state with I/O1, I/O2, so far finishes the simulation output procedure of certain speed V, and velocity amplitude shows by the charactron display.
Claims (5)
1. the device of analog rate output, be used for the speed output of simulated roadway, it is characterized in that: comprise that first processor, second processor, binary-coded decimal change 7 segment encode converters, gate array charactron address decoder, charactron display, first driver, second driver, I/O output interface module, LED lamp, speed output mode selector switch;
Speed output mode selector switch connects first processor, the output terminal of first processor connects the input end of first driver respectively, the input end of second driver, binary-coded decimal changes the input end of 7 segment encode converters and the input end of gate array charactron address decoder, first output end of driver connects the input end of I/O output interface module, second output end of driver connects the LED lamp, binary-coded decimal changes the output terminal of 7 segment encode converters and the output terminal of gate array charactron address decoder all is connected to the charactron display, and the output terminal of second processor connects the input end of first processor.
2. the device of analog rate according to claim 1 output, it is characterized in that: described first processor connects first reset circuit and first oscillatory circuit respectively.
3. the device of analog rate according to claim 1 output, it is characterized in that: described second processor connects second reset circuit and second oscillatory circuit respectively.
4. the device of analog rate according to claim 1 output, it is characterized in that: described speed output mode selector switch is the device for the output mode of the speed of selection, and the output mode of speed comprises fixing fast output mode and continuously variable speed output mode.
5. the device of analog rate output according to claim 1 is characterized in that: the device of described analog rate output is made integrated circuit board by the 3U physical dimension, can insert in the 3U standard industry cabinet.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320229047 CN203217312U (en) | 2013-04-28 | 2013-04-28 | Apparatus for simulating speed output |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320229047 CN203217312U (en) | 2013-04-28 | 2013-04-28 | Apparatus for simulating speed output |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203217312U true CN203217312U (en) | 2013-09-25 |
Family
ID=49206834
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320229047 Expired - Fee Related CN203217312U (en) | 2013-04-28 | 2013-04-28 | Apparatus for simulating speed output |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203217312U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226336A (en) * | 2013-04-28 | 2013-07-31 | 辽宁天久信息科技产业有限公司 | Device and method for simulating speed output |
-
2013
- 2013-04-28 CN CN 201320229047 patent/CN203217312U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103226336A (en) * | 2013-04-28 | 2013-07-31 | 辽宁天久信息科技产业有限公司 | Device and method for simulating speed output |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101339219B (en) | Turn knob potentiometer rotating life-span tester | |
| CN101021551A (en) | Intelligent comprehensive electronic measuring instrument | |
| CN102967348A (en) | Full-flow-point rapid detection device for water meter | |
| CN103226336B (en) | Method for simulating speed output | |
| CN202748666U (en) | Comprehensive telesignaling simulator | |
| CN203217312U (en) | Apparatus for simulating speed output | |
| CN104360188A (en) | Testing device for telemetry system | |
| CN104900121A (en) | Digital electronic technology experiment system and method based on intelligent evaluation | |
| CN102901870B (en) | Frequency testing system based on singlechip and testing method using same | |
| CN201488749U (en) | Novel meter detection equipment | |
| CN201698626U (en) | Multi-functional development board | |
| CN106610336A (en) | Rotating speed measuring and calibrating device for high-voltage switch tester | |
| CN202757953U (en) | Tester for automobile instrument | |
| CN103631152B (en) | Engine controller hardware-in-loop simulation moment of torsion/rotating speed composite signal analogy method | |
| CN104732848B (en) | EDA Instructional Development experimental boxs | |
| CN103542876A (en) | Automatic testing device for resolver-to-digital converter | |
| CN206148028U (en) | Device of intelligence evaluation analog circuit experiment | |
| CN209357268U (en) | Torque test stand and torsional moment test system | |
| CN203165316U (en) | Comprehensive experiment instrument for computer hardware teaching | |
| CN205317180U (en) | Angle code appearance test system | |
| CN2847690Y (en) | Step motor driver of automobile instrument | |
| CN205229797U (en) | A intelligent test appearance that is used for function test on cloud air conditioner line | |
| CN220773190U (en) | Semi-open microcomputer relay protection experimental device for power system | |
| CN204495363U (en) | A kind of Simple bicycle Refreshed Digital | |
| CN203101615U (en) | Pointer type electric detection meter automatic verification device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130925 Termination date: 20170428 |