CN203191082U - Back-end acquisition card for photon counter module - Google Patents
Back-end acquisition card for photon counter module Download PDFInfo
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- CN203191082U CN203191082U CN 201320173402 CN201320173402U CN203191082U CN 203191082 U CN203191082 U CN 203191082U CN 201320173402 CN201320173402 CN 201320173402 CN 201320173402 U CN201320173402 U CN 201320173402U CN 203191082 U CN203191082 U CN 203191082U
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- photon counter
- counter module
- acquisition card
- pulse
- capture card
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Abstract
The utility model discloses a back-end acquisition card for a photon counter module. The back-end acquisition card is characterized by being formed by sequentially connecting a pulse access capture end, a data analysis and processing end and a PC (personal computer) communication end, wherein the front end of the acquisition card is connected with the photon counter module, and the tail end of the acquisition card is connected with the PC end. The core of the acquisition card disclosed by the utility model chooses 32-bit high-speed FPGA (field programmable gate array) processor EP2C8Q208CN, is capable of capturing the higher light intensity frequency of 167 M, and completely compatible with the output range of the single-photon counter module, so that the range of the frequencies capable of being measured by the system is expanded.
Description
Technical field
The utility model relates to the counting of pulse, specifically is the capture card of a kind of photon counter module rear end.
Background technology
The single photon counter module resolves into single photon to light by the avalanche photodide APD that is operated in Geiger mode angular position digitizer, screens through the circuit of inside modules and handles, the finally pulse that changes at module output terminal output frequency.The frequency range that the difference of light intensity causes exporting pulse is big, and uses the pure hardware circuit of trigger or counter can not catch frequency change pulse so frequently effectively in actual applications.In addition, the higher and irregular pulse of waveform for frequency, existing hardware approach obviously is difficult to identify.The present invention utilizes FPGA to have the advantage of High Speed I/O mouth, has realized the counting that high-frequency and waveform irregular pulse are dashed.
Summary of the invention
The purpose of this utility model is for overcoming the defective of prior art, and a kind of high efficiency, program portable is convenient, cost of development is cheap photon counter module rear end capture card are provided.
The technical scheme that realizes the utility model purpose is:
The capture card of a kind of photon counter module rear end, it is inserted by pulse and catches end, data analysis end for process and PC communication ends and be linked in sequence and form, and the front end of capture card is connected with the photon counter module, and its tail end is held with PC and is connected.Described photon counter module can connect interface more than 8 tunnel or be used for the counting of other pulsers.
Described pulse access is caught end and by industrial BNC connector the photon counter module is connected with this capture card, pulse is linked on the crystal oscillator interface CLK of FPGA, at this moment, the input of pulse just is equivalent to the input of crystal oscillator, use verilog written program module just can detect the edge of individual pulse, thereby realize catching.The I/O acquisition rate of FPGA can reach 167M, has realized catching of upper frequency.
Described data analysis end for process produces the different time periods by the 50M crystal oscillator that FPGA CLK1 connects earlier, realize the time delimitation of data acquisition, general standard is that 1s gathers once, and summary counter, realize conversion between 16 systems and 10 systems by the algorithm of self simultaneously, and data are packaged into the RS-232 protocol format.
Described PC communication ends is made up of max232 chip and peripheral circuit thereof, can be delivered to the PC end to the data in real time that collects, and receive and save as the excel form with the host computer of AccessPort assistant or supporting capture card.
Described FPGA is EP2C8Q208CN.
The utility model has the advantages that:
(1)The present invention can seamless link the Canada excelitas company single photon counter module of producing and the single photon counter module of other companies.
(2) kernel of the present invention is selected 32 high speed FPGA processor EP2C8Q208CN for use, and highlight strength frequency can be captured to 167M, the output area of compatible with single photon counter module fully, and the frequency range that makes native system to measure improves.
(3) EP2C8Q208CN has 8 road crystal oscillator clock input ports, inserts data from this mouth, can accurately catch the data that 8 road single photon counter modules are sent simultaneously.
(4) this invention can also be applied to other devices that can produce pulse.
Description of drawings
Fig. 1 is fundamental diagram of the present invention.
Fig. 2 is structured flowchart of the present invention.
Fig. 3 is workflow diagram of the present invention.
Embodiment
The present invention is further described below in conjunction with drawings and Examples.
With reference to Fig. 1, this capture card mainly connects some can produce the module that irregular pulse dashes, and has selected the single photon counter module in an embodiment, and module is handled the back by data of the present invention and given PC end the data that need.
With reference to Fig. 2, this capture card is inserted to catch end, data analysis end for process and to be linked in sequence with the PC communication ends by pulse to be formed.
Described pulse inserts catches end by BNC connector access pulse to be collected, produces the edge prize procedure by FPGA and catches.Enter the data analysis end for process then, data are carried out conversion calculations, at last luminous power and photon number are sent into the PC communication ends and sent to the PC end.
Its workflow is as shown in Figure 3:
S301: beginning;
S302: detecting has the no pulse input;
S303: the acquisition time section is selected, and is defaulted as 1s;
S304: in the setting-up time section, carry out pulse detection;
S305: carry out data in FPGA inside and handle;
S306: send the data that meet the RS-232 protocol format;
S307: host computer receives data;
S308: finish.
Claims (2)
1. the capture card of a photon counter module rear end is characterized in that: it is inserted by pulse and catches end, data analysis end for process and PC communication ends and be linked in sequence and form, and the front end of capture card is connected with the photon counter module, and its tail end is held with PC and is connected.
2. capture card according to claim 1 is characterized in that: described photon counter module can connect interface more than 8 tunnel or be used for the counting of other pulsers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320173402 CN203191082U (en) | 2013-04-09 | 2013-04-09 | Back-end acquisition card for photon counter module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320173402 CN203191082U (en) | 2013-04-09 | 2013-04-09 | Back-end acquisition card for photon counter module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203191082U true CN203191082U (en) | 2013-09-11 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320173402 Expired - Fee Related CN203191082U (en) | 2013-04-09 | 2013-04-09 | Back-end acquisition card for photon counter module |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203191082U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109253807A (en) * | 2018-10-11 | 2019-01-22 | 桂林电子科技大学 | Based on standard integrated circuit technology low noise single photon detection chip and system |
-
2013
- 2013-04-09 CN CN 201320173402 patent/CN203191082U/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109253807A (en) * | 2018-10-11 | 2019-01-22 | 桂林电子科技大学 | Based on standard integrated circuit technology low noise single photon detection chip and system |
| CN109253807B (en) * | 2018-10-11 | 2020-10-13 | 传周半导体科技(上海)有限公司 | Low-noise single photon detection chip and system based on standard integrated circuit process |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130911 Termination date: 20140409 |