CN203180892U - DCF77 code generating device based on synchronous clock signal of satellite - Google Patents
DCF77 code generating device based on synchronous clock signal of satellite Download PDFInfo
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- CN203180892U CN203180892U CN 201320145433 CN201320145433U CN203180892U CN 203180892 U CN203180892 U CN 203180892U CN 201320145433 CN201320145433 CN 201320145433 CN 201320145433 U CN201320145433 U CN 201320145433U CN 203180892 U CN203180892 U CN 203180892U
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Abstract
The utility model provides a DCF77 code generating device based on a synchronous clock signal of a satellite. The device comprises a first party signal receiving unit and a DCF77 code generation unit. The first party signal receiving unit processes a received first party signal and then sends to the DCF77 code generation unit so as to realize a time comparison function. By using the device of the utility model, cost is low; a circuit is simple; reliability is high; an output waveform delay is small.
Description
Technical field
The utility model relates to a kind of DCF77 code generating device, particularly a kind of DCF77 code generating device based on the satellite synchronizing clock signal.
Background technology
Synchronised clock is exactly will be the clock alignment that is distributed in various places (synchronously), generally referring to can receiving satellite signal (as GPS, the Big Dipper etc.) and obtain accurately UTC after the time, exports various time signals again and is used for needing the equipment of time or instrument etc. that the time accurately is provided to other.
Along with continuous progress in science and technology, people require more and more higher to the time precision of automation equipment.Based on gps satellite system, big-dipper satellite system synchronously to the time device be widely used at some key areas, as electric power system, telecommunications industry, national defence field etc., automation equipment in these fields all needs time synchronized accurately, and the normal operation of operational outfit also all needs time synchronized.
In clock synchronization system, the DCF77 timing code as to the time one of main timing code in the field, be widely used.The DCF77 timing code sends a code element each second, and transmitting the complete time signal of a frame needs one fen clock time, comprise year, month, day, week, the time, minute, second and control information.
The time encoding of DCF77 form, the cycle of each code element is 1 second, and wherein the Binary Zero pulse duration is that the pulse of 100ms represents that preceding 100ms is high level, and back 900ms is low level.The binary one pulse duration is that the pulse of 200ms is represented, preceding 200ms is high level, and back 800ms is low level.Its code element waveform as shown in Figure 1.
The equipment that some countries of Europe produce has the interface that carries out time service by above-mentioned DCF77 timing code, because the coding of DCF77 form is a time standard in Europe, and be widely used in to the time field, but the equipment of some European countries, such as Siemens, companies such as Schneider, when the equipment of production is used in China, just need for equipment provide the DCF77 sign indicating number carry out to the time.As the PLC of Schneider, have special SOE data acquisition unit, when needing DCF77, satellite synchronizing clock factory, enterprise, power station, the communications field to the time be widely used, run into these equipment, all need to solve to the time problem.
So how a kind of generating means of DCF77 sign indicating number is provided, becomes the technical problem that needs to be resolved hurrily.
The utility model content
The technical problem that the utility model solves is how a kind of DCF77 code generating device based on the satellite synchronizing clock signal is provided, and solves the synchronous of satellite-signal and local clock, namely to the time problem.
The utility model provides a kind of DCF77 code generating device based on the satellite synchronizing clock signal, comprise: first party signal receiving unit and DCF77 sign indicating number generation unit, described first party signal receiving unit is sent to described DCF77 sign indicating number generation unit after the first party signal that receives is handled; It is characterized in that described DCF77 sign indicating number generation unit comprises: crystal oscillating circuit, basic code element produces circuit, lock-out pulse circuits for triggering, grouping of bits control circuit, single-chip microcomputer and peripheral circuit; Wherein, described basic code element generation circuit comprises: counter and frequency divider; The output of described crystal oscillating circuit is connected with the input of described counter; The output of described counter is connected with the input of described frequency divider; The output of described frequency divider is connected with the input of described grouping of bits control circuit; The input of described single-chip microcomputer receives the described first party signal after handling, and output is connected with the input of described grouping of bits control circuit; The input of described lock-out pulse circuits for triggering receives the described first party signal after handling, and output is connected with the reset terminal that described basic code element produces circuit; The output of described grouping of bits control circuit is connected with photoelectrical coupler.
Preferably, further comprise: the punctual and signal switch unit of constant temperature receives the first party signal that described first party signal receiving unit sends, and described first party signal is converted to standard signal is sent to described DCF77 sign indicating number generation unit.
Preferably, further comprise: the second party signal receiving unit, described second party signal receiving unit is sent to the punctual and signal switch unit of described constant temperature after the second party signal that receives is handled, and the punctual signal switch unit that reaches of described constant temperature is converted to standard signal as the space signal that is sent to described DCF77 sign indicating number generation unit with described second party signal.
Preferably, described first party signal is satellite-signal; Described second party signal is the IRIG-B coded signal.
Preferably, described first party signal is time signal and pps pulse per second signal.
Preferably, described grouping of bits control circuit is the GAL Programmable Logic Device.
Preferably, described lock-out pulse circuits for triggering adopt flip chip 74HC123 to build again.
A kind of DCF77 code generating device based on the satellite synchronizing clock signal that the utility model provides, after described first party signal receiving unit is handled the first party signal that receives, be sent to DCF77 sign indicating number generation unit, by the single-chip microcomputer in the DCF77 sign indicating number generation unit, the first party signal is resolved and is produced the signal of control DCF77 code element formation output, described DCF77 code element queue signals is stored in the internal memory of single-chip microcomputer, single-chip microcomputer requires export control signal each second according to program, and control signal is sent to the grouping of bits control circuit; Simultaneously, the lock-out pulse circuits for triggering are sent to basic code element with the pps pulse per second signal that receives and produce circuit, after treatment, be sent to the grouping of bits control circuit, by the grouping of bits control circuit with time signal and pps pulse per second signal combination back output DCF77 sign indicating number, finished the DCF77 sign indicating number to the time function, the utility model is by the chip microcontroller concrete function, therefore cost is low, circuit is simple, and output waveform postpones little.
In addition, the utility model has comprised the punctual and signal switch unit of constant temperature on the basis of the above, described second party signal receiving unit is sent to the punctual and signal switch unit of described constant temperature with the second party signal, punctual and the signal switch unit of described constant temperature, by the punctual crystal oscillating circuit in this locality, control circuit is converted to standard signal (time signal of standard and the pps pulse per second signal of standard) as the space signal that is sent to described DCF77 sign indicating number generation unit with described second party signal.Described constant temperature is kept time and is reached the state that signal switch unit also detects the second party signal receiving unit, if the second party signal is normal, when the first party signal breaks down, automatically switch to the second party signal receiving unit, with described second party signal as the input synchronous local clock, when two-way time source signal all breaks down, punctual and the local punctual crystal oscillating circuit of signal switch unit employing of constant temperature, control circuit produces standard time pulse per second (PPS) and time reference signal, and the assurance time signal is effectively exported; That is to say that the punctual signal switch unit that reaches of constant temperature can select external signal as a reference source according to the state of external signal (first party signal or second party signal) automatically, signal is converted to standard signal is sent to DCF77 sign indicating number generation unit.
The utility model is by the switch of Single-chip Controlling gate, produce circuit by basic code element and produce basic symbol pulses, DCF77 depends on the signal leading edge triggering forward position of basic symbol pulses, therefore can be by opening gate in advance, allow the undelayed method of passing through of pulse, make that circuit delay is very little, simultaneously, the reset signal that the lock-out pulse circuits for triggering produce makes the entire circuit synchronism good.Therefore, the utility model cost is low, circuit is simple, and output waveform postpone little, effectively realized to the time function.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment and technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment and the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the code element waveform schematic diagram of the DCF77 sign indicating number of a kind of DCF77 code generating device based on the satellite synchronizing clock signal of providing of the utility model;
Fig. 2 is the structured flowchart of a kind of DCF77 code generating device based on the satellite synchronizing clock signal of providing of the utility model;
Fig. 3 is the circuit structure block diagram of a kind of DCF77 code generating device based on the satellite synchronizing clock signal of providing of the utility model;
Fig. 4 be the utility model provide a kind of based on the GAL programming device internal circuit logic diagram in the DCF77 code generating device of satellite synchronizing clock signal;
Fig. 5 is the oscillogram of the divided pulse signal of a kind of DCF77 code generating device based on the satellite synchronizing clock signal of providing of the utility model.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described, obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
Please refer to shown in Figure 2ly, Fig. 2 is the structured flowchart of a kind of DCF77 code generating device based on the satellite synchronizing clock signal of providing of the utility model.
A kind of DCF77 code generating device based on the satellite synchronizing clock signal that the utility model provides, comprise: first party signal receiving unit and DCF77 sign indicating number generation unit, described first party signal receiving unit is sent to described DCF77 sign indicating number generation unit after the first party signal that receives is handled; It is characterized in that described DCF77 sign indicating number generation unit comprises: crystal oscillating circuit, basic code element produces circuit, lock-out pulse circuits for triggering, grouping of bits control circuit, single-chip microcomputer and peripheral circuit; Wherein, described basic code element generation circuit comprises: counter and frequency divider; The output of described crystal oscillating circuit is connected with the input of described counter; The output of described counter is connected with the input of described frequency divider; The output of described frequency divider is connected with the input of described grouping of bits control circuit; The input of described single-chip microcomputer receives the described first party signal after handling, and output is connected with the input of described grouping of bits control circuit; The input of described lock-out pulse circuits for triggering receives the described first party signal after handling, and output is connected with the reset terminal that described basic code element produces circuit; The output of described grouping of bits control circuit is connected with photoelectrical coupler.
Particularly, with reference to shown in Figure 3, Fig. 3 is the circuit structure block diagram of a kind of DCF77 code generating device based on the satellite synchronizing clock signal of providing of the utility model in conjunction with Fig. 2.
Described first party signal receiving unit is handled the first party signal that receives, first party signal after the processing is time signal and pps pulse per second signal, signal after described first party signal receiving unit will be handled sends to DCF77 sign indicating number generation unit, DCF77 sign indicating number generation unit is main control chip with the single-chip microcomputer, the first party signal that reception sends from the first party signal receiving unit, and parsing time signal wherein, produce the signal of control DCF77 code element formation output, described DCF77 code element queue signals is stored in the internal memory of single-chip microcomputer, single-chip microcomputer requires export control signal each second according to program, and control signal is sent to the grouping of bits control circuit.Described DCF77 code element queue signals is stipulated according to the DCF77 agreement, the signal that should send each second is binary zero or binary one, Single Chip Microcomputer (SCM) program all detects the data in the formation of DCF77 code element each second, if 0, then by P1.6 pin control output, door is opened, the pulse of 100ms is let pass, the P1.7 pin blocks the gate circuit of output simultaneously.If 1 is opened corresponding gate circuit by P1.7 pin control output, the pulse of 200ms is let pass, the P1.6 pin blocks the gate circuit of controlling simultaneously, exports simultaneously to prevent two signals, causes confusion (as shown in Figure 4).
Simultaneously, the lock-out pulse circuits for triggering are benchmark with the pps pulse per second signal of standard, produce trigger impulse, make counter, frequency divider synchronous working in the basic code element circuit, crystal oscillating circuit, counter circuit and divider circuit frequency division under the trigger action of unified circuits for triggering obtains basic symbol signal.Basic code element produces circuit basic symbol signal is sent to the grouping of bits control circuit, described grouping of bits control circuit is realized in programmable logic chip GAL, by the GAL chip control signal and basic symbol signal are realized assembly coding, produce the DCF77 coded signal, the DCF77 coded signal is exported from terminal through photoelectric coupler isolation; Thereby realize to the time.
First party signal described above is satellite-signal, is in particular time signal and pps pulse per second signal.
Described lock-out pulse circuits for triggering adopt flip chip 74HC123 to build again, and are time reference with the forward position of the pulse per second (PPS) of standard, produce the chip reset pulse, make counter, frequency divider chip unify zero clearing in the initial moment of per second, the high conformity of circuit.Basic code element produces the delay of pulse front edge in the circuit by the total delay decision of device in the hardware circuit, and its accuracy can be measured.The GAL chip is programmed, build DCF77 code combination circuit at chip internal, make the pulse of circuit output 100ms or 200ms by Single-chip Controlling, at the 59th second, block the output pulse, no pulse output.
DCF77 sign indicating number generation unit is by carrying out processing controls to time reference signal in the utility model, DCF77 sign indicating number output after will handling at last, finished the DCF77 sign indicating number to the time function, the utility model is by the switch of Single-chip Controlling door, hardware circuit produces basic symbol pulses, and DCF77 depends on hardware circuit in the signal leading edge, can advance door opening, allow pulse is undelayed to be passed through, the precision of pulse depends on the precision of hardware circuit.Adopt 74HC123 to produce the reset signal of chip, that can do is very narrow, makes that circuit delay is very little.Therefore, the utility model cost is low, circuit is simple, and output waveform postpones little.
In addition, a kind of DCF77 code generating device based on the satellite synchronizing clock signal that the utility model provides, further comprise: the punctual and signal switch unit of constant temperature, receive the first party signal that described first party signal receiving unit sends, and described first party signal is converted to standard signal is sent to described DCF77 sign indicating number generation unit.
Time signal after the first party signal receiving unit will be resolved and pps pulse per second signal are sent to the punctual and signal switch unit of constant temperature, the punctual signal switch unit that reaches of constant temperature is resolved the first party signal of receiving (time signal and pps pulse per second signal), and will resolve the time signal of the back standard that produces and the pps pulse per second signal of standard, and be sent to DCF77 sign indicating number generation unit.
When abnormal conditions appear in the first party signal receiving unit, in order to guarantee the normal effectively output of time signal and pps pulse per second signal, the utility model further comprises: the second party signal receiving unit, described second party signal receiving unit is sent to the punctual and signal switch unit of described constant temperature with the second party signal, punctual and the signal switch unit of described constant temperature, by the punctual crystal oscillating circuit in this locality, control circuit is converted to standard signal (time signal of standard and the pps pulse per second signal of standard) with described second party signal and is sent to described DCF77 sign indicating number generation unit.Described constant temperature is kept time and is reached the state that signal switch unit also detects the second party signal receiving unit, if the second party signal is normal, when the first party signal breaks down, automatically switch to the second party signal receiving unit, as the synchronous local clock of input, when two-way time source signal all broke down, the punctual signal switch unit that reaches of constant temperature adopted local punctual crystal oscillating circuit with described second party signal, produce standard time pulse per second (PPS) and time reference signal, the assurance time signal is effectively exported.
The punctual signal switch unit that reaches of described constant temperature can be passed through chip microcontroller, single-chip microcomputer receives the time signal of the first party signal that the first party signal receiving unit sends here by serial ports, and the time signal that receives is carried out continuity and correctness judge, if the life period abnormal signal then adopts internal time output, time signal is not upgraded, can be with then switching to the second party signal receiving unit if detect the time signal of second party signal receiving unit, simultaneously update time signal, if the time signal of second party signal receiving unit is unusual, single-chip microcomputer is operated under the inner punctual state, detect the continuity of first party signal receiving unit time signal simultaneously, when the time signal of the time signal of first party signal receiving unit or second party signal receiving unit is effective, switch to corresponding signal element, update time signal.Remove to tame the punctual pps pulse per second signal that reaches signal switch unit of constant temperature with the pulse per second (PPS) of first party signal or the pulse per second (PPS) of second party signal as reference signal, make constant temperature pulse per second (PPS) output signal punctual and signal switch unit follow the tracks of the pps pulse per second signal of input, can effectively prevent the problem that pulse per second (PPS) is lost.
Described first party signal is satellite-signal; Described second party signal is B coded signal or in the clock system networking, is sent by certain clock of power plant, as standby signal.So described second party signal is a kind of space signal.
Described first party signal receiving unit receives signal by adopting dash receiver; The second party signal receiving unit is that the outside signal that provides directly is provided.The IRIG-B signal according to State Grid's standard, is the clock by upper level, the signal that sends out, to lower level clock be used for to the time.
Therefore, a kind of DCF77 code generating device based on the satellite synchronizing clock signal that provides by the utility model can realize to the time function, and cost is low, circuit is simple, and output waveform postpones little.
The preferred implementation of a kind of DCF77 code generating device based on the satellite synchronizing clock signal that the above only provides for the utility model does not constitute the restriction to the utility model protection range.The mode that number of components among this embodiment is not limited to adopt among the embodiment; any any modification of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the claim protection range of the present utility model.
Claims (7)
1. DCF77 code generating device based on the satellite synchronizing clock signal, comprise: first party signal receiving unit and DCF77 sign indicating number generation unit, described first party signal receiving unit is sent to described DCF77 sign indicating number generation unit after the first party signal that receives is handled; It is characterized in that described DCF77 sign indicating number generation unit comprises: crystal oscillating circuit, basic code element produces circuit, lock-out pulse circuits for triggering, grouping of bits control circuit, single-chip microcomputer and peripheral circuit; Wherein, described basic code element generation circuit comprises: counter and frequency divider; The output of described crystal oscillating circuit is connected with the input of described counter; The output of described counter is connected with the input of described frequency divider; The output of described frequency divider is connected with the input of described grouping of bits control circuit; The input of described single-chip microcomputer receives the described first party signal after handling, and output is connected with the input of described grouping of bits control circuit; The input of described lock-out pulse circuits for triggering receives the described first party signal after handling, and output is connected with the reset terminal that described basic code element produces circuit; The output of described grouping of bits control circuit is connected with photoelectrical coupler.
2. device according to claim 1, it is characterized in that, further comprise: the punctual and signal switch unit of constant temperature receives the first party signal that described first party signal receiving unit sends, and described first party signal is converted to standard signal is sent to described DCF77 sign indicating number generation unit.
3. device according to claim 2, it is characterized in that, further comprise: the second party signal receiving unit, described second party signal receiving unit is sent to the punctual and signal switch unit of described constant temperature after the second party signal that receives is handled, and the punctual signal switch unit that reaches of described constant temperature is converted to standard signal as the standby time signal that is sent to described DCF77 sign indicating number generation unit with described second party signal.
4. device according to claim 3 is characterized in that, described first party signal is satellite-signal; The IRIG-B coded signal that described second party signal is international standard.
5. device according to claim 4 is characterized in that, described satellite-signal is time signal and pps pulse per second signal.
6. device according to claim 1 is characterized in that, described grouping of bits control circuit is the GAL programmable circuit.
7. device according to claim 1 is characterized in that, described lock-out pulse circuits for triggering adopt flip chip 74HC123 to build again.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201320145433 CN203180892U (en) | 2013-03-27 | 2013-03-27 | DCF77 code generating device based on synchronous clock signal of satellite |
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| CN 201320145433 CN203180892U (en) | 2013-03-27 | 2013-03-27 | DCF77 code generating device based on synchronous clock signal of satellite |
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| CN 201320145433 Expired - Fee Related CN203180892U (en) | 2013-03-27 | 2013-03-27 | DCF77 code generating device based on synchronous clock signal of satellite |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104410411A (en) * | 2014-12-16 | 2015-03-11 | 镇江中煤电子有限公司 | Intelligent phase locking device for long-distance synchronous communication clock |
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2013
- 2013-03-27 CN CN 201320145433 patent/CN203180892U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104410411A (en) * | 2014-12-16 | 2015-03-11 | 镇江中煤电子有限公司 | Intelligent phase locking device for long-distance synchronous communication clock |
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Granted publication date: 20130904 |