CN203180838U - Time-delay release amplifier circuit of operational amplifier relay - Google Patents
Time-delay release amplifier circuit of operational amplifier relay Download PDFInfo
- Publication number
- CN203180838U CN203180838U CN 201320121261 CN201320121261U CN203180838U CN 203180838 U CN203180838 U CN 203180838U CN 201320121261 CN201320121261 CN 201320121261 CN 201320121261 U CN201320121261 U CN 201320121261U CN 203180838 U CN203180838 U CN 203180838U
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- resistor
- capacitor
- operational amplifier
- amplifier
- time
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Abstract
The utility model discloses a time-delay release amplifier circuit of an operational amplifier relay. The time-delay release amplifier circuit of the operational amplifier relay comprises a direct-current power supply, a first operational amplifier, a second operational amplifier, a first loudspeaker, a second loudspeaker, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor and an eighth resistor. The anti-interference capacity of the time-delay release amplifier circuit is improved by adopting time-delay release of the operational amplifier relay. The time-delay release amplifier circuit has the advantages of being simple in structure, strong in anti-interference capacity and long in service life.
Description
Technical field
The utility model relates to a kind of amplifier, relates in particular to a kind of amplifier relay time-delay and discharges amplifier circuit.
Background technology
At present, the requirement to modern shipborne radar has: improve target acquisition distance, radar antijamming capability, data with new rate, functional reliability and shortening available machine time.And the vertical direction broad beam that radar antenna transmits and receives exists spatial selectivity poor; Can not the measurement target elevation angle; In radar detection area, there is directional diagram zero point because of the interference between direct projection radio wave and the sea surface reflection radio wave; The amplifier that is used for carrier-borne antenna; High elevation angle airbound target detects poor performance; Poor anti jamming capability; So just need receive and send its signal by antenna, and aerial signal receives and sends so requirement is amplified its signal from anti-interference.But, be used at present receiving and the aerial signal amplifier that sends, poor anti jamming capability, can not be accurately to the amplification of signal.
The utility model content
The purpose of this utility model provides a kind of amplifier relay time-delay to discharge amplifier circuit with regard to being in order to address the above problem.
The utility model is achieved through the following technical solutions above-mentioned purpose:
The utility model comprises DC power supply, first operational amplifier, second operational amplifier, first loud speaker, second loud speaker, first capacitor, second capacitor, the 3rd capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, first resistor, second resistor, the 3rd resistor, the 4th resistor, the 5th resistor, the 6th resistor, the 7th resistor and the 8th resistor, the cathode output end of described DC power supply respectively with first end of described second capacitor, first end of described the 3rd resistor, the normal phase input end of described first operational amplifier, first end of described first resistor is connected with first end of described second resistor, second end of described first resistor is connected with first end of described first capacitor, second end of described second resistor respectively with first end of described the 3rd capacitor, first end of described the 4th resistor is connected with the signal output part of described first operational amplifier, second end of described the 3rd capacitor is connected with first end of described first loud speaker, the inverting input of described first operational amplifier is connected with the normal phase input end of described second operational amplifier, second end of described the 3rd resistor is connected with first end of described the 4th capacitor and first end of described the 5th resistor respectively, the inverting input of described second operational amplifier is connected with first end of described the 6th resistor and first end of described the 7th resistor respectively, second end of described the 6th resistor is connected with first end of described the 5th capacitor, second end of described the 7th resistor respectively with first end of described the 8th resistor, first end of the signal output part of described second operational amplifier and described the 6th capacitor is connected, second end of described the 6th capacitor is connected with first end of described second loud speaker, second end of described first capacitor, second end of described second capacitor, second end of described the 4th capacitor, second end of described the 5th capacitor, second end of described the 4th resistor, second end of described the 5th resistor, second end of described the 8th resistor, second end of described first loud speaker all is connected with the cathode output end of described DC power supply with second end of described second loud speaker.
The beneficial effects of the utility model are:
The utility model makes amplifier increase anti-jamming capacity by adopting the time-delay of amplifier relay to discharge; The utlity model has the advantage that circuit structure is simple, antijamming capability is strong and useful life is long.
Description of drawings
Fig. 1 is the circuit diagram that a kind of amplifier relay time-delay described in the utility model discharges amplifier circuit.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing:
As shown in Figure 1, the utility model comprises DC power supply, the first operational amplifier IC1, the second operational amplifier IC2, the first loud speaker BL1, the second loud speaker BL2, the first capacitor C1, the second capacitor C2, the 3rd capacitor C3, the 4th capacitor C4, the 5th capacitor C5, the 6th capacitor C6, the first resistor R1, the second resistor R2, the 3rd resistor R3, the 4th resistor R4, the 5th resistor R5, the 6th resistor R6, the 7th resistor R7 and the 8th resistor R8, the cathode output end of DC power supply respectively with first end of the second capacitor C2, first end of the 3rd resistor R3, the normal phase input end of the first operational amplifier IC1, first end of the first resistor R1 is connected with first end of the second resistor R2, second end of the first resistor R1 is connected with first end of the first capacitor C1, second end of the second resistor R2 respectively with first end of the 3rd capacitor C3, first end of the 4th resistor R4 is connected with the signal output part of the first operational amplifier IC1, second end of the 3rd capacitor C3 is connected with first end of the first loud speaker BL1, the inverting input of the first operational amplifier IC1 is connected with the normal phase input end of the second operational amplifier IC2, second end of the 3rd resistor R3 is connected with first end of the 4th capacitor C4 and first end of the 5th resistor R5 respectively, the inverting input of the second operational amplifier IC2 is connected with first end of the 6th resistor R6 and first end of the 7th resistor R7 respectively, second end of the 6th resistor R6 is connected with first end of the 5th capacitor C5, second end of the 7th resistor R7 respectively with first end of the 8th resistor R8, the signal output part of the second operational amplifier IC2 is connected with first end of the 6th capacitor C6, second end of the 6th capacitor C6 is connected with first end of the second loud speaker BL2, second end of the first capacitor C1, second end of the second capacitor C2, second end of the 4th capacitor C4, second end of the 5th capacitor C5, second end of the 4th resistor R4, second end of the 5th resistor R5, second end of the 8th resistor R8, second end of second end of the first loud speaker BL1 and the second loud speaker BL2 all is connected with the cathode output end of DC power supply.
Claims (1)
1. an amplifier relay time-delay discharges amplifier circuit, it is characterized in that: comprise DC power supply, first operational amplifier, second operational amplifier, first loud speaker, second loud speaker, first capacitor, second capacitor, the 3rd capacitor, the 4th capacitor, the 5th capacitor, the 6th capacitor, first resistor, second resistor, the 3rd resistor, the 4th resistor, the 5th resistor, the 6th resistor, the 7th resistor and the 8th resistor, the cathode output end of described DC power supply respectively with first end of described second capacitor, first end of described the 3rd resistor, the normal phase input end of described first operational amplifier, first end of described first resistor is connected with first end of described second resistor, second end of described first resistor is connected with first end of described first capacitor, second end of described second resistor respectively with first end of described the 3rd capacitor, first end of described the 4th resistor is connected with the signal output part of described first operational amplifier, second end of described the 3rd capacitor is connected with first end of described first loud speaker, the inverting input of described first operational amplifier is connected with the normal phase input end of described second operational amplifier, second end of described the 3rd resistor is connected with first end of described the 4th capacitor and first end of described the 5th resistor respectively, the inverting input of described second operational amplifier is connected with first end of described the 6th resistor and first end of described the 7th resistor respectively, second end of described the 6th resistor is connected with first end of described the 5th capacitor, second end of described the 7th resistor respectively with first end of described the 8th resistor, first end of the signal output part of described second operational amplifier and described the 6th capacitor is connected, second end of described the 6th capacitor is connected with first end of described second loud speaker, second end of described first capacitor, second end of described second capacitor, second end of described the 4th capacitor, second end of described the 5th capacitor, second end of described the 4th resistor, second end of described the 5th resistor, second end of described the 8th resistor, second end of described first loud speaker all is connected with the cathode output end of described DC power supply with second end of described second loud speaker.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320121261 CN203180838U (en) | 2013-03-18 | 2013-03-18 | Time-delay release amplifier circuit of operational amplifier relay |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320121261 CN203180838U (en) | 2013-03-18 | 2013-03-18 | Time-delay release amplifier circuit of operational amplifier relay |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203180838U true CN203180838U (en) | 2013-09-04 |
Family
ID=49077492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320121261 Expired - Fee Related CN203180838U (en) | 2013-03-18 | 2013-03-18 | Time-delay release amplifier circuit of operational amplifier relay |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203180838U (en) |
-
2013
- 2013-03-18 CN CN 201320121261 patent/CN203180838U/en not_active Expired - Fee Related
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130904 Termination date: 20140318 |