CN203177552U - Temperature control device for semiconductor coolers - Google Patents
Temperature control device for semiconductor coolers Download PDFInfo
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- CN203177552U CN203177552U CN 201320153276 CN201320153276U CN203177552U CN 203177552 U CN203177552 U CN 203177552U CN 201320153276 CN201320153276 CN 201320153276 CN 201320153276 U CN201320153276 U CN 201320153276U CN 203177552 U CN203177552 U CN 203177552U
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Abstract
The utility model discloses a temperature control device for semiconductor coolers. The temperature control device comprises a main board circuit, three driving circuits with the same structure and five semiconductor coolers with the same structure, wherein four semiconductor coolers of the five semiconductor coolers are positioned on the same horizontal plane and form a rectangular shape, every two semiconductor coolers of the four semiconductor coolers are in one group, the two semiconductor coolers in each group are connected in series, in addition, the two semiconductor coolers in each group are driven by a driving circuit, the other one semiconductor cooler is arranged above the four semiconductor coolers and is positioned in the right center of the rectangular shape formed by the other four semiconductor coolers, and the semiconductor cooler is fixed to the four semiconductor coolers at the lower layer through heat conducting estersil and is driven by the third driving circuit. The temperature control device has the advantages that the size of the temperature control device per se is small, the driving capability of a power supply is sufficiently utilized, the power supply utilization rate is improved, and the temperature control flexibility is enhanced.
Description
Technical field
The utility model belongs to semiconductor control technology field, relates to a kind of temperature control equipment, specifically is a kind of semiconductor cooler attemperating unit.
Background technology
Temperature characterisitic is to consider an extremely important index of many photoelectric devices and device performance, and especially in some certain applications, for some temperature sensitive device and device, temperature performance becomes one of greatest factor of its application of restriction.For example, under mal-conditions such as aeronautical environment, Military Application, some precision optics measuring units, as optical fibre gyro, namely very responsive to environment temperature.Extreme temperature environment makes the photoelectric device mis-behave of optical fibre gyro inside, thereby causes gyroscopic stability and reliability decrease, even can not work.Therefore, thermally sensitive photoelectric device and equipment carry out the important step that temperature performance test on a large scale is the fastidious stability of a system and reliability.Certainly, except investigating photoelectric device on a large scale temperature stability and the reliability, the ability that needs the taking into account system bearing temperature to impact toward contact.When the resisting temperature impact capacity of test component and equipment, need test macro temperature change extremely fast.Simultaneously, responsive unusually to vibration such as gyro and similar photoelectric device or system, when carrying out the test of temperature correlation performance, the expectation testing equipment is not introduced vibration yet.
Therefore, for the temperature performance test of optical fibre gyro and similar photoelectric device or system, three requirements the most basic have been proposed test macro: have bigger temperature to become scope; Controlled warm variable Rate, temperature becomes fast; Do not introduce vibration.Simultaneously, wish that also attemperating unit is simple in structure, reliable and stable, control is convenient, the small and exquisite suitable low profile photovoltaic device of volume.
Traditional temperature test equipment is the incubator of compressor formula, and there are several shortcomings in it: for small and exquisite photoelectric device, volume is too huge; Power consumption is big; Vibration of compressor has a strong impact on test result etc.
Summary of the invention
The purpose of this utility model is at the deficiencies in the prior art, and a kind of semiconductor cooler attemperating unit is provided.
The utility model comprises a master control borad circuit, three drive circuit, five semiconductor coolers that structure is identical that structure is identical; Four semiconductor coolers in five semiconductor coolers are on same horizontal plane, constitute rectangular-shaped, four semiconductor coolers are one group with two, two semiconductor cooler series connection of every group, and two semiconductor coolers of every group are driven by a drive circuit; Another semiconductor cooler is arranged on four semiconductor coolers, and be positioned at the rectangular-shaped positive center that other four semiconductor coolers constitute, this semiconductor cooler is fixed by four semiconductor coolers of conduction estersil and lower floor, is driven by the 3rd drive circuit.
Described master control borad circuit comprises governor circuit and serial port circuit;
Governor circuit comprises main control chip U1, the first crystal oscillator CY1, first resistance R 1, first capacitor C 1 and second capacitor C 2, and 4 pin of main control chip U1 connect an end of first resistance R 1, another termination+5V power supply of first resistance R 1; 14 pin of main control chip U1 are connected with the end of the first crystal oscillator CY1, an end of first capacitor C 1, one end of 15 pin of main control chip U1 and the other end of the first crystal oscillator CY1, second capacitor C 2, be connected the equal ground connection of the other end of the other end of first capacitor C 1 and second capacitor C 2; 6 pin of main control chip U1,17 pin, 38 pin connect+the 5V power supply, 16 pin of main control chip U1,28 pin, 39 pin ground connection;
Serial port circuit comprises master control serial port chip U2, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4 and the 5th resistance R 5; 2 pin of master control serial port chip U2 are connected with an end of second resistance R 2, and 3 pin are connected with an end of the 3rd resistance R 3, and 4 pin are connected with an end of the 4th resistance R 4, and 5 pin are connected with an end of the 5th resistance R 5; The other end of second resistance R 2 is connected with 7 pin of main control chip U1, the other end of the 3rd resistance R 3 is connected with 12 pin of main control chip U1, the other end of the 4th resistance R 4 is connected with 13 pin of main control chip U1, and the other end of the 5th resistance R 5 is connected with 5 pin of main control chip U1; 13 pin and 14 pin of master control serial port chip U2 connect+the 5V power supply; 6 pin of master control serial port chip U2 and 7 pin ground connection;
Described main control chip U1 is the ATmega162L-8AI chip;
Described master control serial port chip U2 is the 7LB180 chip;
Described drive circuit comprises Drive and Control Circuit, drives serial port circuit and H bridge control circuit;
Drive and Control Circuit comprises driving control chip U3, the second crystal oscillator CY2, the 6th resistance R 6, the 3rd capacitor C 3 and the 4th capacitor C 4; 4 pin that drive control chip U3 are connected another termination+5V power supply of the 6th resistance R 6 with an end of the 6th resistance R 6; 7 pin that drive control chip U3 are connected with the end of the second crystal oscillator CY2, an end of the 3rd capacitor C 3, and 8 pin are connected with the other end of the second crystal oscillator CY2, an end of the 4th capacitor C 4; The other end ground connection of the other end of the 3rd capacitor C 3 and the 4th capacitor C 4; 5 pin, 17 pin, 27 pin, 29 pin, 38 pin that drive control chip U3 connect+the 5V power supply; Drive 6 pin, 18 pin, 28 pin, the 39 pin ground connection of control chip U3;
Drive serial port circuit and comprise driving serial port chip U4, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10; 2 pin that drive serial port chip U4 are connected with an end of the 7th resistance R 7, and 3 pin are connected with an end of the 8th resistance R 8, and 4 pin are connected with an end of the 9th resistance R 9, and 5 pin are connected with an end of the tenth resistance R 10; The other end of the 7th resistance R 7 is connected with 10 pin that drive control chip U3, the other end of the 8th resistance R 8 is connected with 3 pin that drive control chip U3, the other end of the 9th resistance R 9 is connected with 2 pin that drive control chip U3, and the other end of the tenth resistance R 10 is connected with 9 pin that drive control chip U3; 13 pin and 14 pin that drive serial port chip U4 connect+the 5V power supply; Drive 6 pin and the 7 pin ground connection of serial port chip U4; 9 pin that drive serial port chip U4 connect 12 pin of master control serial port chip U2,10 pin that drive serial port chip U4 connect 11 pin of master control serial port chip U2,11 pin that drive serial port chip U4 connect 10 pin of master control serial port chip U2, and 12 pin that drive serial port chip U4 connect 9 pin of master control serial port chip U2;
The H bridge control circuit comprises that H bridge control chip U5, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 15 resistance R 15, the 16 resistance R 16, the 17 resistance R 17, the 18 resistance R 18, the 19 resistance R 19, the 20 resistance R 20, the 4th capacitor C 5, the 4th capacitor C 6, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS manage N4; 21 pin of H bridge control chip U5 are connected with an end of the 11 resistance R 11,22 pin are connected with an end of the 12 resistance R 12,23 pin are connected with an end of the 13 resistance R 13,24 pin are connected with an end of the 14 resistance R 14,25 pin are connected with an end of the 15 resistance R 15, and 26 pin are connected with an end of the 16 resistance R 16; The other end of the 11 resistance R 11 is connected with 16 pin that drive control chip U3, the other end of the 12 resistance R 12 is connected with 15 pin that drive control chip U3, the other end of the 13 resistance R 13 is connected with 14 pin that drive control chip U3, the other end of the 14 resistance R 14 is connected with 13 pin that drive control chip U3, the other end of the 15 resistance R 15 is connected with 12 pin that drive control chip U3, and the other end of the 16 resistance R 16 is connected with 11 pin that drive control chip U3; 5 pin of H bridge control chip U5 are connected with an end of the 17 resistance R 17, and the other end of the 17 resistance R 17 is connected with the grid of NMOS pipe N1; 3 pin of H bridge control chip U5 are connected with an end of the 18 resistance R 18, and the other end of the 18 resistance R 18 is connected with the grid of the 2nd NMOS pipe N2; 10 pin of H bridge control chip U5 are connected with an end of the 19 resistance R 19, and the other end of the 19 resistance R 19 is connected with the grid of the 3rd NMOS pipe N3; 12 pin of H bridge control chip U5 are connected with an end of the 20 resistance R 20, and the other end of the 20 resistance R 20 is connected with the grid of the 4th NMOS pipe N4; 6 pin of H bridge control chip U5 are connected with an end of the 5th capacitor C 5, the source electrode of the drain electrode of the other end of 4 pin and the 5th capacitor C 5, NMOS pipe N1, the 2nd NMOS pipe N2 is connected, and with this 4 pin as the drive end of a semiconductor cooler TEC in the series connection group or directly as a drive end of single semiconductor cooler in the non-series connection group; 9 pin of H bridge control chip U5 are connected with an end of the 6th capacitor C 6, the source electrode of the drain electrode of the other end of 11 pin and the 6th capacitor C 6, the 3rd NMOS pipe N3, the 4th NMOS pipe N4 is connected, and with this 11 pin as the drive end of another semiconductor cooler TEC in the series connection group or directly as another drive end of single semiconductor cooler in the non-series connection group; The source electrode of the source electrode of the one NMOS pipe N1 and the 3rd NMOS pipe N3 connects+the 15V power supply, the grounded drain of the drain electrode of the 2nd NMOS pipe N2 and the 4th NMOS pipe N4.
Wherein driving control chip U3 is the ATmega16-16MC chip;
Wherein driving serial port chip U4 is the 7LB180 chip;
Wherein H bridge control chip U5 is the A3940 chip, and the NMOS pipe is the IRF3205NMOS pipe.
The drive end of two of the H bridge control circuit semiconductor cooler TEC is connected with the input of semiconductor cooler TEC in the series connection group respectively in each drive circuit.The master control borad circuit transmits control signal by the driving serial port circuit of serial port circuit to three drive circuits, after the controlled signal of drive circuit, the PWM that the driving control chip U3 of Drive and Control Circuit produces corresponding pulsewidth involves logic control signal, and PWM is involved logic control signal send to the H bridge control circuit, the H bridge control circuit receives PWM and involves logic control signal, directly control the one NMOS manages N1, the 2nd NMOS manages N2, the 3rd NMOS manages N3, the orderly break-make of this four NMOS pipe of the 4th NMOS pipe N4, thereby the break-make of the drive end output current of control semiconductor cooler TEC, reach the size of semiconductor cooler TEC drive current in the control series connection group, the drive current of the corresponding different sizes of the PWM of distinct pulse widths, by changing PWM ripple pulsewidth, can change the size of semiconductor cooler drive current, thereby reach different temperature control amounts.Simultaneously, send to the logic control signal of H bridge control circuit by change, the H bridge control circuit is worked under the different mode, can change the sense of current of the drive end output current of H bridge control circuit semiconductor cooler TEC, thereby make semiconductor cooler work in heating or refrigerating state.
The utility model beneficial effect:
Compare conventional apparatus, the utility model device uses TEC as heating and refrigeration part, and volume own is small and exquisite, is fit to the test of photoelectric device.Simultaneously, TEC can not introduce vibration during work, is conducive to the test to the device of vibration sensing.In the utility model, four semiconductor coolers in five semiconductor coolers are on same horizontal plane, constitute rectangular-shaped, another semiconductor cooler is arranged on four semiconductor coolers, and is positioned at positive center, arranges like this, guaranteed to reach maximal heat transfer efficient between the two-layer TEC up and down, easy for installation, test macro temperature change extremely fast simultaneously also can obtain bigger temperature and become scope.And 4 TEC of lower floor are connected in twos, take full advantage of the driving force of power supply, improve the power utilization rate, increased temperature controlled flexibility ratio.
Description of drawings
Fig. 1 is the utility model attemperating unit structural representation;
Fig. 2 is the utility model master control borad circuit diagram;
Fig. 3 is the utility model drive circuit schematic diagram;
Fig. 4 is the utility model H bridge control circuit.
The specific embodiment
Below in conjunction with accompanying drawing the utility model is described further.
As shown in Figure 1, the semiconductor cooler attemperating unit comprises a master control borad circuit, three drive circuit, five semiconductor coolers that structure is identical that structure is identical; The first semiconductor cooler TEC1, the second semiconductor cooler TEC2, the 3rd semiconductor cooler TEC3, the 4th semiconductor cooler TEC4 are on same horizontal plane in five semiconductor coolers, constitute rectangular-shaped, and the first semiconductor cooler TEC1, second semiconductor cooler TEC2 series connection is one group, and the 3rd semiconductor cooler TEC3, the 4th semiconductor cooler TEC4 series connection is another group; The semiconductor cooler of two groups of series connection first drive circuit, second drive circuit respectively drives; The 5th semiconductor cooler TEC5 is arranged on four semiconductor coolers, and be positioned at the rectangular-shaped positive center that other four semiconductor coolers constitute, the 5th semiconductor cooler TEC5 fixes by four semiconductor coolers of conduction estersil and lower floor, is driven by the 3rd drive circuit.
As shown in Figure 2, described master control borad circuit comprises governor circuit and serial port circuit;
Governor circuit comprises main control chip U1, the first crystal oscillator CY1, first resistance R 1, first capacitor C 1 and second capacitor C 2, and 4 pin of main control chip U1 connect an end of first resistance R 1, another termination+5V power supply of first resistance R 1; 14 pin of main control chip U1 are connected with the end of the first crystal oscillator CY1, an end of first capacitor C 1, one end of 15 pin of main control chip U1 and the other end of the first crystal oscillator CY1, second capacitor C 2, be connected the equal ground connection of the other end of the other end of first capacitor C 1 and second capacitor C 2; 6 pin of main control chip U1,17 pin, 38 pin connect+the 5V power supply, 16 pin of main control chip U1,28 pin, 39 pin ground connection;
Serial port circuit comprises master control serial port chip U2, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4 and the 5th resistance R 5; 2 pin of master control serial port chip U2 are connected with an end of second resistance R 2, and 3 pin are connected with an end of the 3rd resistance R 3, and 4 pin are connected with an end of the 4th resistance R 4, and 5 pin are connected with an end of the 5th resistance R 5; The other end of second resistance R 2 is connected with 7 pin of main control chip U1, the other end of the 3rd resistance R 3 is connected with 12 pin of main control chip U1, the other end of the 4th resistance R 4 is connected with 13 pin of main control chip U1, and the other end of the 5th resistance R 5 is connected with 5 pin of main control chip U1; 13 pin and 14 pin of master control serial port chip U2 connect+the 5V power supply; 6 pin of master control serial port chip U2 and 7 pin ground connection;
Described main control chip U1 is the ATmega162L-8AI chip;
Described master control serial port chip U2 is the 7LB180 chip;
Described drive circuit comprises Drive and Control Circuit, drives serial port circuit and H bridge control circuit;
As shown in Figure 3, Drive and Control Circuit comprises driving control chip U3, the second crystal oscillator CY2, the 6th resistance R 6, the 3rd capacitor C 3 and the 4th capacitor C 4; 4 pin that drive control chip U3 are connected another termination+5V power supply of the 6th resistance R 6 with an end of the 6th resistance R 6; 7 pin that drive control chip U3 are connected with the end of the second crystal oscillator CY2, an end of the 3rd capacitor C 3, and 8 pin are connected with the other end of the second crystal oscillator CY2, an end of the 4th capacitor C 4; The other end ground connection of the other end of the 3rd capacitor C 3 and the 4th capacitor C 4; 5 pin, 17 pin, 27 pin, 29 pin, 38 pin that drive control chip U3 connect+the 5V power supply; Drive 6 pin, 18 pin, 28 pin, the 39 pin ground connection of control chip U3;
As shown in Figure 3, drive serial port circuit and comprise driving serial port chip U4, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10; 2 pin that drive serial port chip U4 are connected with an end of the 7th resistance R 7, and 3 pin are connected with an end of the 8th resistance R 8, and 4 pin are connected with an end of the 9th resistance R 9, and 5 pin are connected with an end of the tenth resistance R 10; The other end of the 7th resistance R 7 is connected with 10 pin that drive control chip U3, the other end of the 8th resistance R 8 is connected with 3 pin that drive control chip U3, the other end of the 9th resistance R 9 is connected with 2 pin that drive control chip U3, and the other end of the tenth resistance R 10 is connected with 9 pin that drive control chip U3; 13 pin and 14 pin that drive serial port chip U4 connect+the 5V power supply; Drive 6 pin and the 7 pin ground connection of serial port chip U4; 9 pin that drive serial port chip U4 connect 12 pin of master control serial port chip U2,10 pin that drive serial port chip U4 connect 11 pin of master control serial port chip U2,11 pin that drive serial port chip U4 connect 10 pin of master control serial port chip U2, and 12 pin that drive serial port chip U4 connect 9 pin of master control serial port chip U2;
As shown in Figure 4, the H bridge control circuit comprises that H bridge control chip U5, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 15 resistance R 15, the 16 resistance R 16, the 17 resistance R 17, the 18 resistance R 18, the 19 resistance R 19, the 20 resistance R 20, the 4th capacitor C 5, the 4th capacitor C 6, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS manage N4; 21 pin of H bridge control chip U5 are connected with an end of the 11 resistance R 11,22 pin are connected with an end of the 12 resistance R 12,23 pin are connected with an end of the 13 resistance R 13,24 pin are connected with an end of the 14 resistance R 14,25 pin are connected with an end of the 15 resistance R 15, and 26 pin are connected with an end of the 16 resistance R 16; The other end of the 11 resistance R 11 is connected with 16 pin of main control chip U1, the other end of the 12 resistance R 12 is connected with 15 pin of main control chip U1, the other end of the 13 resistance R 13 is connected with 14 pin of main control chip U1, the other end of the 14 resistance R 14 is connected with 13 pin of main control chip U1, the other end of the 15 resistance R 15 is connected with 12 pin of main control chip U1, and the other end of the 16 resistance R 16 is connected with 11 pin of main control chip U1; 5 pin of H bridge control chip U5 are connected with an end of the 17 resistance R 17, and the other end of the 17 resistance R 17 is connected with the grid of NMOS pipe N1; 3 pin of H bridge control chip U5 are connected with an end of the 18 resistance R 18, and the other end of the 18 resistance R 18 is connected with the grid of the 2nd NMOS pipe N2; 10 pin of H bridge control chip U5 are connected with an end of the 19 resistance R 19, and the other end of the 19 resistance R 19 is connected with the grid of the 3rd NMOS pipe N3; 12 pin of H bridge control chip U5 are connected with an end of the 20 resistance R 20, and the other end of the 20 resistance R 20 is connected with the grid of the 4th NMOS pipe N4; 6 pin of H bridge control chip U5 are connected with an end of the 5th capacitor C 5, the source electrode of the drain electrode of the other end of 4 pin and the 5th capacitor C 5, NMOS pipe N1, the 2nd NMOS pipe N2 is connected, and with this 4 pin as the drive end of a semiconductor cooler TEC in the series connection group or directly as a drive end of single semiconductor cooler in the non-series connection group; 9 pin of H bridge control chip U5 are connected with an end of the 6th capacitor C 6, the source electrode of the drain electrode of the other end of 11 pin and the 6th capacitor C 6, the 3rd NMOS pipe N3, the 4th NMOS pipe N4 is connected, and with this 11 pin as the drive end of another semiconductor cooler TEC in the series connection group or directly as another drive end of single semiconductor cooler in the non-series connection group; The source electrode of the source electrode of the one NMOS pipe N1 and the 3rd NMOS pipe N3 connects+the 15V power supply, the grounded drain of the drain electrode of the 2nd NMOS pipe N2 and the 4th NMOS pipe N4.
Wherein driving control chip U3 is the ATmega16-16MC chip;
Wherein driving serial port chip U4 is the 7LB180 chip;
Wherein H bridge control chip U5 is the A3940 chip, and the NMOS pipe is the IRF3205NMOS pipe;
The drive end of two of the H bridge control circuit semiconductor cooler TEC is connected with the input of semiconductor cooler TEC in the series connection group respectively in each drive circuit.The master control borad circuit transmits control signal by the driving serial port circuit of serial port circuit to three drive circuits, after the controlled signal of drive circuit, the PWM that the driving control chip U3 of Drive and Control Circuit produces corresponding pulsewidth involves logic control signal, and PWM is involved logic control signal send to the H bridge control circuit, the H bridge control circuit receives PWM and involves logic control signal, directly control the one NMOS manages N1, the 2nd NMOS manages N2, the 3rd NMOS manages N3, the orderly break-make of this four NMOS pipe of the 4th NMOS pipe N4, thereby the break-make of the drive end output current of control semiconductor cooler TEC, reach the size of semiconductor cooler TEC drive current in the control series connection group, the drive current of the corresponding different sizes of the PWM of distinct pulse widths, by changing PWM ripple pulsewidth, can change the size of semiconductor cooler drive current, thereby reach different temperature control amounts.Simultaneously, send to the logic control signal of H bridge control circuit by change, the H bridge control circuit is worked under the different mode, can change the sense of current of the drive end output current of H bridge control circuit semiconductor cooler TEC, thereby make semiconductor cooler work in heating or refrigerating state.
Claims (2)
1. the semiconductor cooler attemperating unit comprises a master control borad circuit, three drive circuit, five semiconductor coolers that structure is identical that structure is identical; It is characterized in that:
Four semiconductor coolers in five semiconductor coolers are on same horizontal plane, constitute rectangular-shaped, four semiconductor coolers are one group with two, two semiconductor cooler series connection of every group, and two semiconductor coolers of every group are driven by a drive circuit; Another semiconductor cooler is arranged on four semiconductor coolers, and be positioned at the rectangular-shaped positive center that other four semiconductor coolers constitute, this semiconductor cooler is fixed by four semiconductor coolers of conduction estersil and lower floor, is driven by the 3rd drive circuit;
Described master control borad circuit comprises governor circuit and serial port circuit;
Governor circuit comprises main control chip U1, the first crystal oscillator CY1, first resistance R 1, first capacitor C 1 and second capacitor C 2, and 4 pin of main control chip U1 connect an end of first resistance R 1, another termination+5V power supply of first resistance R 1; 14 pin of main control chip U1 are connected with the end of the first crystal oscillator CY1, an end of first capacitor C 1, one end of 15 pin of main control chip U1 and the other end of the first crystal oscillator CY1, second capacitor C 2, be connected the equal ground connection of the other end of the other end of first capacitor C 1 and second capacitor C 2; 6 pin of main control chip U1,17 pin, 38 pin connect+the 5V power supply, 16 pin of main control chip U1,28 pin, 39 pin ground connection;
Serial port circuit comprises master control serial port chip U2, second resistance R 2, the 3rd resistance R 3, the 4th resistance R 4 and the 5th resistance R 5; 2 pin of master control serial port chip U2 are connected with an end of second resistance R 2, and 3 pin are connected with an end of the 3rd resistance R 3, and 4 pin are connected with an end of the 4th resistance R 4, and 5 pin are connected with an end of the 5th resistance R 5; The other end of second resistance R 2 is connected with 7 pin of main control chip U1, the other end of the 3rd resistance R 3 is connected with 12 pin of main control chip U1, the other end of the 4th resistance R 4 is connected with 13 pin of main control chip U1, and the other end of the 5th resistance R 5 is connected with 5 pin of main control chip U1; 13 pin and 14 pin of master control serial port chip U2 connect+the 5V power supply; 6 pin of master control serial port chip U2 and 7 pin ground connection;
Described drive circuit comprises Drive and Control Circuit, drives serial port circuit and H bridge control circuit;
Drive and Control Circuit comprises driving control chip U3, the second crystal oscillator CY2, the 6th resistance R 6, the 3rd capacitor C 3 and the 4th capacitor C 4; 4 pin that drive control chip U3 are connected another termination+5V power supply of the 6th resistance R 6 with an end of the 6th resistance R 6; 7 pin that drive control chip U3 are connected with the end of the second crystal oscillator CY2, an end of the 3rd capacitor C 3, and 8 pin are connected with the other end of the second crystal oscillator CY2, an end of the 4th capacitor C 4; The other end ground connection of the other end of the 3rd capacitor C 3 and the 4th capacitor C 4; 5 pin, 17 pin, 27 pin, 29 pin, 38 pin that drive control chip U3 connect+the 5V power supply; Drive 6 pin, 18 pin, 28 pin, the 39 pin ground connection of control chip U3;
Drive serial port circuit and comprise driving serial port chip U4, the 7th resistance R 7, the 8th resistance R 8, the 9th resistance R 9, the tenth resistance R 10; 2 pin that drive serial port chip U4 are connected with an end of the 7th resistance R 7, and 3 pin are connected with an end of the 8th resistance R 8, and 4 pin are connected with an end of the 9th resistance R 9, and 5 pin are connected with an end of the tenth resistance R 10; The other end of the 7th resistance R 7 is connected with 10 pin that drive control chip U3, the other end of the 8th resistance R 8 is connected with 3 pin that drive control chip U3, the other end of the 9th resistance R 9 is connected with 2 pin that drive control chip U3, and the other end of the tenth resistance R 10 is connected with 9 pin that drive control chip U3; 13 pin and 14 pin that drive serial port chip U4 connect+the 5V power supply; Drive 6 pin and the 7 pin ground connection of serial port chip U4; 9 pin that drive serial port chip U4 connect 12 pin of master control serial port chip U2,10 pin that drive serial port chip U4 connect 11 pin of master control serial port chip U2,11 pin that drive serial port chip U4 connect 10 pin of master control serial port chip U2, and 12 pin that drive serial port chip U4 connect 9 pin of master control serial port chip U2;
The H bridge control circuit comprises that H bridge control chip U5, the 11 resistance R 11, the 12 resistance R 12, the 13 resistance R 13, the 14 resistance R 14, the 15 resistance R 15, the 16 resistance R 16, the 17 resistance R 17, the 18 resistance R 18, the 19 resistance R 19, the 20 resistance R 20, the 4th capacitor C 5, the 4th capacitor C 6, a NMOS pipe N1, the 2nd NMOS pipe N2, the 3rd NMOS pipe N3, the 4th NMOS manage N4; 21 pin of H bridge control chip U5 are connected with an end of the 11 resistance R 11,22 pin are connected with an end of the 12 resistance R 12,23 pin are connected with an end of the 13 resistance R 13,24 pin are connected with an end of the 14 resistance R 14,25 pin are connected with an end of the 15 resistance R 15, and 26 pin are connected with an end of the 16 resistance R 16; The other end of the 11 resistance R 11 is connected with 16 pin that drive control chip U3, the other end of the 12 resistance R 12 is connected with 15 pin that drive control chip U3, the other end of the 13 resistance R 13 is connected with 14 pin that drive control chip U3, the other end of the 14 resistance R 14 is connected with 13 pin that drive control chip U3, the other end of the 15 resistance R 15 is connected with 12 pin that drive control chip U3, and the other end of the 16 resistance R 16 is connected with 11 pin that drive control chip U3; 5 pin of H bridge control chip U5 are connected with an end of the 17 resistance R 17, and the other end of the 17 resistance R 17 is connected with the grid of NMOS pipe N1; 3 pin of H bridge control chip U5 are connected with an end of the 18 resistance R 18, and the other end of the 18 resistance R 18 is connected with the grid of the 2nd NMOS pipe N2; 10 pin of H bridge control chip U5 are connected with an end of the 19 resistance R 19, and the other end of the 19 resistance R 19 is connected with the grid of the 3rd NMOS pipe N3; 12 pin of H bridge control chip U5 are connected with an end of the 20 resistance R 20, and the other end of the 20 resistance R 20 is connected with the grid of the 4th NMOS pipe N4; 6 pin of H bridge control chip U5 are connected with an end of the 5th capacitor C 5, the source electrode of the drain electrode of the other end of 4 pin and the 5th capacitor C 5, NMOS pipe N1, the 2nd NMOS pipe N2 is connected, and with this 4 pin as the drive end of a semiconductor cooler TEC in the series connection group or directly as a drive end of single semiconductor cooler in the non-series connection group; 9 pin of H bridge control chip U5 are connected with an end of the 6th capacitor C 6, the source electrode of the drain electrode of the other end of 11 pin and the 6th capacitor C 6, the 3rd NMOS pipe N3, the 4th NMOS pipe N4 is connected, and with this 11 pin as the drive end of another semiconductor cooler TEC in the series connection group or directly as another drive end of single semiconductor cooler in the non-series connection group; The source electrode of the source electrode of the one NMOS pipe N1 and the 3rd NMOS pipe N3 connects+the 15V power supply, the grounded drain of the drain electrode of the 2nd NMOS pipe N2 and the 4th NMOS pipe N4.
2. semiconductor cooler attemperating unit as claimed in claim 1 is characterized in that:
Described main control chip U1 is the ATmega162L-8AI chip;
Described master control serial port chip U2 is the 7LB180 chip;
Wherein driving control chip U3 is the ATmega16-16MC chip;
Wherein driving serial port chip U4 is the 7LB180 chip;
Wherein H bridge control chip U5 is the A3940 chip, and the NMOS pipe is the IRF3205NMOS pipe.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320153276 CN203177552U (en) | 2013-03-29 | 2013-03-29 | Temperature control device for semiconductor coolers |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320153276 CN203177552U (en) | 2013-03-29 | 2013-03-29 | Temperature control device for semiconductor coolers |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103234316A (en) * | 2013-03-29 | 2013-08-07 | 浙江大学 | Temperature control device for semiconductor cooler |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103234316A (en) * | 2013-03-29 | 2013-08-07 | 浙江大学 | Temperature control device for semiconductor cooler |
| CN103234316B (en) * | 2013-03-29 | 2015-04-15 | 浙江大学 | Temperature control device for semiconductor cooler |
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