CN203166766U - Digital control DC/DC converter - Google Patents

Digital control DC/DC converter Download PDF

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Publication number
CN203166766U
CN203166766U CN201320137051XU CN201320137051U CN203166766U CN 203166766 U CN203166766 U CN 203166766U CN 201320137051X U CN201320137051X U CN 201320137051XU CN 201320137051 U CN201320137051 U CN 201320137051U CN 203166766 U CN203166766 U CN 203166766U
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China
Prior art keywords
transducer
output
control
circuit
power stage
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CN201320137051XU
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Chinese (zh)
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王盛宇
周劲松
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SUZHOU LANGXU ELECTRONIC TECHNOLOGY Co Ltd
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SUZHOU LANGXU ELECTRONIC TECHNOLOGY Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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  • Dc-Dc Converters (AREA)

Abstract

The utility model discloses a digital control DC/DC converter. The digital control DC/DC converter comprises two parts of a power grade circuit and a control unit, wherein a primary grade of the power grade circuit comprises a full bridge inverter circuit formed by four sets of switch field effect transistors Q1, Q2, Q3 and Q4, an input end of the full bridge inverter circuit is connected with direct current high voltage, an output end of the full bridge inverter circuit is connected with a primary winding of a high-frequency transformer, after rectification and filtering, secondary grade winding output of the high-frequency transformer after rectification and filtering is connected with direct current low voltage output, a secondary grade employs a synchronous rectifier formed by two field effect transistors Q5 and Q6 to reduce secondary grade conduction loss, and high precision pulse width modulation (HRPWM) output of the control unit passes through the driving circuit and then is connected with grid electrodes of the field effect transistors Q1, Q2, Q3, Q4, Q5 and Q6. The digital control DC/DC converter realizes digital control, moreover, the adaptive synchronous rectifier realizes optimization on dead zone time to achieve higher conversion efficiency.

Description

Use numerically controlled DC/DC transducer
Technical field
The utility model relates to the numerically controlled DC/DC transducer of a kind of use.
Background technology
As one of hybrid power, the crucial energy conversion elements of pure electric automobile, the function of DC/DC transducer is that the voltage transitions with the on-board high-voltage battery pack is the 14V power supply supplying conventional low pressure mobile unit (unidirectional decompression mode), or the subsidiary 14V boosting ability (two-way mode) of boosting simultaneously.The DC/DC transducer has multiple implementation, and as the early stage two-stage change-over circuit that boosts and add half-bridge that adopts of the Camry hybrid vehicle of Toyota Motor Corporation, and more general full-bridge phase shifting zero voltage switch circuit is realized.
From the control mode aspect; these DC/DC transducers all adopt simulation control; its core control function is finished by special Switching Power Supply control integrated circuit as error amplifier, ramp generator, pulse width modulator (PWM) and over-voltage over-current protection, soft start etc.Through the development of decades, adopt the top standard DC/DC converter performance of simulation control to arrive its peak substantially.Using the traditional analog control of being familiar with to drive design only allows doing very little improvement aspect conversion efficiency and the power density index.
The utility model content
The numerically controlled DC/DC transducer of a kind of use, it has realized the digital control of DC/DC transducer, adaptive synchronous rectifier realizes optimizing and then reaching higher conversion efficiency to Dead Time simultaneously.
In order to solve these problems of the prior art, the technical scheme that the utility model provides is:
The numerically controlled DC/DC transducer of a kind of use, comprise power stage circuit and control unit two parts, the elementary of power stage circuit comprises by four groups of switched field effect pipe Q1, Q2, Q3, the full bridge inverter that Q4 forms, the input of full bridge inverter is connected with high direct voltage and the elementary winding of output and high frequency transformer joins, the secondary winding output of high frequency transformer is connected with dc low-voltage output behind rectifying and wave-filtering, secondary employing is by two field effect transistor Q5, the synchronous rectifier that Q6 forms reduces secondary conduction loss, and high accuracy pulsewidth modulation (HRPWM) output of control unit inserts the grid of described field effect transistor Q1～Q6 behind drive circuit.
For technique scheme, utility model people also has further optimization embodiment.
As optimization, in power stage circuit elementary, be provided with current transformer, be used for providing required current signal to control unit.
As optimization, the output of full bridge inverter also is provided with change of current inductance, and change of current inductance is with the elementary windings in series of high frequency transformer, and the parasitic capacitance with limit, source brachium pontis forms resonant circuit realization ZVS operation again.
As optimization, control unit comprises microprocessor, data storage, analog to digital converter (ADC), high accuracy pulsewidth modulator (HRPWM), control law coprocessor (CLA),
The analog signal of the power stage circuit in the DC/DC transducer is joined with analog to digital converter through buffer circuit;
High accuracy pulsewidth modulator is responsible for producing the grid control signal of power stage switching device Q1～Q6, and the controlled quentity controlled variable of grid control signal comprises accurate cycle, phase shift and Dead Time;
The control law coprocessor is used for electric current is carried out quick adjustment, and microprocessor is used for realizing output voltage control and the system monitoring merit of low speed;
Communication-cooperation between microprocessor and the control law coprocessor is finished by the shared region of data storage.
As optimization; also be provided with analog comparator in the control unit; analog signal in the DC/DC transducer is sent to analog comparator; analog comparator comparative voltage, electric current, temperature signal judge whether to exist overvoltage, overcurrent and overtemperature; and, be used for the protection of realization rapid system and avoid damaging DC/DC transducer hardware by the control of high accuracy pulsewidth modulator realization to the power stage circuit of DC/DC transducer according to result of determination.
As optimization, the analog signal of the power stage circuit in the DC/DC transducer comprises input voltage, output voltage, electric current and temperature signal.
Can adopt following efficiency optimization method based on the numerically controlled DC/DC transducer of above-mentioned use utility model people, described method is used for best t time of delay of search D1And t D2, t D1With Q 2The trailing edge of control PWM is reference, t D2With Q 4The trailing edge of control PWM is reference, makes the stable state duty ratio minimum of transducer, and the multi-channel PWM of the control unit of DC/DC transducer is shared same time reference, specifically optimizes flow process (with search t D1For example is described) as follows:
Step 1, begin t D1Be set at an abundant little time value to guarantee the safe operation of DC/DC transducer, preserve this value as optimal value;
Step 2, waiting system reach stable state, and controller is preserved corresponding stable state duty ratio;
Step 3, controller are by step delta t D1Increase progressively Dead Time t D1
Step 4, algorithm treat that system reaches new stable state, and controller obtains t D1Duty ratio after the increase and with the 3rd the step duty ratio compare;
If the stable state duty ratio that step 5 is new is less than or equal to the dutyfactor value of preservation, algorithm returns step 3, repeating step 3～5 after covering old value with new dutyfactor value;
Step 6, new stable state duty ratio are greater than the dutyfactor value of preserving, and algorithm is set the t before increasing progressively D1For optimal value and finish t D1Search;
Step 7, from feasible abundant big time value successively decrease the search t D2
Step 8, end.
The execution of described efficiency optimization method causes by trigger mechanism, and possible trigger mechanism contains the variation (as input voltage, load current, variations in temperature and other transient affair) of system power-on reset, certain transducer operating condition.
With respect to scheme of the prior art, the utility model has the advantages that:
1. do not sacrificing any electric property, comprising under degree of regulation, transient response, the output noise level conditions, conversion efficiency equals optimum available simulation solution at least;
2. higher integrated level and abundanter operating characteristic, flexibility;
3. the quick feedback control loop of transducer and system control function are finished by same microcontroller, directly reduce number of devices cost, circuit board space cost;
4. be easier to realize burst mode (Burst Mode) operation under the light-load conditions, and then improve the conversion efficiency of transducer under light-load conditions;
5. allow the setting of many group control parameters, in wide region, improve the transducer transient response characteristic by the real-time parameter scheduling.
Description of drawings
Below in conjunction with drawings and Examples the utility model is further described:
Fig. 1 is the structural representation of the power stage circuit of the utility model embodiment;
Fig. 2 is the structural representation of the control unit of the utility model embodiment;
Fig. 3 is the digital feedback control loop work schematic diagram among the utility model embodiment;
Fig. 4 is digital phase shift pulse-width modulation (PWM) output waveform figure among the utility model embodiment;
Fig. 5 is the secondary synchronization rectifier dead band time setting schematic diagram among the utility model embodiment;
Fig. 6 is the system flow chart that implementation efficiency is optimized among the utility model embodiment.
Embodiment
Below in conjunction with specific embodiment such scheme is described further.Should be understood that these embodiment are not limited to limit scope of the present utility model for explanation the utility model.The implementation condition that adopts among the embodiment can be done further adjustment according to the condition of concrete producer, and not marked implementation condition is generally the condition in the normal experiment.
Embodiment:
Present embodiment has been described the numerically controlled DC/DC transducer of a kind of use, comprise power stage circuit and control unit two parts, the elementary of power stage circuit as shown in Figure 1 comprises by four groups of switched field effect pipe Q1, Q2, Q3, the full bridge inverter that Q4 forms, the input of full bridge inverter is connected with high direct voltage 1 and the elementary winding of output and high frequency transformer 2 joins, the secondary winding output of high frequency transformer 2 is connected with dc low-voltage output 5 behind rectifying and wave-filtering, secondary employing is by two field effect transistor Q5, the synchronous rectifier that Q6 forms reduces secondary conduction loss, and high accuracy pulsewidth modulation (HRPWM) output of control unit inserts the grid of described field effect transistor Q1～Q6 behind drive circuit.
In power stage circuit elementary, be provided with current transformer 3, be used for providing required current signal to control unit.The output of full bridge inverter also is provided with change of current inductance, and change of current inductance is with the elementary windings in series of high frequency transformer 2, and the parasitic capacitance with limit, source brachium pontis forms resonant circuit realization ZVS operation again.
Control unit as shown in Figure 2 comprises microprocessor, data storage, analog to digital converter (ADC), high accuracy pulsewidth modulator (HRPWM), control law coprocessor (CLA) 10,
The analog signal of the power stage circuit in the DC/DC transducer is joined with analog to digital converter through buffer circuit;
High accuracy pulsewidth modulator is responsible for producing the grid control signal of power stage switching device Q1～Q6, and the controlled quentity controlled variable of grid control signal comprises accurate cycle, phase shift and Dead Time;
The control law coprocessor is used for electric current is carried out quick adjustment, and microprocessor is used for realizing output voltage control and the system monitoring merit of low speed;
Communication-cooperation between microprocessor and the control law coprocessor is finished by the shared region of data storage.
Also be provided with analog comparator in the control unit; analog signal in the DC/DC transducer is sent to analog comparator; analog comparator comparative voltage, electric current, temperature signal judge whether to exist overvoltage, overcurrent and overtemperature; and, be used for the protection of realization rapid system and avoid damaging DC/DC transducer hardware by the control of high accuracy pulsewidth modulator realization to the power stage circuit of DC/DC transducer according to result of determination.
The analog signal of the power stage circuit in the DC/DC transducer comprises input voltage, output voltage, electric current and temperature signal.
The workflow of DC/DC transducer control loop is as shown in Figure 3, and is specific as follows:
In each switch periods of DC/DC transducer, output voltage at first changes digital signal through sampling back into by 12 analog to digital converter (ADC), and this signal subtracts each other with voltage setting value and obtains output voltage error item e v(t); This error term is passed through the digital loop filters with the PID equivalence again, and the time domain relation that inputs to filter output from error can be described as:
PID ( e v ( t ) ) = k p e v ( t ) + k i ∫ 0 t e v ( τ ) dτ + k d de v ( t ) dt (formula 1)
The dynamic response characteristic of this loop is by three control parameters, ratio k p, integration k iWith differential k dSelection determine.
Pid number filter output is converted into corresponding phase shift again, is programmed to HRPWM by the control law coprocessor with the form of clock number, and then control power switch Q 1-Q 6Turn-on and turn-off, compensated regulation since the output voltage that causes of disturbance change.Be different from traditional simulation control, a special advantage of digital control is to regulate inner control parameter in DC/DC transducer operate as normal; According to the zone, working point of DC/DC transducer, control unit can preset the different optimal PID parameter value of many groups, selects only parameter with conditions such as line voltage, load and temperature then, realizes the optimization of dynamic response characteristic in the transducer gamut.Digital controller is also regulated immediately to the frequency of operation of transducer, promotes transducer than the conversion efficiency under the light load condition in the mode of pulse frequency modulated (PFM), burst mode or discontinuous conduction mode (DCM).
Fig. 4 is converter power switch Q 1-Q 6Grid control waveform, both relative timing relations of its conducting/off state.In this full bridge inverter, Q 1-Q 4In the signal of each switch be that positively biased is slightly less than 180 °, and instead be slightly larger than 180 ° partially; This time difference partially anti-and positively biased derives from: for two MOSFETs of same brachium pontis, Q 1With Q 2Or Q 3With Q 4, have no progeny and need insert certain time of delay in MOSFET pass, wait for that complementary MOSFET enters zero voltage switch (ZVS) time domain and just adds forward bias, thereby cause Q 1-Q 4The positively biased time of MOSFET is less than the anti-time partially.Under the continuous operation mode condition, the output voltage of phase-shifting full-bridge inverter circuit is by regulating the phase place of two brachium pontis, thereby the mode of regulating the output voltage pulse duration obtains.Waveform with Fig. 4 is example, Q here 3Phase place than the phase lag θ of Q1,0 °＜θ＜180 °.Definition phase shift phi=θ/180 °, if ignore the change of current time of inductance 4, output voltage values can be approximate with following formula
V o=Φ nV In(formula 2)
Wherein n is the secondary and elementary turn ratio of transformer 3; Φ and θ are linear, can reach the voltage change ratio that changes transducer by the size that changes θ.Consider the parasitic capacitance of brachium pontis and the influence of change of current inductance, more accurate transducer voltage no-load voltage ratio is provided by following formula
M = V o nV in = Φ + FP ZVT ( J ) (formula 3)
P ZVT ( J ) = 1 2 π [ 1 J - 2 tan - 1 ( 1 J 2 - 1 ) - 2 ( J + J 2 - 1 ) ] (formula 4)
F = f s f o (formula 5)
f o = 1 2 π L c C leg (formula 6)
J = nI V in L c C leg (formula 7)
I is converter current output, L in the following formula cInductance value, C for inductance 4 LegTotal parasitic capacitance equivalence value, f for each brachium pontis sSwitching frequency for transducer.J〉1 for satisfying the necessary condition of ZVS.Here P ZVT(J) value always is negative value, therefore change of current inductance acts on the voltage change ratio that has reduced transducer on the one hand, make Q1-Q4 work in zero voltage switch (ZVS) pattern but then, thereby reduce the switching loss of transducer effectively, its advantage that reduces switching loss is particularly evident in high-frequency converter.Another design of described transducer is considered to make the value of Φ high as far as possible under transducer input-output characteristic enabled condition, and then reduces the conduction loss of converter power level.
Because lower conduction loss, synchronous rectifier is widely used in nearly all low-voltage direct Switching Power Supply.The adjustment capability in the dead band of commutating is depended in the optimum utilization of synchronous rectifier.The long meeting of Dead Time is owing to the conducting of MOSFET body diode and reverse recovery cause extra loss; Dead Time is too short then can be caused the secondary of short duration short circuit of transformer and the efficient of transducer is produced more adverse influence.Since the circuit parameter tolerance, temperature and disturbances of power, and simply fixedly the Dead Time design can seriously damage the efficiency index of transducer.Based on above consideration, steady operation duty ratio minimum that an adaptive Dead Time control method (efficiency optimization method) makes the DC/DC transducer has also been described in this enforcement, conversion efficiency is the highest simultaneously.
At Q 1And Q 4Be in simultaneously during the forward bias, select according to the polarity of transformer of Fig. 1, the head end of Transformer Winding (representing with the polarity round dot among the figure) voltage is on the occasion of, Q 5Should be in off state and the unlikely secondary short circuited that causes.Owing to export Q to from controller 5Have various circuit delays in the actual turn off process, and the control lag of primary switch and synchronous rectifier control lag can not mate fully also, processing mode the simplest and the most commonly used be in converter design to introduce Dead Time, guarantee at Q 1With Q 4Finish Q before the positively biased simultaneously 5Turn-off action.In Dead Time, Q 5The electric current that raceway groove is born is changed into by Q 5Body diode is born, and its result is the increase of conduction loss.Based on the identical requirement of avoiding secondary short circuited, at Q 1With Q 4Positively biased finishes the back and drives Q 5Enter between the conducting state, need to introduce another time of delay, in this period, Q 5Electric current is also born by its body diode but is followed bigger conduction loss.From above-mentioned explanation, best Dead Time is selected should guarantee secondary short circuited not occur but Q 5The time of body diode conducting is the shortest.Q 6Dead Time select and Q 5Identical.
Can adopt following efficiency optimization method based on the numerically controlled DC/DC transducer of above-mentioned use utility model people, described method is used for best t time of delay of search D1And t D2, t D1With Q 2The trailing edge of control PWM is reference, t D2With Q 4The trailing edge of control PWM is reference, makes the stable state duty ratio minimum of transducer, and the multi-channel PWM of the control unit of DC/DC transducer is shared same time reference, specifically optimizes flow process (with search t D1For example is described) as follows:
Step 1, begin t D1Be set at an abundant little time value to guarantee the safe operation of DC/DC transducer, preserve this value as optimal value;
Step 2, waiting system reach stable state, and controller is preserved corresponding stable state duty ratio;
Step 3, controller are by step delta t D1Increase progressively Dead Time t D1
Step 4, algorithm treat that system reaches new stable state, and controller obtains t D1Duty ratio after the increase and with the 3rd the step duty ratio compare;
If the stable state duty ratio that step 5 is new is less than or equal to the dutyfactor value of preservation, algorithm returns step 3, repeating step 3～5 after covering old value with new dutyfactor value;
Step 6, new stable state duty ratio are greater than the dutyfactor value of preserving, and algorithm is set the t before increasing progressively D1For optimal value and finish t D1Search;
Step 7, from feasible abundant big time value successively decrease the search t D2
Step 8, end.
The execution of described efficiency optimization method causes by trigger mechanism, and possible trigger mechanism contains the variation (as input voltage, load current, variations in temperature and other transient affair) of system power-on reset, certain transducer operating condition.
Above-mentioned example only is explanation technical conceive of the present utility model and characteristics, and its purpose is to allow the people who is familiar with this technology can understand content of the present utility model and enforcement according to this, can not limit protection range of the present utility model with this.All equivalent transformation or modifications of doing according to the utility model spirit essence all should be encompassed within the protection range of the present utility model.

Claims (6)

1. one kind is used numerically controlled DC/DC transducer, comprise power stage circuit and control unit two parts, it is characterized in that, the elementary of power stage circuit comprises by four groups of switched field effect pipe Q1, Q2, Q3, the full bridge inverter that Q4 forms, the input of full bridge inverter is connected with high direct voltage and the elementary winding of output and high frequency transformer joins, the secondary winding output of high frequency transformer is connected with dc low-voltage output behind rectifying and wave-filtering, secondary employing is by two field effect transistor Q5, the synchronous rectifier that Q6 forms reduces secondary conduction loss, and high accuracy pulsewidth modulation (HRPWM) output of control unit inserts the grid of described field effect transistor Q1 ~ Q6 behind drive circuit.
2. the numerically controlled DC/DC transducer of use according to claim 1 is characterized in that, is provided with current transformer in power stage circuit elementary, is used for providing required current signal to control unit.
3. the numerically controlled DC/DC transducer of use according to claim 1, it is characterized in that, the output of full bridge inverter also is provided with change of current inductance, and change of current inductance is with the elementary windings in series of high frequency transformer, and the parasitic capacitance with limit, source brachium pontis forms resonant circuit realization ZVS operation again.
4. the numerically controlled DC/DC transducer of use according to claim 1, it is characterized in that, control unit comprises microprocessor, data storage, analog to digital converter (ADC), high accuracy pulsewidth modulator (HRPWM), control law coprocessor (CLA)
The analog signal of the power stage circuit in the DC/DC transducer is joined with analog to digital converter through buffer circuit;
High accuracy pulsewidth modulator is responsible for producing the grid control signal of power stage switching device Q1 ~ Q6, and the controlled quentity controlled variable of grid control signal comprises accurate cycle, phase shift and Dead Time;
The control law coprocessor is used for electric current is carried out quick adjustment, and microprocessor is used for realizing output voltage control and the system monitoring merit of low speed;
Communication-cooperation between microprocessor and the control law coprocessor is finished by the shared region of data storage.
5. the numerically controlled DC/DC transducer of use according to claim 4; it is characterized in that; also be provided with analog comparator in the control unit; analog signal in the DC/DC transducer is sent to analog comparator; analog comparator comparative voltage, electric current, temperature signal judge whether to exist overvoltage, overcurrent and overtemperature; and, be used for the protection of realization rapid system and avoid damaging DC/DC transducer hardware by the control of high accuracy pulsewidth modulator realization to the power stage circuit of DC/DC transducer according to result of determination.
6. the numerically controlled DC/DC transducer of use according to claim 4 is characterized in that the analog signal of the power stage circuit in the DC/DC transducer comprises input voltage, output voltage, electric current and temperature signal.
CN201320137051XU 2013-03-25 2013-03-25 Digital control DC/DC converter Expired - Fee Related CN203166766U (en)

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103138588A (en) * 2013-03-25 2013-06-05 苏州朗旭电子科技有限公司 Direct current (DC)/DC converter controlled in digital mode and efficiency optimization method thereof
CN104167940A (en) * 2014-07-01 2014-11-26 华南理工大学 Driving circuit for phase-shifted full-bridge synchronous rectifier circuit and control method thereof
CN107863878A (en) * 2017-10-13 2018-03-30 无锡瓴芯电子科技有限公司 A kind of switch power source driving circuit based on PWM controls
CN109586581A (en) * 2018-12-15 2019-04-05 华南理工大学 Digital Realization device for full-bridge DC/DC transducer synchronous rectification
WO2019129275A1 (en) * 2017-12-29 2019-07-04 无锡华润上华科技有限公司 Control system for synchronous rectifier tube of llc converter
CN109995228A (en) * 2017-12-29 2019-07-09 东南大学 Dead time Automatic Optimal system under primary side feedback flyback power supply CCM mode

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103138588A (en) * 2013-03-25 2013-06-05 苏州朗旭电子科技有限公司 Direct current (DC)/DC converter controlled in digital mode and efficiency optimization method thereof
CN104167940A (en) * 2014-07-01 2014-11-26 华南理工大学 Driving circuit for phase-shifted full-bridge synchronous rectifier circuit and control method thereof
CN104167940B (en) * 2014-07-01 2017-02-15 华南理工大学 Driving circuit for phase-shifted full-bridge synchronous rectifier circuit and control method thereof
CN107863878A (en) * 2017-10-13 2018-03-30 无锡瓴芯电子科技有限公司 A kind of switch power source driving circuit based on PWM controls
WO2019129275A1 (en) * 2017-12-29 2019-07-04 无锡华润上华科技有限公司 Control system for synchronous rectifier tube of llc converter
CN109995228A (en) * 2017-12-29 2019-07-09 东南大学 Dead time Automatic Optimal system under primary side feedback flyback power supply CCM mode
CN109995228B (en) * 2017-12-29 2020-12-29 东南大学 Dead time automatic optimization system under primary side feedback flyback power supply CCM mode
US11201557B2 (en) 2017-12-29 2021-12-14 Csmc Technologies Fab2 Co, Ltd. Control system for synchronous rectifying transistor of LLC converter
US11557959B2 (en) 2017-12-29 2023-01-17 Csmc Technologies Fab2 Co., Ltd. Deadtime automatic-optimization system for flyback power supply having primary-side feedback in CCM, control system and method for flyback power supply having primary-side feedback in CCM
CN109586581A (en) * 2018-12-15 2019-04-05 华南理工大学 Digital Realization device for full-bridge DC/DC transducer synchronous rectification

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