CN203164960U - Electronic information product - Google Patents
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- CN203164960U CN203164960U CN2013201565221U CN201320156522U CN203164960U CN 203164960 U CN203164960 U CN 203164960U CN 2013201565221 U CN2013201565221 U CN 2013201565221U CN 201320156522 U CN201320156522 U CN 201320156522U CN 203164960 U CN203164960 U CN 203164960U
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Abstract
The utility model relates to an electronic information product which comprises a caching storage cell, a storage cell, a data storage control terminal, an interface cell, a non-caching storage buffer cell and an arbitration cell, wherein the interface cell is respectively connected with the non-caching storage buffer cell and the arbitration cell, the arbitration cell is respectively connected with the interface cell and the storage cell, and the non-caching storage buffer cell is respectively connected with the interface cell and the storage cell. When data to be accessed by the electronic information product are in the caching storage cell, the data are directly accessed from the caching storage cell. When the data to be accessed by the electronic information product are in the non-caching storage buffer cell, the data are directly accessed from the un-caching storage buffer cell. When the data to be accessed by the electronic information product are only in the storage cell, the data are partially accessed from the storage cell, meanwhile, the non-caching storage buffer cell is updated, and then the data are accessed form the un-caching storage buffer cell.
Description
Technical field
The utility model relates to field of data transmission, particularly a kind of electronics and IT products.
Background technology
Along with making rapid progress with flourish of electronic information science and technology, many powerful electronics and IT products are constantly weeded out the old and bring forth the new in function, as PC, notebook computer and other consumption electronic products etc.Meanwhile, the user is more and more higher to the requirement that electronics and IT products can be presented to the user's data processing speed, more specifically, all belong to this respect as the calculating of mass data, complicated application execution, the work such as visual and sound effects when carrying out uploading of data or download and play multimedia by world-wide web.
In fact, the user will realize the function of above-mentioned electronics and IT products, the easiest measure is exactly to upgrade at the hardware device of electronics and IT products, for example to the CPU (central processing unit) processing speed promote, the processing speed of processors such as the Random Access Storage Unit capacity increases, storage facilities access data speed increases, video signal adapting card or audio adapting card increases, even the in full reportedly improvement etc. of transmission frequency width of overall network communication system framework.Can not dare not or would not speak up, the measure that above-mentioned all hardware equipment functions promote is that the effect of getting instant result is arranged for the processing speed of electronics and IT products.But the user will certainly significantly increase on use cost in order to reach the purpose of so-called " HardwareUpgring ", and therefore, pure HardwareUpgring is not to be an economical and practical solution.
Except above-mentioned HardwareUpgring, another widely the measure adopted of user be " software upgrading ", the edition upgrading of for example application programs upgrading, hardware device driver upgrading, interface routine such as DirectX etc. and upgrading of operating system program etc.With regard to economic aspect, to compare with HardwareUpgring, software upgrading almost need not increase cost except application program and operating system program upgrade, therefore, utilize modes such as network download freely to obtain the upgrading software content traditionally under the situation usually.But resulting effect does not have the satisfactory for result of HardwareUpgring in this case.
In a word, how can be issued to lifting electronics and IT products data processing speed in the situation that does not increase great amount of cost is problem demanding prompt solution.Be example with the PC framework, technology is improved at the data access speed of CPU (central processing unit) traditionally, as adding one first rank cache storage unit (Level1Cache Memory) to reduce external data time in CPU (central processing unit) inside, in addition, can also add one second rank cache storage unit (Level2Cache Memory) at motherboard (Main Board), also realize shortening the external data time of CPU (central processing unit).Yet, no matter increase the cache storage unit by aforementioned which kind of form, also to face another problem in the personal computer system field---CPU (central processing unit) and own the right that same cache storage unit block data is read and write together with the interconnective external device (ED) of personal computer system or the interior arrangement that is built in the personal computer system, at this moment, must set up one first monitoring mechanism (snooping), such as when the CPU (central processing unit) execution writes the action of data to the second cache storage unit, if have in the data that write with the first built-in rank cache storage unit of CPU (central processing unit) in wherein stored data have identical address, then make corresponding informance stored in the first rank cache storage unit lose efficacy.Another kind method then is that the particular block with storage unit is set at non-cache (non-cacheable) zone, there are the device of read-write right or unit all the information in the described non-cache block must not be write in the cache storage unit own to the information in the block in the non-cache zone, make the consistance of keeping system information.But, if desire the interior information of the described block of access, then must carry out access and can't have a strong impact on the efficient of work by the cache storage unit of device or unit itself storage unit.
In sum, how can be under the prerequisite of the cost that increases hardware device not significantly, the work efficiency that increases electronics and IT products is problem demanding prompt solution.
The utility model content
For solving the shortcoming of above-mentioned known technology, fundamental purpose of the present utility model is to provide a kind of electronics and IT products data access method and electronics and IT products, increasing not significantly under the cost prerequisite of hardware, increasing the work efficiency of electronics and IT products access data.
For realizing above-mentioned utility model purpose, the utility model proposes a kind of electronics and IT products, comprise cache storage unit, storage unit and data storage control end, described data storage control end is connected with described cache storage unit, described cache storage unit links to each other with described storage unit, and the partial data in the described storage unit stores up in described cache memory cell; When described data storage control end sends the interior data address of data address that data access request signal wants access and described cache storage unit and conforms to, then directly get corresponding data from the cache memory cell;
Described electronics and IT products also comprise interface unit, non-cache storage buffer cell and arbitration unit;
Described interface unit is connected with non-cache storage buffer cell, arbitration unit respectively; Be used for receiving data storage control end and send the data of data access request signal and the transmission access that requires; When described data storage control end sends data access request signal and wants the data address of access and data address in the described cache storage unit does not conform to, send a signal to described non-cache according to described data access request signal and store buffer cell; And when not meeting the data address of described data access request signal requirement access in the non-cache storage buffer cell, again the signal that sends is transferred to described arbitration unit;
Described arbitration unit is connected with described interface unit, storage unit respectively; The signal that is used for sending according to described interface unit is from the storage unit access data;
Described non-cache storage buffer cell is connected with described interface unit, described storage unit respectively; Be used for requiring the data address of access according to the signal that described interface unit the sends over described data access request signal that judges whether to be consistent, and with the described data access from described non-cache storage buffer cell that requires access.
Optionally, in the utility model one embodiment, described arbitration unit is further used for the signal access data from storage unit according to described interface unit transmission; In data when described storage unit is sent to the process of described interface unit, the data of getting of will seeking survival in advance are stored in the described non-cache storage buffer cell from described storage unit, and indicate described interface unit to require information remaining in the data of access to obtain from described non-cache storage buffer cell to transmit with described.
Optionally, in the utility model one embodiment, described electronics and IT products be PC, notebook computer, palmtop computer, personal digital assistant, servomechanism and workstation one of them.
Optionally, in the utility model one embodiment, described storage unit be static random access memory (sram) cell, DRAM cell, synchronous dynamic random-access storage unit and high power speed information transmitting synchronous DRAM cell one of them.
Optionally, in the utility model one embodiment, described data storage control end be CPU (central processing unit), microprocessing unit, circumscribed peripheral device and embedded peripheral device at least one of them.
Technique scheme has following beneficial effect: compare with technical scheme traditionally, the technical solution of the utility model is by a non-cache storage buffer cell mechanism, reduce the interior unit of electronics and IT products or module to the number of times of storage unit direct access information, in addition, continuous information to the described non-cache of access is in advance stored in the buffer cell, improves the work efficiency of information processing.
Description of drawings
In order to be illustrated more clearly in the utility model embodiment or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is embodiment more of the present utility model, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is a kind of electronics and IT products structured flowchart that the utility model proposes;
Fig. 2 is the structured flowchart of example with the personal computer system for electronics and IT products in the utility model.
Embodiment
Below in conjunction with the accompanying drawing among the utility model embodiment, the technical scheme among the utility model embodiment is clearly and completely described.Obviously, described embodiment only is the utility model part embodiment, rather than whole embodiment.Based on the embodiment in the utility model, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the utility model protection.
As shown in Figure 1, a kind of electronics and IT products structured flowchart for the utility model proposes.Comprise cache storage unit, storage unit 100 and data storage control end, described data storage control end is connected with described cache storage unit, described cache storage unit links to each other with described storage unit 100, and the partial data in the described storage unit 100 stores up in described cache memory cell; When described data storage control end sends the interior data address of data address that data access request signal wants access and described cache storage unit and conforms to, then directly get corresponding data from the cache memory cell; It is characterized in that,
Described electronics and IT products 10 also comprise interface unit 102, non-cache storage buffer cell 104 and arbitration unit 106;
Described interface unit 102 is connected with non-cache storage buffer cell 104, arbitration unit 106, data access control end respectively; Be used for receiving the data that electronics and IT products send data access request signal and the transmission access that requires; When described electronics and IT products 10 send data access request signal and want the data address of access and data address in the described cache storage unit does not conform to, send a signal to described non-cache storage buffer cell 104 according to described data access request signal; And when not meeting the data address of described data access request signal requirement access in the non-cache storage buffer cell 104, again the signal that sends is transferred to described arbitration unit 106;
Described arbitration unit 106 is connected with described interface unit 102, storage unit 100 respectively; The signal that is used for sending according to described interface unit 102 is from storage unit 100 access datas;
Described non-cache storage buffer cell 104 is connected with described interface unit 102, described storage unit 100 respectively; Be used for requiring the data address of access according to the signal that described interface unit 100 the sends over described data access request signal that judges whether to be consistent, and with the described data access from described non-cache storage buffer cell 104 that requires access.For example: the data of access in storage unit, and the initial address of the data of access in storage unit is 300, if the occupied address total length of the data of access is stored the memory size of buffer cell smaller or equal to non-cache, then in data when described storage unit is sent to the process of described interface unit, (address is 300 with these data in advance, 301,302 ... end address until access data) write in the lump in the non-cache storage buffer cell, the access from described non-cache storage buffer cell of described interface unit is described to require remaining data in the data of access.
Also have, described arbitration unit 106 is further used for the signal access data from storage unit 100 according to described interface unit 102 transmissions; In data when described storage unit 100 is sent to the process of described interface unit 102, the data of getting of will seeking survival in advance are stored in the described non-cache storage buffer cell 104 from described storage unit 100, and indicate described interface unit 102 to require information remaining in the data of access to obtain from described non-cache storage buffer cell 104 to transmit with described.
Preferably, described electronics and IT products 10 be PC, notebook computer, palmtop computer, personal digital assistant, servomechanism and workstation one of them.
Preferably, described storage unit 100 be static random access memory (sram) cell, DRAM cell, synchronous dynamic random-access storage unit and high power speed information transmitting synchronous DRAM cell one of them.
Described data storage control end be CPU (central processing unit), microprocessing unit, circumscribed peripheral device and embedded peripheral device at least one of them.
Embodiment:
As shown in Figure 2, be the structured flowchart of example with the personal computer system for electronics and IT products in the utility model.In the present embodiment, memory cell data access system 1 of the present utility model is applied in the personal computer system 2.Wherein, by the basic framework of the shown described memory cell data access system 1 of Fig. 1 as can be known, described memory cell data access system 1 comprises: a storage unit 100, an interface unit 102, non-cache storage buffer cell 104 and an arbitration unit 106.
In addition, described personal computer system 2 also comprises: a processing unit 110, a circumscribed peripheral device 112 and an embedded peripheral device 114; Wherein, described processing unit 110 is used for by data transfer path transmission and reception information, and sends the signal of acquisition, decoding and execution command to memory cell data access system 1; Memory cell data access system 1 is unit or the module of described personal computer system 2.Described circumscribed peripheral device 112 be used for by as data transmission interface such as cable and as described in personal computer system 2 interconnect to carry out data transmission and have data processing function; Described embedded peripheral device 114 is used for being arranged in the described personal computer system 2 to be handled to carry out data.
The person of should be specified, in fact described personal computer system 2 should comprise more unit or device, required to keep normal operation, only mentions the part relevant with memory cell data access system 1 running of the present utility model in the present embodiment.That is to say that the data access control end is processing unit 110, circumscribed peripheral device 112 and embedded peripheral device 114 in the present embodiment.
Described storage unit 100 is to accept the control of processing unit 110, is the general data storage area of described personal computer system 2, in order to temporary instruction and data.In the present embodiment, described storage unit 100 is a random access memory (Random Access Memory; RAM), be a volatility and the readable storage unit of writing in nature.Described storage unit 100 helps described processing unit 110 that data are write self corresponding position according to the access instruction of described processing unit 110 from the input block input of keyboard or slide-mouse etc., realizes as the purposes of carrying out data access.In addition, can also initiatively data be sent to output unit, for example printer, display unit etc.
Described interface unit 102 interconnects with described processing unit 110, after receiving the signal that described processing unit 110 sends, as to as described in the data access request signal etc. of storage unit 100, the signal content that sends according to described processing unit 110, send a signal to one and described interface unit 102 interconnective unit or modules of appointment in the signal, use and carry out data transmission work.
Described non-cache storage buffer cell 104 plays the effect of caching data storage mechanism as non-cache storage area in the described storage unit 100.In the present embodiment, being set with a specific region in the described storage unit 100 is non-cache storage area, other modules of described memory cell data access system 1 and described personal computer system 2 or unit all must not be stored to the data that are stored in the described non-cache storage area in the cache storage unit of itself, if have one first rank cache storage unit in the described processing unit 110, then described processing unit 110 must not be stored to the data that are stored in the described non-cache storage area in the described first rank cache storage unit.The purpose of above-mentioned mechanism is to keep the consistance of system data between described memory cell data access system 1 and the described personal computer system 2.
Avoid aforesaid described processing unit 110, other mould resistances in described circumscribed peripheral device 112 and described embedded peripheral device 114 and the described personal computer system 2 or unit are had to by the data in the described non-cache storage area of described storage unit 100 ability accesses, and then cause the delay of data time, after described interface unit 102 received the data access request signal that described processing unit 110 sends, the data access request signal that described non-cache storage buffer cell 104 is used for sending according to described processing unit 110 judged whether to meet the data address that described data access request signal requires access.If have, then described non-cache storage buffer cell 104 carries out data access for described processing unit 110, increase the usefulness of data in the non-cache storage area of described processing unit 110 accesses, and because the data of described non-cache storage buffer cell 104 are logined the sum of the non-cache storage area described in (entry) number low background technology far away, so required hardware at the first general rank cache memory bank and second rank cache memory bank economization more, also need not be wasted the lifting that a large amount of costs can obtain system works usefulness relatively.
In addition, has consistance for keeping data stored in information stored in the described non-cache storage buffer cell 104 and the described storage unit 100.Then write fashionable when other module of described location information access system 1 and described personal computer system 2 or unit carry out data to described storage unit 100, described non-cache storage buffer cell 104 namely carries out the data address and itself the stored data address that require to write and compares, if the data address that has comparison to conform to, then in advance with described storage unit 100 in data upgrade synchronously, this moment, described processing unit 110 was when carrying out access at the data of described storage unit address, can be from 104 accesses of described non-cache storage buffer cell to data content correspondingly.
Described arbitration unit 106 is used for providing the module of described location information access system 1 and described personal computer system 2 or the unit carries out system resource allocation to the data access request of sending in described storage unit 100 mechanism.In the present embodiment, other moulds resistance in the described personal computer systems 2 such as described processing unit 110, described circumscribed peripheral device 112 and described embedded peripheral device 114 or unit be if send data access request to described storage unit 100 simultaneously, and then described arbitration unit 106 can distribute with regard to the existing systems resource at the data access request that each module or unit send.
Brought forward is described, should be specified, when requiring the data of the access of wanting not to be stored in described non-cache, data access that described processing unit 110 sends stores in the buffer cell 104, then described interface unit 102 sends memory cell access immediately and requires extremely described arbitration unit 106, allows described storage unit 100 that data are sent to described interface unit 102.Simultaneously, described non-cache storage buffer cell 104 must provide one second monitoring (Snooping) mechanism, namely in the process of data transmission, in advance processing unit 110 is wanted the data of access in described storage unit 100, to be stored in the described non-cache storage buffer cell 104, described processing unit 110 requires information remaining in the data of access just can store access the buffer cell 104 from described non-cache, at this moment, need not be from described storage unit 100 access data, increase system works usefulness to save data time.
The device that the utility model proposes is for utilizing general processor, digital signal processor, special IC (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, computer installation, or the access of the data that realize of the design of above-mentioned any combination.
Various illustrative logical block described in the device of the present utility model, or the unit can pass through general processor, digital signal processor, special IC (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the design of above-mentioned any combination realizes or operates described function.General processor can be microprocessor, and alternatively, this general processor also can be any traditional processor, controller, microcontroller or state machine.Processor also can realize by the combination of calculation element, for example digital signal processor and microprocessor, a plurality of microprocessors, Digital Signal Processor Core of one or more microprocessors associatings, or any other similarly configuration realize.
The step of the method described in the device of the present utility model can directly embed hardware, the software module of processor execution or the two combination.Software module can be stored in the storage medium of other arbitrary form in RAM storer, flash memory, ROM storer, eprom memory, eeprom memory, register, hard disk, moveable magnetic disc, CD-ROM or this area.Exemplarily, storage medium can be connected with processor, so that processor can read information from storage medium, and can deposit write information to storage medium.Alternatively, storage medium can also be integrated in the processor.Processor and storage medium can be arranged among the ASIC, and ASIC can be arranged in the user terminal.Alternatively, processor and storage medium also can be arranged in the different parts in the user terminal.
The technical scheme that the utility model proposes reduces the interior unit of electronics and IT products or module to the number of times of storage unit direct accessing data by a non-cache storage buffer cell mechanism, improves the work efficiency that data are handled; Simultaneously, by a non-cache storage buffer cell mechanism, continuous data to the described non-cache of access is in advance stored in the buffer cell, improves data processing efficiency.
Above-described embodiment; the purpose of this utility model, technical scheme and beneficial effect are further described; institute is understood that; the above only is embodiment of the present utility model; and be not used in and limit protection domain of the present utility model; all within spirit of the present utility model and principle, any modification of making, be equal to replacement, improvement etc., all should be included within the protection domain of the present utility model.
Claims (5)
1. electronics and IT products, comprise cache storage unit, storage unit and data storage control end, described data storage control end is connected with described cache storage unit, described cache storage unit links to each other with described storage unit, and the partial data in the described storage unit stores up in described cache memory cell; When described data storage control end sends the interior data address of data address that data access request signal wants access and described cache storage unit and conforms to, then directly get corresponding data from the cache memory cell; It is characterized in that,
Described electronics and IT products also comprise interface unit, non-cache storage buffer cell and arbitration unit;
Described interface unit is connected with non-cache storage buffer cell, arbitration unit respectively; Be used for receiving data storage control end and send the data of data access request signal and the transmission access that requires; When described data storage control end sends data access request signal and wants the data address of access and data address in the described cache storage unit does not conform to, send a signal to described non-cache according to described data access request signal and store buffer cell; And when not meeting the data address of described data access request signal requirement access in the non-cache storage buffer cell, again the signal that sends is transferred to described arbitration unit;
Described arbitration unit is connected with described interface unit, storage unit respectively; The signal that is used for sending according to described interface unit is from the storage unit access data;
Described non-cache storage buffer cell is connected with described interface unit, described storage unit respectively; Be used for requiring the data address of access according to the signal that described interface unit the sends over described data access request signal that judges whether to be consistent, and with the described data access from described non-cache storage buffer cell that requires access.
2. electronics and IT products as claimed in claim 1 is characterized in that, described arbitration unit further is connected with described non-cache storage buffer cell, and the signal that is used for sending according to described interface unit is from the storage unit access data; In data when described storage unit is sent to the process of described interface unit, the data of getting of will seeking survival in advance are stored in the described non-cache storage buffer cell from described storage unit, and indicate described interface unit to require information remaining in the data of access to obtain from described non-cache storage buffer cell to transmit with described.
3. electronics and IT products as claimed in claim 1 or 2 is characterized in that, described electronics and IT products be PC, notebook computer, palmtop computer, personal digital assistant, servomechanism and workstation one of them.
4. electronics and IT products as claimed in claim 1 or 2, it is characterized in that, described storage unit be static random access memory (sram) cell, DRAM cell, synchronous dynamic random-access storage unit and high power speed information transmitting synchronous DRAM cell one of them.
5. electronics and IT products as claimed in claim 1 or 2 is characterized in that, described data storage control end be CPU (central processing unit), microprocessing unit, circumscribed peripheral device and embedded peripheral device at least one of them.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2013201565221U CN203164960U (en) | 2013-04-01 | 2013-04-01 | Electronic information product |
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| CN2013201565221U CN203164960U (en) | 2013-04-01 | 2013-04-01 | Electronic information product |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090846A (en) * | 2013-04-01 | 2014-10-08 | 深圳芯力电子技术有限公司 | Electronic information product data accessing method and electronic information product |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104090846A (en) * | 2013-04-01 | 2014-10-08 | 深圳芯力电子技术有限公司 | Electronic information product data accessing method and electronic information product |
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Owner name: SHENZHEN XINLI ELECTRONIC TECHNOLOGY CO., LTD. Free format text: FORMER NAME: HAINAN XINLI SEMICONDUCTOR CO., LTD. |
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Address after: 518040 A, block 13Z, Fortune Plaza, 7060 Shennan Road, Shenzhen, Guangdong, Futian District Patentee after: SHENZHEN XINLI ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: 403 room 571924, incubator of Hainan eco Software Park, hi tech demonstration zone, Hainan old city Patentee before: HNXLI SEMICONDUCTOR Co.,Ltd. |
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Effective date of registration: 20201203 Address after: Room a-7982, building 3, 20 Yong'an Road, Shilong Economic Development Zone, Mentougou District, Beijing (cluster registration) Patentee after: Datang state investment information technology Co.,Ltd. Address before: 518040 A, block 13Z, Fortune Plaza, 7060 Shennan Road, Shenzhen, Guangdong, Futian District Patentee before: SHENZHEN XINLI ELECTRONIC TECHNOLOGY Co.,Ltd. |
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Granted publication date: 20130828 |