CN203134795U - Semiconductor structure - Google Patents
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- CN203134795U CN203134795U CN 201220557467 CN201220557467U CN203134795U CN 203134795 U CN203134795 U CN 203134795U CN 201220557467 CN201220557467 CN 201220557467 CN 201220557467 U CN201220557467 U CN 201220557467U CN 203134795 U CN203134795 U CN 203134795U
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Abstract
The utility model provides a semiconductor structure, comprising a substrate (100), gate stacks and source/drain regions (310), wherein the substrate (100) comprises a first direction and a second direction; the gate stacks are located on the substrate (100), and each gate stack is formed by stacking a first insulating layer (110) and a floating gate, a second insulating layer (170) and a control gate (180) from the bottom to the top in sequence; the side surfaces of the floating gates are respectively provided with more than two depressions in the first direction and the second direction; and the source/drain regions (310) are located in the substrate (100) on two sides of the gate stacks in the second direction. The semiconductor structure can reduce the capacitive coupling between two adjacent rows of units, and strengthens the capacitive coupling between control gates and the floating gates.
Description
Technical field
The utility model relates to technical field of semiconductors, relates in particular to a kind of semiconductor structure.
Background technology
The EEPROM(EEPROM (Electrically Erasable Programmable Read Only Memo)) but be the read-only memory (ROM) of user change, its can by be higher than common voltage be used for wipe and reprogrammed (rewriting).Unlike the EPROM chip, EEPROM does not need to take out from computer and can revise.In an EEPROM, when computer reprogrammed continually when in use, so the application of EEPROM more and more widely.
EEPROM adopts double-deck grid (two layers of polysilicon) structure, namely increase one deck polysilicon gate again below the Si-gate of the metal-oxide-semiconductor of routine, this layer Si-gate discord is extraneous to link to each other, and is insulated layer material fully (such as silicon dioxide, silicon nitrides etc.) and on every side isolate, this layer Si-gate just is floating boom.Electric charge in the floating boom can change by charge carrier (generally being electronics) turnover floating boom, and at the control gate making alive, the electronics in the substrate is transferred in the floating boom through oxide layer under the effect of voltage.Amount of charge will influence the threshold voltage of metal-oxide-semiconductor in the floating boom, and when the injection of electronics was arranged in the floating boom, for n type metal-oxide-semiconductor, threshold voltage was raised.Different threshold voltages is corresponding to different store statuss.Along with the development of modern technologies, people are more and more higher to the requirement of memory span, so memory density is increasing, the distance between corresponding memory cell just becomes more and more littler.When this distance little to a certain degree the time, the problem of the capacitive coupling effect between consecutive storage unit just becomes and highlights, it can cause the threshold voltage between consecutive storage unit unstable or uncertain, this has seriously limited the further lifting of storage density, finds a way to solve this problem so need badly.
Along with the development of modern technologies, people are more and more higher to the requirement of memory span, so memory density is increasing, the distance between corresponding memory cell just becomes more and more littler.When this distance is little to a certain degree the time, the problem of the capacitive coupling effect between consecutive storage unit just becomes and highlights, and this has seriously limited the further lifting of storage density, finds a way to solve this problem so need badly.
The utility model content
The utility model provides a kind of semiconductor structure that can address the above problem and manufacture method thereof.
According to an aspect of the present utility model, a kind of manufacture method of semiconductor structure is provided, this method may further comprise the steps:
A) provide substrate 100, described substrate 100 comprises first direction and second direction;
B) form grid at described substrate 100 and pile up, described grid pile up and comprise first insulating barrier 110 and the floating boom successively;
C) at described first direction floating boom is carried out etching, make the sidewall of described floating boom form at least two depressions at first direction;
D) deposit forms second insulating barrier 170 and control gate 180 on floating boom, and described second insulating barrier 170 and control gate 180 cover the side of described floating boom at first direction;
E) on second direction, described floating boom is carried out etching, make the sidewall of described floating boom form at least two depressions in second direction;
F) form source/drain region 310 in the stacking gate both sides.
According to another aspect of the present utility model, a kind of semiconductor structure also is provided, comprising:
Grid pile up, and are positioned on the described substrate 100, and described grid pile up to be stacked gradually from the bottom up by first insulating barrier 110 and floating boom, second insulating barrier 170 and control gate 180 and form;
Described floating boom side has plural depression respectively on described first direction and second direction;
Source/drain region 310 is arranged in the substrate 100 that described grid are stacked on the second direction both sides.
Wherein said floating boom comprises first successively to the layer 5 material layer on first insulating barrier (110).
Wherein, in described floating boom side, the described second and the 4th material layer forms depression with respect to the first, the 3rd and the 5th material layer, and the cup depth of described the 4th material layer is greater than the cup depth of described second material layer.
Compared with prior art, the utility model is etched into plural concave shape in bit line direction with the floating boom sidewall, can reduce the capacitive coupling between the unit, and at word-line direction by can tighten control capacitive coupling between grid and the floating boom of the floating boom that wraps side convex-concave shape with second insulating barrier and control gate.By above method, can effectively reduce the parasitic couplings effect between the consecutive storage unit, be conducive to further reduce memory cell pitch from and increase the integrated scale of circuit.
Description of drawings
By reading the detailed description of doing with reference to the following drawings that non-limiting example is done, it is more obvious that other features, objects and advantages of the present utility model will become.
Fig. 1 is the flow chart according to the semiconductor structure manufacture method of embodiment of the present utility model;
Fig. 2 be to Figure 18 for make the schematic diagram in each stage of semiconductor structure according to flow process shown in Figure 1;
Wherein, Fig. 2, Fig. 3, Fig. 6, Fig. 7, Fig. 8, Figure 10, Figure 11, Figure 12, Figure 13 are the generalized section of word-line direction intercepting;
The generalized section that Figure 16, Figure 17, Figure 18 intercept for bit line direction;
Fig. 4, Fig. 5, Fig. 9, Figure 14, Figure 15 are vertical view.
Embodiment
Describe embodiment of the present utility model below in detail.
The example of described embodiment is shown in the drawings, and wherein identical or similar label is represented identical or similar elements or the element with identical or similar functions from start to finish.Be exemplary below by the embodiment that is described with reference to the drawings, only be used for explaining the utility model, and can not be interpreted as restriction of the present utility model.Disclosing hereinafter provides many different embodiment or example to be used for realizing different structure of the present utility model.Of the present utility model open in order to simplify, hereinafter parts and the setting to specific examples is described.Certainly, they only are example, and purpose does not lie in restriction the utility model.In addition, the utility model can be in different examples repeat reference numerals and/or letter.This repetition is in order to simplify and purpose clearly, itself not indicate the relation between the various embodiment that discuss of institute and/or the setting.In addition, various specific technology and examples of material that the utility model provides, but those of ordinary skills can recognize the property of can be applicable to of other technologies and/or the use of other materials.
According to an aspect of the present utility model, provide a kind of manufacture method of manufacture method, particularly a kind of memory device of semiconductor structure.Below, will specifically describe by the method that Fig. 1 of embodiment of the present utility model forms semiconductor structure in conjunction with Fig. 2 to Figure 18.As shown in Figure 1, manufacture method provided by the utility model may further comprise the steps:
In step S101, substrate 100 is provided, described substrate 100 comprises word line and bit line both direction, described word line is vertical mutually usually with the bit line both direction.Many the word line connects memory cell array at word-line direction, and multiple bit lines connects described memory cell array in bit line direction.Wherein when word line and bit line, can read the memory cell that is connected with bit line with described word line and bit line infall and selected word line in elected.
The concrete manufacture method of described memory device is as follows, as shown in Figure 2, at first provides substrate 100.In the present embodiment, described substrate 100 is silicon substrate, for example silicon wafer.According to the known designing requirement of prior art (for example P type substrate or N-type substrate), substrate 100 can comprise various doping configurations.In other embodiments, described substrate 100 can comprise other basic semiconductors, as III-V family material, for example germanium.Perhaps, substrate 100 can comprise compound semiconductor, for example carborundum, GaAs, indium arsenide.Typically, substrate 100 can have but be not limited to the thickness of about hundreds of micron, for example can be in the thickness range of 400 μ m-800 μ m.
We give described substrate 100 regulation word line and bit line both directions, and as shown in Figure 4, in ensuing narration, we can carry out detailed narration to whole manufacturing process on this both direction.
In step S102, form grid at described substrate 100 and pile up, described grid pile up and comprise first insulating barrier 110 and the floating boom successively.
Concrete, as shown in Figure 2, deposit one deck first insulating barrier 110 on described substrate 100 at first, available deposition process comprises PVD, CVD, ALD, PLD, MOCVD, PEALD, sputter, molecular beam deposition (MBE) etc., perhaps directly uses the method for thermal oxidation at substrate (100) growth one deck oxide.
Generate floating boom at described first insulating barrier 110 afterwards, concrete manufacture method be deposit formation at least five layer of material successively on first insulating barrier 110, for example comprise: first conductive layer 120, semiconductor layer 130,138, conductive material layer 135 and second conductive layer 140, wherein first conductive layer 120 and second conductive layer 140 also can replace with semiconductor material layer.As shown in Figure 3.The material of described first conductive layer 120, conductive material layer 135 and second conductive layer 140 is Poly-Si, Ti, Co, Ni, Al, W, alloy, metal silicide or its combination; Described semiconductor layer 130 and 138 material have etching selection with respect to first conductive layer 120, conductive material layer 135, second conductive layer 140. Semiconductor layer 130 and 138 for example can be SiGe, and the ratio of regulating SiGe can be controlled the etch rate of semiconductor layer 130 and 138.This is to prepare for ensuing etch step.Described floating gate layer gross thickness is 50-80nm, and wherein semiconductor layer 130 and 138 thickness sum account for 40～60% of floating gate layer gross thickness.
After 140 deposits of second conductive layer form, need again it to be carried out etching, apply photoresist 150 at first thereon, as shown in Figure 4.Be that mask carries out graphical etching to first insulating barrier 110 and floating gate layer with photoresist 150 afterwards, expose substrate 100 until the part that is not covered by photoresist, vertical view as shown in Figure 5, along the profile of word-line direction as shown in Figure 6.Concrete lithographic method can be selected dry etching such as reactive ion etching RIE or wet etching for use.
In an embodiment of the present utility model, at etching first insulating barrier 110 and the floating gate layer, expose after the substrate 100, composition with photoresist continues etching is carried out in substrate 100 parts again, and as shown in Figure 7, etching depth is 100-300nm.The photoresist that is positioned on floating gate layer surface and the substrate can be removed, backfill oxide in described groove afterwards, stop until the position of height a little more than first insulating barrier 110, to form fleet plough groove isolation structure 160, vertical view as shown in Figure 9, its profile as shown in Figure 8, the section of Fig. 8 is the section of the A-A line intercepting in Fig. 9.
In step S103, at described word-line direction selective etch is carried out in the floating boom side, make that the side on the floating boom word-line direction has at least two depressions, with the surface area that is coupled between the control gate that increases floating boom and form afterwards.
Concrete, select corresponding lithographic method to come semiconductor layer 130,138 is carried out selective etch according to the material of five layers of selected before floating gate layer, as shown in figure 10.At this moment semiconductor layer 130,138 very fast with respect to the etching speed of first conductive layer 120, conductive material layer 135 and second conductive layer 140, therefore semiconductor layer 130,138 forms depression with respect to first conductive layer 120, conductive material layer 135 and second conductive layer 140, and first conductive layer 120, conductive material layer 135 and second conductive layer 140 are with respect to semiconductor layer 130,138 projections.
But, in follow-up PROCESS FOR TREATMENT, such as wet-cleaned, chemical-mechanical planarization etc., when the semiconductor layer 130 of recess undersized and a little less than causing mechanical strength the time, rupture easily, for head it off the utility model also provides another one embodiment.As shown in figure 11, change its corrosion rate by the SiGe combination of carrying out different proportion from top to bottom, then corrosion rate is fast than semiconductor layer 130 height of bottom for semiconductor layer 138 germanium concentrations on top, can form bucking ladder.The bucking ladder that this is low wide and up narrow can increase the mechanical strength of floating boom lower end, and in follow-up PROCESS FOR TREATMENT, the depression at semiconductor layer 130 places is not easy fracture than the young pathbreaker.
In step S104, deposit forms second insulating barrier 170 and control gate 180 on the floating boom after the etching, and described second insulating barrier 170 and control gate 180 wrap floating boom at word-line direction.
Concrete, form second insulating barrier 170 on floating boom surface and side, described second insulating barrier 170 wraps floating boom at word-line direction.Described second insulating barrier 170 can be formed by three layers, is respectively oxide skin(coating), nitride layer and oxide skin(coating).
After described second insulating barrier 170 formed, deposit thereon formed one deck control gate 180 again, and described control gate 180 will wrap floating boom and second insulating barrier 170, profile as shown in figure 13, vertical view is as shown in figure 14.Material is electric conducting material Poly-Si, Ti, Co, Ni, Al, W, alloy or metal silicide and combination thereof.Can carry out chemical mechanical polish process to its top after forming control gate, make its upper flat.Because second insulating barrier 170 and control gate 180 wrap floating boom, and the floating boom middle part is etched to sunk structure, has therefore increased coupling area between control gate 180 and the floating boom, increases coupling capacitance, improves control gate to the control of floating boom, increases device performance.At this moment, with a plurality of floating boom sidewall parcels of same row, the control gate of each floating boom links together control gate 180, forms same current potential on word-line direction.
In step S105, form the floating boom array, in bit line direction floating boom is carried out selective etch then, make floating boom medial recess and two ends projection equally, to increase the coupling distance between the adjacent floating boom.
Concrete, at first form many photoresists along word-line direction and cover control gate 180 tops, semiconductor device is carried out control gate 180, second insulating barrier, floating boom and first insulating barrier of etching to remove the photoresist both sides, make bar shaped photoresist exposed at both sides go out substrate 100 or shallow trench isolation from 160, after removing photoresist vertical view as shown in figure 15, the profile of the B-B line in Figure 15 is as shown in figure 16.Photoresist is removed after also can being chosen in next step selective etch again.
Afterwards, according to similar mode as mentioned, in bit line direction the floating boom sidewall is carried out selective etch.Concrete, select corresponding lithographic method to come semiconductor layer 130,138 is carried out selective etch according to the material of at least five layers of selected before floating gate layer.At this moment semiconductor layer 130,138 very fast with respect to the etching speed of first conductive layer 120, conductive material layer 135 and second conductive layer 140, therefore semiconductor layer 130 and 138 forms depression with respect to first conductive layer 120, conductive material layer 135 and second conductive layer 140, and first conductive layer 120, conductive material layer 135 and second conductive layer 140 are with respect to the relative projection with 138 of semiconductor layer 130.Profile as shown in figure 17 after finishing.The control gate 180 of adjacent two row's floating booms may be connected to different potentials, therefore may have electromagnetic interference between adjacent two row's floating booms.The utility model corrodes into the dentation of convex-concave by the sidewall with adjacent two row's floating booms, has increased distance and electric capacity between the adjacent floating boom, reduces and disturbs.
Above be that five-layer structure is that example describes with the floating boom, in fact according to the utility model, can also form the floating gate structure more than five layers.The multi-layer floating gate structure is through behind the selective etch, and the side in the cross section of described floating boom forms the zigzag convex-concave structure, can realize increasing the floating boom surface area equally and increase the coupling distance between the adjacent devices and the purpose that reduces to disturb between device.
In step S106, form source/drain region 310 in the stacking gate both sides.
Particularly, as shown in figure 18, by in substrate 100, injecting P type or N-type alloy or impurity, pile up both sides at described pseudo-grid and form source/drain region 310.The type of preferred described semiconductor structure is NMOS, and then described source-drain area 310 doping types are N-type.
Then described semiconductor structure is annealed, with the doping in activation of source/drain region 310, annealing can be adopted and comprise that other suitable methods such as short annealing, spike annealing form.
Compared with prior art, the utlity model has following advantage: the utility model is etched into floating boom the shape of intermediate recess two ends projection, can be increased in the coupling distance between the adjacent floating boom of bit line direction, reduce the capacitive coupling between two row unit, and adorn can tighten control capacitive coupling between grid and the floating boom of floating boom at word-line direction by wrap tooth with second insulating barrier and control gate.By above two methods, can effectively reduce the parasitic couplings effect, this help further to increase the integrated scale of circuit and reduce memory cell pitch from.
According to another aspect of the present utility model, a kind of semiconductor structure also is provided, this semiconductor structure comprises:
Grid pile up, and are positioned on the described substrate 100, and described grid pile up to be stacked gradually from the bottom up by first insulating barrier 110 and floating boom, second insulating barrier 170 and control gate 180 and form.At the profile of word-line direction as shown in figure 10, at the profile of bit line direction as shown in figure 18.
Wherein said floating boom is made of at least five layer of material on first insulating barrier 110, for example has first conductive layer 120, semiconductor layer 130,138, conductive material layer 135 and second conductive layer 140 to pile up and forms.Wherein first conductive layer 120 and second conductive layer 140 also can be replaced by semiconductor layer.The floating gate layer gross thickness is 50-80nm, and the thickness of wherein said semiconductor layer 130 accounts for 40～60% of floating gate layer gross thickness.
Described floating boom is sandwich construction, and its side in the cross section of word line and bit line direction has at least two sunk parts.For example, shown in Figure 10, semiconductor layer 130 and semiconductor layer 138 places form depression with respect to adjacent aspect.Preferably, as shown in figure 11, the depression at semiconductor layer 138 places is bigger than the depression at semiconductor layer 130 places, to increase the mechanical strength of floating boom bottom.The side in described cross section can form the zigzag of convex-concave.And be formed on second insulating barrier 170 on the floating boom and control gate 180 cover floating boom at word-line direction upper surface and side, and at bit line direction second insulating barrier 170 and 180 upper surfaces that cover floating boom of control gate, namely the side surface of floating boom is not covered by second insulating barrier 170 and control gate 180.
Wherein, the material of described floating boom and control gate is Poly-Si, Ti, Co, Ni, Al, W, alloy, metal silicide or its combination, and concrete semiconductor layer 130,138 material have selectivity with respect to the material of first conductive layer 120, second conductive layer 140 and conductive material layer 135.First conductive layer 120 and second conductive layer 140 also can replace with semiconductor material layer.As shown in Figure 3.The material of described first conductive layer 120, conductive material layer 135 and second conductive layer 140 is Poly-Si, Ti, Co, Ni, Al, W, alloy, metal silicide or its combination; Semiconductor layer 130 and 138 for example can be SiGe, and the ratio of regulating SiGe can be controlled the etch rate of semiconductor layer 130 and 138.As described in Figure 12, make that the etch rate of semiconductor layer 138 is faster than the etch rate of semiconductor layer 130, to reduce the etching to bottom material layer, increase the mechanical strength of floating boom bottom.
Described second insulating barrier 170 preferably is made up of three-decker at least, for example is respectively the three-decker of oxide skin(coating), nitride layer and oxide skin(coating).
Source/drain region 310 is arranged in the substrate (100) that described grid pile up both sides in bit line direction, according to the type of semiconductor structure, comprises P type or N-type alloy or impurity in described source/drain region 310, and for example, for the PMOS device, impurity is boron; For nmos device, impurity is arsenic.Wherein, the doping content scope in described source/drain region 310 is about 5 * 10
18Cm
-3To 5 * 10
20Cm
-3, its junction depth scope is about 3nm to 50nm.The type of preferred described semiconductor structure is NMOS, and then described source-drain area 310 doping types are N-type, as shown in figure 18.
Fleet plough groove isolation structure 160 is arranged along the bit line direction bar shaped, is arranged in substrate 100, and material is SiO
2, Si
3N
4Deng megohmite insulant, thickness is 100-300nm, as shown in figure 10.
Though describe in detail about example embodiment and advantage thereof, be to be understood that under the situation of the protection range that does not break away from the restriction of spirit of the present utility model and claims, can carry out various variations, substitutions and modifications to these embodiment.For other examples, when those of ordinary skill in the art should understand easily in keeping the utility model protection range, the order of processing step can change.
In addition, range of application of the present utility model is not limited to technology, mechanism, manufacturing, material composition, means, method and the step of the specific embodiment of describing in the specification.From disclosure of the present utility model, to easily understand as those of ordinary skill in the art, for the technology, mechanism, manufacturing, material composition, means, method or the step that have existed or be about to later on develop at present, wherein they are carried out the corresponding embodiment cardinal principle identical functions of describing with the utility model or obtain identical substantially result, can use them according to the utility model.Therefore, the utility model claims are intended to these technology, mechanism, manufacturing, material composition, means, method or step are included in its protection range.
Claims (4)
1. semiconductor structure comprises:
Substrate (100), described substrate (100) comprises first direction and second direction;
Grid pile up, and are positioned on the described substrate (100), and described grid pile up to be stacked gradually from the bottom up by first insulating barrier (110) and floating boom, second insulating barrier (170) and control gate (180) and form;
Described floating boom side has plural depression respectively on described first direction and second direction;
Source/drain region (310) is arranged in the substrate (100) that described grid pile up both sides in second direction.
2. semiconductor structure according to claim 1, wherein said floating boom comprises first successively to the layer 5 material layer on first insulating barrier (110).
3. semiconductor structure according to claim 1, wherein, described second insulating barrier (170) and control gate (180) cover the side of floating boom at first direction.
4. semiconductor structure according to claim 1, wherein, in described floating boom side, the described second and the 4th material layer forms depression with respect to the first, the 3rd and the 5th material layer, and the cup depth of described the 4th material layer is greater than the cup depth of described second material layer.
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| CN 201220557467 CN203134795U (en) | 2012-10-26 | 2012-10-26 | Semiconductor structure |
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| CN 201220557467 CN203134795U (en) | 2012-10-26 | 2012-10-26 | Semiconductor structure |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794564A (en) * | 2012-10-26 | 2014-05-14 | 李迪 | Semiconductor structure and manufacturing method thereof |
| CN105140301A (en) * | 2015-08-19 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory structure and fabrication method thereof |
| CN105575969A (en) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacture method thereof and electronic device |
| CN110047836A (en) * | 2019-04-18 | 2019-07-23 | 武汉新芯集成电路制造有限公司 | Flush memory device and its manufacturing method |
-
2012
- 2012-10-26 CN CN 201220557467 patent/CN203134795U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103794564A (en) * | 2012-10-26 | 2014-05-14 | 李迪 | Semiconductor structure and manufacturing method thereof |
| CN105575969A (en) * | 2014-10-17 | 2016-05-11 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacture method thereof and electronic device |
| CN105575969B (en) * | 2014-10-17 | 2020-06-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device, manufacturing method thereof and electronic device |
| CN105140301A (en) * | 2015-08-19 | 2015-12-09 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory structure and fabrication method thereof |
| CN105140301B (en) * | 2015-08-19 | 2019-03-12 | 武汉新芯集成电路制造有限公司 | Floating gate type flash memory structure and preparation method thereof |
| CN110047836A (en) * | 2019-04-18 | 2019-07-23 | 武汉新芯集成电路制造有限公司 | Flush memory device and its manufacturing method |
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Granted publication date: 20130814 Termination date: 20171026 |