CN203118416U - Shifting register and display device - Google Patents
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- CN203118416U CN203118416U CN 201320090139 CN201320090139U CN203118416U CN 203118416 U CN203118416 U CN 203118416U CN 201320090139 CN201320090139 CN 201320090139 CN 201320090139 U CN201320090139 U CN 201320090139U CN 203118416 U CN203118416 U CN 203118416U
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Abstract
The utility model discloses a shifting register and a display device. The shifting register comprises an input module, a pull-down module, an opposite-phase module and a first pull-up module. The input module is in response to a first clock signal so as to supply the voltage of an input signal to a pull-down node, wherein the pull-down node is served as the output node of the input module. The pull-down module is used for storing the voltage of the input signal and then supplying a second clock signal to an output terminal in response to the pull-down node. The opposite-phase module is in response to the pull-down node to supply the voltage of the positive or negative electrode of a power supply to a first pull-up node. The first pull-up module is in response to the first pull-up node to supply the voltage of the positive electrode of the power supply to the output terminal. According to the technical scheme of the utility model, one part or all of the dangling nodes of the shifting register are improved to be not dangled any more. Or, the source and drain electrodes of a thin-film transistor, which are influenced by the dangling nodes of the shifting register, are controlled to improve the output stability of the shifting register.
Description
Technical Field
The utility model relates to a liquid crystal display drive technical field especially relates to a shift register and display device.
Background
Flat panel displays are widely used because of their thinness and energy conservation. Shift registers are used in most flat panel displays, and a gate driving device is integrated into a shift register implemented by a liquid crystal on array (GOA) method, so that a gate driving IC can be omitted, and a manufacturing process can be reduced, thereby reducing the manufacturing cost of the flat panel display and shortening the manufacturing period to a certain extent. The GOA technology has been widely used in flat panel display manufacturing in recent years. The output stability of the GOA has been a concern in the design of the GOA.
Fig. 1 is a basic unit of a GOA in the prior art, which is composed of 6 thin film transistors M12, M19, M20, M21, M22, and 1 capacitor C1, where CLK and CLKB are clock signals, VGH is a power supply positive voltage, VGL is a power supply negative voltage, STV is an input signal, and a node B is a pull-down node; in practical application, the mutual interference of the residual voltage signals of the previous stage on the node a and the node C of the GOA unit affects whether the thin film transistor M19 is turned on, so that the shift register cannot stably work for a long time, and the OUTPUT signal of the OUTPUT terminal OUTPUT is unstable.
SUMMERY OF THE UTILITY MODEL
The utility model aims at providing a shift register and display device, this shift register improves the unsettled node in the operation process, solves the unstable problem of shift register output.
The utility model aims at realizing through the following technical scheme:
an embodiment of the utility model provides a shift register, this shift register includes: the device comprises an input module, a pull-down module, an inverting module and a first pull-up module; wherein,
the input module responds to a first clock signal and provides an input signal voltage to a pull-down node, wherein the pull-down node is an output node of the input module;
the pull-down module stores the input signal voltage and provides a second clock signal to an output terminal in response to an output voltage of the pull-down node;
the inverting module responds to the output voltage of the pull-down node and provides the power supply positive electrode voltage or the power supply negative electrode voltage to the first pull-up node;
the first pull-up module supplies the power supply positive electrode voltage to the output terminal in response to the output voltage of the first pull-up node.
Preferably, the input module includes:
and a gate of the first thin film transistor is connected with a first clock signal end, a source of the first thin film transistor is connected with an input signal end, and a drain of the first thin film transistor is used as the output node of the input module, namely the pull-down node.
Preferably, the pull-down module includes:
a second thin film transistor, wherein the grid electrode of the second thin film transistor is connected with the pull-down node, the source electrode of the second thin film transistor is connected with a second clock signal end, and the drain electrode of the second thin film transistor is connected with the output terminal;
and the capacitor is connected between the pull-down node and the drain electrode of the second thin film transistor.
Preferably, the inverting module includes:
a grid electrode of the third thin film transistor is connected with the pull-down node, a source electrode of the third thin film transistor is connected with a positive voltage end of a power supply, and a drain electrode of the third thin film transistor is connected with the first pull-up node;
and the grid electrode and the drain electrode of the fourth thin film transistor are connected with the negative voltage end of the power supply, and the source electrode of the fourth thin film transistor is connected with the first pull-up node.
Preferably, the first drawing-up module includes:
and the grid electrode of the fifth thin film transistor is connected with the first pull-up node, the source electrode of the fifth thin film transistor is connected with the positive voltage end of the power supply, and the drain electrode of the fifth thin film transistor is connected with the output terminal.
Preferably, the power supply further comprises a second pull-up module, which is responsive to the output voltage of the pull-down node and the input signal, and supplies the power supply positive electrode voltage to the output terminal.
Preferably, the second pull-up module includes:
a sixth thin film transistor, a gate of which is connected to the pull-down node, a source of which is connected to the input signal terminal, and a drain of which is connected to the second pull-up node;
and the grid electrode of the seventh thin film transistor is connected with the second pull-up node, the source electrode of the seventh thin film transistor is connected with the positive voltage end of the power supply, and the drain electrode of the seventh thin film transistor is connected with the output terminal.
An embodiment of the present invention provides a display device, including cascaded shift register as described above.
The embodiment of the utility model has the following beneficial effects: the shift register improves part or all of suspended nodes to ensure that the nodes are not suspended any more; or controlling the source and drain electrodes of the thin film transistor influenced by the suspended node; thereby improving the stability of the shift register output.
Drawings
FIG. 1 is a schematic diagram of a prior art basic cell shift register;
fig. 2 is a schematic structural diagram of a shift register according to a first embodiment of the present invention;
fig. 3 is a timing diagram of control signals of the shift register according to the embodiment of the present invention;
fig. 4 is a schematic structural diagram of a shift register according to a second embodiment of the present invention;
fig. 5 is a schematic structural diagram of a cascaded shift register of a display device according to a third embodiment of the present invention;
fig. 6 is a timing diagram of control signals of the cascaded shift register according to the third embodiment of the present invention.
The reference numerals in figures 2 to 4 are as follows:
101. an input module 101; m29 first thin film transistor;
102. a pull-down module 102; m28 second thin film transistor;
103. an inversion module 103; m24 third thin film transistor;
104. a first pull-up module 104; m26 fourth thin film transistor;
105. a second pull-up module 105; m27 fifth thin film transistor;
m25 sixth thin film transistor; m30 seventh thin film transistor.
Detailed Description
The following describes in detail the implementation process of the embodiments of the present invention with reference to the drawings.
An embodiment of the present invention provides a shift register, as shown in fig. 2, the shift register includes: an input module 101, a pull-down module 102, an inversion module 103 and a first pull-up module 104; wherein,
an input block 101 for providing an input signal STV to a pull-down node B in response to a first clock signal CLK, wherein the pull-down node B is an output node of the input block 101;
a pull-down module 102 storing the input signal STV and an OUTPUT voltage in response to a pull-down node B point, and providing a second clock signal CLKB to an OUTPUT terminal OUTPUT;
the inverting module 103 responds to the output voltage of the pull-down node B point and provides the power supply anode voltage VGH or the power supply cathode voltage VGL to the first pull-up node A point;
the first pull-up module 104 supplies the power source positive electrode voltage VGH to the OUTPUT terminal OUTPUT in response to the OUTPUT voltage at the first pull-up node a.
Preferably, the input module 101 includes:
the first thin film transistor M29 has a gate connected to the first clock signal CLK terminal, a source connected to the input signal STV terminal, and a drain serving as the output node of the input block 101, i.e., the node B of the pull-down node.
Preferably, the pull-down module 102 includes:
a second thin film transistor M28, having a gate connected to the pull-down node B, a source connected to the end of the second clock signal CLKB, and a drain connected to the OUTPUT terminal OUTPUT;
and a capacitor C2 connected between the pull-down node B and the drain of the second TFT M28.
Preferably, the inverting module 103 includes:
a third thin film transistor M24, the grid of which is connected with the point B of the pull-down node, the source of which is connected with the voltage end VGH of the positive electrode of the power supply, and the drain of which is connected with the point A of the first pull-up node;
the gate and the drain of the fourth thin film transistor M26 are connected to the terminal of the power supply cathode voltage VGL, and the source is connected to the first pull-up node a.
Preferably, the first drawing-up module 104 includes:
the fifth thin film transistor M27 has a gate connected to the first pull-up node a, a source connected to the positive power supply voltage VGH terminal, and a drain connected to the OUTPUT terminal OUTPUT.
Referring to the control timing diagram shown in fig. 3, a driving method of a shift register according to an embodiment of the present invention includes:
in the first stage t1, the first clock signal CLK is low, the second clock signal CLKB is high, and the input signal STV is low. Since the first clock signal CLK is at a low level, the first thin film transistor M29 is turned on, and a low level signal of the input signal STV is input to the pull-down node B, and the low level of the pull-down node B turns on the second thin film transistor M28 and the third thin film transistor M24; the turned-on third thin film transistor M24 outputs the high level of the power supply positive electrode voltage VGH to the first pull-up node a, the high level of the first pull-up node a turning off the fifth thin film transistor M27; the turned-on second thin film transistor M28 OUTPUTs a high level signal of the second clock signal CLKB to the OUTPUT terminal OUTPUT of the shift register.
At the second stage t2, the first clock signal CLK is at a high level, the second clock signal CLKB is at a low level, and the input signal STV is at a high level; the low level at the node B is held by the capacitor C2, and the second thin film transistor M28 is turned on; the turned-on second thin film transistor M28 OUTPUTs the low level of the second clock signal CLKB to the OUTPUT terminal OUTPUT, and also functions to pull down the potential at the pull-down node B.
At this time, the low level of the node B is pulled down, so that the third tft M24 is in a conducting state, and the power supply positive voltage VGH is OUTPUT to the first pull-up node a, so that the fifth tft M27 is turned off, thereby ensuring that the OUTPUT terminal OUTPUT receives the stable signal of the second tft M28.
In the third stage t3, the first clock signal CLK is at a low level, the second clock signal CLKB is at a high level, and the input signal STV is at a high level; since the first clock signal CLK is at a low level, the first thin film transistor M29 is turned on, the turned-on first thin film transistor M29 outputs a high level of the input signal STV to the pull-down node B, and the high level of the pull-down node B turns off the second thin film transistor M28 and the third thin film transistor M24. The fourth thin film transistor M26 receives the low level of the power low voltage signal VGL and OUTPUTs the low level to the first pull-up node a, so that the fifth thin film transistor M27 is turned on, and the turned-on fifth thin film transistor M27 OUTPUTs the high level of the power high voltage signal VGH to the OUTPUT terminal OUTPUT.
A fourth stage t4, in which the first clock signal CLK is at a high level, the second clock signal CLKB is at a low level, and the input signal STV is at a high level; the pull-down node B still maintains the high level of the third stage t3 through the capacitor C2, so that the second thin film transistor M28 and the third thin film transistor M24 are in an off state. The low level of the second clock signal CLKB cannot be OUTPUT to the OUTPUT terminal OUTPUT through the second thin film transistor M28, and thus does not affect the stability of the OUTPUT signal.
Meanwhile, the fourth tft M26 receives the low level of the power low voltage signal VGL and OUTPUTs the low level to the first pull-up node a, such that the fifth tft M27 is turned on, and the turned-on fifth tft M27 OUTPUTs the high level of the power high voltage signal VGH to the OUTPUT terminal OUTPUT.
In a fifth stage t5, the first clock signal CLK is at a low level, the second clock signal CLKB is at a high level, and the input signal STV is at a high level; as in the case of the third stage.
The third stage and the fourth stage are repeated in the subsequent stages, and the high level is output until the low level of the input signal STV is received again, and output is performed according to the timing at which the low level of the input signal STV is received.
The embodiment of the utility model has the following beneficial effects: the shift register improves part or all of suspended nodes to ensure that the nodes are not suspended any more; or controlling the source and drain electrodes of the thin film transistor influenced by the suspended node; thereby improving the stability of the shift register output.
The embodiment of the utility model provides a second provides a shift register, as shown in FIG. 4, this shift register includes: an input module 101, a pull-down module 102, an inversion module 103, a first pull-up module 104, and a second pull-up module 105; wherein,
an input block 101 for providing an input signal STV to a pull-down node B in response to a first clock signal CLK, wherein the pull-down node B is an output node of the input block 101;
a pull-down module 102 storing the input signal STV and an OUTPUT voltage in response to a pull-down node B point, and providing a second clock signal CLKB to an OUTPUT terminal OUTPUT;
the inverting module 103 responds to the output voltage of the pull-down node B point and provides the power supply anode voltage VGH or the power supply cathode voltage VGL to the first pull-up node A point;
a first pull-up module 104 supplying the power source positive electrode voltage VGH to the OUTPUT terminal OUTPUT in response to the OUTPUT voltage at the first pull-up node a;
the second pull-up module 105 supplies the power source positive electrode voltage VGH to the OUTPUT terminal OUTPUT in response to the OUTPUT voltage at the pull-down node B and the input signal STV.
Preferably, the input module 101 includes:
the first thin film transistor M29 has a gate connected to the first clock signal CLK, a source connected to the input signal STV, and a drain serving as the output node of the input block 101, i.e., the node B of the pull-down node.
Preferably, the pull-down module 102 includes:
a second thin film transistor M28, having a gate connected to the pull-down node B, a source connected to the end of the second clock signal CLKB, and a drain connected to the OUTPUT terminal OUTPUT;
and a capacitor C2 connected between the pull-down node B and the drain of the second TFT M28.
Preferably, the inverting module 103 includes:
a third thin film transistor M24, the grid of which is connected with the point B of the pull-down node, the source of which is connected with the voltage end VGH of the positive electrode of the power supply, and the drain of which is connected with the point A of the first pull-up node;
the gate and the drain of the fourth thin film transistor M26 are connected to the terminal of the power supply cathode voltage VGL, and the source is connected to the first pull-up node a.
Preferably, the first drawing-up module 104 includes:
the fifth thin film transistor M27 has a gate connected to the first pull-up node a, a source connected to the positive power supply voltage VGH terminal, and a drain connected to the OUTPUT terminal OUTPUT.
Preferably, the second drawing-up module 105 includes:
a sixth thin film transistor M25, having a gate connected to the pull-down node B, a source connected to the input signal STV terminal, and a drain connected to the second pull-up node C;
the seventh thin film transistor M30 has a gate connected to the second pull-up node C, a source connected to the positive power supply voltage VGH terminal, and a drain connected to the OUTPUT terminal OUTPUT.
Referring to the control timing diagram shown in fig. 3, a second embodiment of the present invention provides a method for driving a shift register, including:
in the first stage t1, the first clock signal CLK is low, the second clock signal CLKB is high, and the input signal STV is low. Since the first clock signal CLK is at a low level, the first thin film transistor M29 is turned on, and a low level signal of the input signal STV is input to the pull-down node B, and the low level of the pull-down node B turns on the second thin film transistor M28 and the third thin film transistor M24; the turned-on third thin film transistor M24 outputs the high level of the power supply positive electrode voltage VGH to the first pull-up node a, and the high level of the first pull-up node a causes the fifth thin film transistor M27 to be turned off; the turned-on second thin film transistor M28 OUTPUTs a high level signal of the second clock signal CLKB to the OUTPUT terminal OUTPUT of the shift register.
Meanwhile, the low level of the pull-down node B turns on the sixth thin film transistor M25, the turned on sixth thin film transistor M25 OUTPUTs the low level of the input signal STV to the second pull-up node C, the low level of the second pull-up node C turns on the seventh thin film transistor M30, and the turned on seventh thin film transistor M30 OUTPUTs the high level of the power supply positive electrode voltage VGH to the OUTPUT terminal OUTPUT, thereby ensuring the stability of the OUTPUT terminal signal.
At the second stage t2, the first clock signal CLK is at a high level, the second clock signal CLKB is at a low level, and the input signal STV is at a high level; the low level at the node B is held by the capacitor C2, and the second thin film transistor M28 is turned on; the turned-on second thin film transistor M28 OUTPUTs the low level of the second clock signal CLKB to the OUTPUT terminal OUTPUT, and also functions to pull down the potential at the pull-down node B.
At this time, the low level of the node B is pulled down, so that the third tft M24 is in a conducting state, and the power supply positive voltage VGH is OUTPUT to the first pull-up node a, so that the fifth tft M27 is turned off, and it is ensured that the OUTPUT terminal OUTPUT receives the stable signal of the second tft M28.
Meanwhile, the low level of the pull-down node B turns on the sixth thin film transistor M25, the turned-on sixth thin film transistor M25 outputs the high level of the input signal STV to the second pull-up node C, and the high level of the second pull-up node C turns off the seventh thin film transistor M30, which does not affect the normal operation of the shift register.
In the third stage t3, the first clock signal CLK is at a low level, the second clock signal CLKB is at a high level, and the input signal STV is at a high level; since the first clock signal CLK is at a low level, the first thin film transistor M29 is turned on, the turned-on first thin film transistor M29 outputs a high level of the input signal STV to the pull-down node B, and the high level of the pull-down node B turns off the second thin film transistor M28, the third thin film transistor M24, and the sixth thin film transistor M25. The fourth thin film transistor M26 receives the low level of the power low voltage signal VGL and OUTPUTs the low level to the first pull-up node a, so that the fifth thin film transistor M27 is turned on, and the turned-on fifth thin film transistor M27 OUTPUTs the high level of the power high voltage signal VGH to the OUTPUT terminal OUTPUT.
It should be noted that, since the sixth tft M25 is turned off and the second pull-up node C is in a floating state, the source-drain signals of the seventh tft M30 controlled by the second pull-up node C are all at a high level, and therefore, the operation of the shift register is not affected, and the OUTPUT signal of the OUTPUT terminal OUTPUT is not affected.
A fourth stage t4, in which the first clock signal CLK is at a high level, the second clock signal CLKB is at a low level, and the input signal STV is at a high level; the pull-down node B still maintains the high level of the third stage t3 through the capacitor C2, so that the second thin film transistor M28, the third thin film transistor M24, and the sixth thin film transistor M25 are turned off. The low level of the second clock signal CLKB cannot be OUTPUT to the OUTPUT terminal OUTPUT through the second thin film transistor M28, and thus does not affect the stability of the OUTPUT signal.
Meanwhile, the fourth tft M26 receives the low level of the power low voltage signal VGL and OUTPUTs the low level to the first pull-up node a, such that the fifth tft M27 is turned on, and the turned-on fifth tft M27 OUTPUTs the high level of the power high voltage signal VGH to the OUTPUT terminal OUTPUT.
The source-drain signals of the seventh thin film transistor M30 are all high level, and therefore do not affect the operation of the shift register, nor the OUTPUT signal of the OUTPUT terminal OUTPUT.
In a fifth stage t5, the first clock signal CLK is at a low level, the second clock signal CLKB is at a high level, and the input signal STV is at a high level; as in the case of the third stage.
The third stage and the fourth stage are repeated in the subsequent stages, and the high level is output until the low level of the input signal STV is received again, and output is performed according to the timing at which the low level of the input signal STV is received.
The embodiment of the utility model has the following beneficial effects: the shift register improves part or all of suspended nodes to ensure that the nodes are not suspended any more; or controlling the source and drain electrodes of the thin film transistor influenced by the suspended node; thereby improving the stability of the shift register output.
It should be noted that the above embodiments of the present invention are described by taking the shift register applied to the unidirectional scan structure as an example. All the Thin Film Transistors (TFTs) are P-type TFTs, and are switched on at a low level and switched off at a high level. However, the technical solution of the present invention can be applied to shift registers in which the TFT is an N-type TFT or a mixed design of N-type and P-type, when the TFT is an N-type TFT, the high and low potentials of the signals of the shift register structure shown in fig. 2 or fig. 4 are reversed, and the power supply positive voltage VGH and the power supply negative voltage VGL are interchanged; the principle of the shift register with the mixed design of the N type and the P type is similar to the shift register with the mixed design of the N type and the P type, and the description is not repeated.
An embodiment of the present invention provides a display device, including cascaded shift registers as described above, where the cascaded shift registers are as shown in fig. 5, and include n cascaded shift registers (only a part of which is shown) as described in the first embodiment or the second embodiment; providing a first clock signal CLK, a second clock signal CLKB, a power supply anode voltage VGH and a power supply cathode voltage VGL for each shift register; meanwhile, the OUTPUT terminal OUTPUT of the previous stage of shift register is connected with the input signal STV end of the next stage of shift register.
The timing of the cascaded shift registers is shown in fig. 6 (only the timing chart of a part of the cascaded shift registers is shown), and in the stages from t1 to t6, the output signal timing of the next stage shift register is backward delayed by a low level compared with the output signal timing of the previous stage shift register.
It will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (8)
1. A shift register, comprising: the device comprises an input module, a pull-down module, an inverting module and a first pull-up module; wherein,
the input module responds to a first clock signal and provides an input signal voltage to a pull-down node, wherein the pull-down node is an output node of the input module;
the pull-down module stores the input signal voltage and provides a second clock signal to an output terminal in response to an output voltage of the pull-down node;
the inverting module responds to the output voltage of the pull-down node and provides the power supply positive electrode voltage or the power supply negative electrode voltage to the first pull-up node;
the first pull-up module supplies the power supply positive electrode voltage to the output terminal in response to the output voltage of the first pull-up node.
2. The shift register of claim 1, wherein the input module comprises:
and a gate of the first thin film transistor is connected with a first clock signal end, a source of the first thin film transistor is connected with an input signal end, and a drain of the first thin film transistor is used as the output node of the input module, namely the pull-down node.
3. The shift register of claim 1, wherein the pull-down module comprises:
a second thin film transistor, wherein the grid electrode of the second thin film transistor is connected with the pull-down node, the source electrode of the second thin film transistor is connected with a second clock signal end, and the drain electrode of the second thin film transistor is connected with the output terminal;
and the capacitor is connected between the pull-down node and the drain electrode of the second thin film transistor.
4. The shift register of claim 1, wherein the inverting module comprises:
a grid electrode of the third thin film transistor is connected with the pull-down node, a source electrode of the third thin film transistor is connected with a positive voltage end of a power supply, and a drain electrode of the third thin film transistor is connected with the first pull-up node;
and the grid electrode and the drain electrode of the fourth thin film transistor are connected with the negative voltage end of the power supply, and the source electrode of the fourth thin film transistor is connected with the first pull-up node.
5. The shift register of claim 1, wherein the first pull-up module comprises:
and the grid electrode of the fifth thin film transistor is connected with the first pull-up node, the source electrode of the fifth thin film transistor is connected with the positive voltage end of the power supply, and the drain electrode of the fifth thin film transistor is connected with the output terminal.
6. The shift register of any one of claims 1 to 5, further comprising a second pull-up module supplying the power supply positive electrode voltage to the output terminal in response to the output voltage of the pull-down node and the input signal.
7. The shift register of claim 6, wherein the second pull-up module comprises:
a sixth thin film transistor, a gate of which is connected to the pull-down node, a source of which is connected to the input signal terminal, and a drain of which is connected to the second pull-up node;
and the grid electrode of the seventh thin film transistor is connected with the second pull-up node, the source electrode of the seventh thin film transistor is connected with the positive voltage end of the power supply, and the drain electrode of the seventh thin film transistor is connected with the output terminal.
8. A display device comprising a cascade of shift registers as claimed in any one of claims 1 to 7.
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| CN 201320090139 CN203118416U (en) | 2013-02-27 | 2013-02-27 | Shifting register and display device |
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| CN 201320090139 CN203118416U (en) | 2013-02-27 | 2013-02-27 | Shifting register and display device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151010A (en) * | 2013-02-27 | 2013-06-12 | 京东方科技集团股份有限公司 | Shift register and display device |
| CN104332137A (en) * | 2014-11-28 | 2015-02-04 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
-
2013
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103151010A (en) * | 2013-02-27 | 2013-06-12 | 京东方科技集团股份有限公司 | Shift register and display device |
| CN103151010B (en) * | 2013-02-27 | 2014-12-10 | 京东方科技集团股份有限公司 | Shift register and display device |
| US9767916B2 (en) | 2013-02-27 | 2017-09-19 | Boe Technology Group Co., Ltd. | Shift register and display apparatus |
| CN104332137A (en) * | 2014-11-28 | 2015-02-04 | 京东方科技集团股份有限公司 | Gate drive circuit and display device |
| CN104332137B (en) * | 2014-11-28 | 2016-11-16 | 京东方科技集团股份有限公司 | Gate driver circuit and display device |
| US9881559B2 (en) | 2014-11-28 | 2018-01-30 | Boe Technology Group Co., Ltd. | Gate drive circuit and display device |
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