CN203070631U - Circuits for NAND gate teaching demonstration - Google Patents
Circuits for NAND gate teaching demonstration Download PDFInfo
- Publication number
- CN203070631U CN203070631U CN 201320048793 CN201320048793U CN203070631U CN 203070631 U CN203070631 U CN 203070631U CN 201320048793 CN201320048793 CN 201320048793 CN 201320048793 U CN201320048793 U CN 201320048793U CN 203070631 U CN203070631 U CN 203070631U
- Authority
- CN
- China
- Prior art keywords
- sheffer stroke
- stroke gate
- gate chip
- input end
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Instructional Devices (AREA)
Abstract
The utility model discloses circuits for NAND gate teaching demonstration. According to the utility model, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a button S1, a button S2, a S3 button and a button S4 compose a player circuit; a resistor R1, a resistor R2, a resistor R3, a resistor R4, a light-emitting diode VL1, a light-emitting diode VL2, a light-emitting diode VL3 and a light-emitting diode VL4 compose a display circuit; an inverter A, an inverter B, an inverter C, an inverter D, a first NAND gate chip and a second NAND gate chip compose a control circuit, wherein the first NAND gate chip is composed of a first NAND gate chip A and a second NAND gate chip B, and the second NAND gate chip comprises a second NAND gate chip A and a second NAND gate chip B. The utility model has the following beneficial effects: through demonstration by teaching demonstration circuits, students can visually see application of NAND gate characteristics in the circuits.
Description
Technical field
The utility model relates to a kind of teaching demonstration circuit, specifically is a kind of Sheffer stroke gate teaching demonstration circuit.
Background technology
In the teaching of digital circuit combinational logic gate circuit, explanation for the Sheffer stroke gate gate circuit, general teacher forms a simple circuit with an independent Sheffer stroke gate gate circuit, draw the characteristic of Sheffer stroke gate gate circuit, such way only limits to the characteristic that the student knows Sheffer stroke gate, but how to utilize the characteristic of Sheffer stroke gate in example, use and a plurality of gate circuit between how to realize that the study of the relation of controlling and design seem and be nowhere near.
Summary of the invention
Problem at above-mentioned prior art existence, the utility model provides a kind of Sheffer stroke gate teaching demonstration circuit, can see intuitively the Sheffer stroke gate characteristic in circuit application and a plurality of gate circuit between how to connect the control action that realizes between the complex logic relation, be convenient to student's study and understand.
To achieve these goals, the technical solution adopted in the utility model is: a kind of Sheffer stroke gate teaching demonstration circuit, comprise button S1, button S2, button S3, button S4, resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, light emitting diode L1, light emitting diode L2, light emitting diode L3, light emitting diode L4, phase inverter A, phase inverter B, phase inverter C, phase inverter D, the first Sheffer stroke gate chip and the second Sheffer stroke gate chip, the described first Sheffer stroke gate chip is made up of the first Sheffer stroke gate chip A and the first Sheffer stroke gate chip B, the described second Sheffer stroke gate chip is made up of the second Sheffer stroke gate chip A and the second Sheffer stroke gate chip B, button S1 is connected with the input end of resistance R 5 with the second Sheffer stroke gate chip B respectively, button S2 is connected with the input end of resistance R 6 with the second Sheffer stroke gate chip A respectively, button S3 is connected with the input end of resistance R 7 with the first Sheffer stroke gate chip B respectively, button S4 is connected with the input end of resistance R 8 with the first Sheffer stroke gate chip A respectively, the output terminal of the first Sheffer stroke gate chip A successively with phase inverter A, light emitting diode L1 is connected with resistance R 1, the output terminal of the first Sheffer stroke gate chip B successively with phase inverter B, light emitting diode L2 is connected with resistance R 2, the output terminal of the second Sheffer stroke gate chip A successively with phase inverter C, light emitting diode L3 is connected with resistance R 3, the output terminal of the second Sheffer stroke gate chip B successively with phase inverter D, light emitting diode L4 is connected with resistance R 4, the output terminal of the first Sheffer stroke gate chip A respectively with the input end of the first Sheffer stroke gate chip B, the input end of the second Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the first Sheffer stroke gate chip B respectively with the input end of the first Sheffer stroke gate chip A, the input end of the second Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the second Sheffer stroke gate chip A respectively with the input end of the first Sheffer stroke gate chip B, the input end of the first Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the second Sheffer stroke gate chip B respectively with the input end of the first Sheffer stroke gate chip B, the input end of the second Sheffer stroke gate chip A is connected with the input end of the first Sheffer stroke gate chip B.
Further, the first Sheffer stroke gate chip and the second Sheffer stroke gate chip are 74LS20.
Further, phase inverter A, phase inverter B, phase inverter C and phase inverter D are 74LS04.
The beneficial effects of the utility model are: can see Sheffer stroke gate role in circuit intuitively by this device, being convenient to the student understands, allow students experience arrive the conventional method of being realized the complex logic relation by the basic logic gate circuit, deepen the student to the understanding of the control action of gate circuit, be convenient to the student to study and the grasp of gate circuit knowledge.
Description of drawings
Fig. 1 is electric theory diagram of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with accompanying drawing.
As shown in Figure 1, a kind of Sheffer stroke gate teaching demonstration circuit, comprise button S1, button S2, button S3, button S4, resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, light emitting diode L1, light emitting diode L2, light emitting diode L3, light emitting diode L4, phase inverter A, phase inverter B, phase inverter C, phase inverter D, the first Sheffer stroke gate chip and the second Sheffer stroke gate chip, the described first Sheffer stroke gate chip is made up of the first Sheffer stroke gate chip A and the first Sheffer stroke gate chip B, the described second Sheffer stroke gate chip is made up of the second Sheffer stroke gate chip A and the second Sheffer stroke gate chip B, button S1 is connected with the input end of resistance R 5 with the second Sheffer stroke gate chip B respectively, button S2 is connected with the input end of resistance R 6 with the second Sheffer stroke gate chip A respectively, button S3 is connected with the input end of resistance R 7 with the first Sheffer stroke gate chip B respectively, button S4 is connected with the input end of resistance R 8 with the first Sheffer stroke gate chip A respectively, the output terminal of the first Sheffer stroke gate chip A successively with phase inverter A, light emitting diode L1 is connected with resistance R 1, the output terminal of the first Sheffer stroke gate chip B successively with phase inverter B, light emitting diode L2 is connected with resistance R 2, the output terminal of the second Sheffer stroke gate chip A successively with phase inverter C, light emitting diode L3 is connected with resistance R 3, the output terminal of the second Sheffer stroke gate chip B successively with phase inverter D, light emitting diode L4 is connected with resistance R 4, the output terminal of the first Sheffer stroke gate chip A respectively with the input end of the first Sheffer stroke gate chip B, the input end of the second Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the first Sheffer stroke gate chip B respectively with the input end of the first Sheffer stroke gate chip A, the input end of the second Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the second Sheffer stroke gate chip A respectively with the input end of the first Sheffer stroke gate chip B, the input end of the first Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the second Sheffer stroke gate chip B respectively with the input end of the first Sheffer stroke gate chip B, the input end of the second Sheffer stroke gate chip A is connected with the input end of the first Sheffer stroke gate chip B.
The first Sheffer stroke gate chip and the second Sheffer stroke gate chip are 74LS20; Phase inverter A, phase inverter B, phase inverter C and phase inverter D are 74LS04.
The course of work: after this device starts, this moment button S1, button S2, button S3, button S4 disconnects, the input end of the first Sheffer stroke gate chip A then, the input end of the first Sheffer stroke gate chip B, one of them interface of the input end of the input end of the second Sheffer stroke gate chip A and the second Sheffer stroke gate chip B is low level, characteristic according to the Sheffer stroke gate chip, having only the total interface when input end is high level, its output terminal just is low level, otherwise its output terminal output high level, because the output terminal of the first Sheffer stroke gate chip and the output terminal of second Sheffer stroke gate chip output high level, principle according to phase inverter, input low level is output as high level, then the output terminal of phase inverter is low level output, this moment, all light emitting diodes did not all work, and the expression no one races to be the first to answer a question; When the people races to be the first to answer a question, press the button any one among S1, button S2, button S3, the button S4, the interface of all input ends of the Sheffer stroke gate that be connected with this button this moment is high level, and then its output terminal output low level, then through the effect of the phase inverter that is connected with this Sheffer stroke gate output terminal, the output terminal output high level of phase inverter, this moment, corresponding player's a light emitting diode was lighted; On this basis, closure button arbitrarily again, can not light remaining light emitting diode, because the output terminal of this Sheffer stroke gate is low level and an input end that is connected to remaining Sheffer stroke gate, make that one of them interface of input end of remaining Sheffer stroke gate is low level, so no matter closure switch arbitrarily can not lighted remaining light emitting diode.Teacher just can explain while demonstrating like this, and the student can see intuitively how the characteristic of Sheffer stroke gate is applied in the circuit, how to utilize the connection of gate circuit to realize complicated logic control relation in addition, is convenient to the student and understands, thereby effectively improve efficiency of teaching.
Claims (3)
1. Sheffer stroke gate teaching demonstration circuit, it is characterized in that, comprise button S1, button S2, button S3, button S4, resistance R 1, resistance R 2, resistance R 3, resistance R 4, resistance R 5, resistance R 6, resistance R 7, resistance R 8, light emitting diode L1, light emitting diode L2, light emitting diode L3, light emitting diode L4, phase inverter A, phase inverter B, phase inverter C, phase inverter D, the first Sheffer stroke gate chip and the second Sheffer stroke gate chip, the described first Sheffer stroke gate chip is made up of the first Sheffer stroke gate chip A and the first Sheffer stroke gate chip B, the described second Sheffer stroke gate chip is made up of the second Sheffer stroke gate chip A and the second Sheffer stroke gate chip B, button S1 is connected with the input end of resistance R 5 with the second Sheffer stroke gate chip B respectively, button S2 is connected with the input end of resistance R 6 with the second Sheffer stroke gate chip A respectively, button S3 is connected with the input end of resistance R 7 with the first Sheffer stroke gate chip B respectively, button S4 is connected with the input end of resistance R 8 with the first Sheffer stroke gate chip A respectively, the output terminal of the first Sheffer stroke gate chip A successively with phase inverter A, light emitting diode L1 is connected with resistance R 1, the output terminal of the first Sheffer stroke gate chip B successively with phase inverter B, light emitting diode L2 is connected with resistance R 2, the output terminal of the second Sheffer stroke gate chip A successively with phase inverter C, light emitting diode L3 is connected with resistance R 3, the output terminal of the second Sheffer stroke gate chip B successively with phase inverter D, light emitting diode L4 is connected with resistance R 4, the output terminal of the first Sheffer stroke gate chip A respectively with the input end of the first Sheffer stroke gate chip B, the input end of the second Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the first Sheffer stroke gate chip B respectively with the input end of the first Sheffer stroke gate chip A, the input end of the second Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the second Sheffer stroke gate chip A respectively with the input end of the first Sheffer stroke gate chip B, the input end of the first Sheffer stroke gate chip A is connected with the input end of the second Sheffer stroke gate chip B, the output terminal of the second Sheffer stroke gate chip B respectively with the input end of the first Sheffer stroke gate chip B, the input end of the second Sheffer stroke gate chip A is connected with the input end of the first Sheffer stroke gate chip B.
2. Sheffer stroke gate teaching demonstration circuit according to claim 1 is characterized in that, the described first Sheffer stroke gate chip and the second Sheffer stroke gate chip are 74LS20.
3. Sheffer stroke gate teaching demonstration circuit according to claim 1 is characterized in that, described phase inverter A, phase inverter B, phase inverter C and phase inverter D are 74LS04.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320048793 CN203070631U (en) | 2013-01-29 | 2013-01-29 | Circuits for NAND gate teaching demonstration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320048793 CN203070631U (en) | 2013-01-29 | 2013-01-29 | Circuits for NAND gate teaching demonstration |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN203070631U true CN203070631U (en) | 2013-07-17 |
Family
ID=48769396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320048793 Expired - Fee Related CN203070631U (en) | 2013-01-29 | 2013-01-29 | Circuits for NAND gate teaching demonstration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN203070631U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106128240A (en) * | 2016-06-29 | 2016-11-16 | 郭金虎 | A kind of logic circuit demonstration device based on Hall effect |
-
2013
- 2013-01-29 CN CN 201320048793 patent/CN203070631U/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106128240A (en) * | 2016-06-29 | 2016-11-16 | 郭金虎 | A kind of logic circuit demonstration device based on Hall effect |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN203070631U (en) | Circuits for NAND gate teaching demonstration | |
| CN202473036U (en) | Bridge rectifier circuit demonstrator | |
| CN204537578U (en) | Self-inductive phenomenon demonstration instrument | |
| CN204117458U (en) | The break alarm circuit of 555 IC design educations | |
| CN103780108A (en) | Switching power supply driving circuit and dead time adjusting method thereof | |
| CN204904710U (en) | Alcohol gas sensor characteristic and applied demonstration appearance | |
| CN202795852U (en) | Electric solenoid displaying current direction | |
| CN204614313U (en) | Transformer alternating, direct current, pulse current effect demonstrator | |
| CN202268149U (en) | Light-emitting diode (LED) backlight driving circuit of learning machine | |
| CN203120248U (en) | Circuit structure of LED backlight source | |
| CN204257065U (en) | Wet-out phenomenon demonstrator | |
| CN202871155U (en) | Basic SR latch logical relationship demonstration apparatus | |
| CN107656570A (en) | A kind of soft start mu balanced circuit | |
| CN204465055U (en) | Indicator light change-over circuit is full of without postponing charging | |
| CN203225728U (en) | Time relay based on integrated circuit | |
| CN204614315U (en) | current flowing demonstration device | |
| CN204706253U (en) | A kind of device of demonstration battery energy | |
| CN205943243U (en) | Zener diode working characteristics demonstrates appearance | |
| CN205375931U (en) | Acoustooptic controlled delay economize on electricity light switch principle demonstration appearance | |
| CN203773822U (en) | Teaching aid-used lightning formation demonstration device | |
| CN204720069U (en) | thyristor characteristics and application demonstrator | |
| CN203491897U (en) | Electric transformer for computer | |
| CN204374691U (en) | A kind of electronic whiteboard electric power management circuit | |
| CN202504983U (en) | Electric curtain controller | |
| CN202101778U (en) | Integrated temperature transmitter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130717 Termination date: 20140129 |