CN203069704U - Capacitor operation monitoring and early warning instrument - Google Patents
Capacitor operation monitoring and early warning instrument Download PDFInfo
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- CN203069704U CN203069704U CN 201320029913 CN201320029913U CN203069704U CN 203069704 U CN203069704 U CN 203069704U CN 201320029913 CN201320029913 CN 201320029913 CN 201320029913 U CN201320029913 U CN 201320029913U CN 203069704 U CN203069704 U CN 203069704U
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Abstract
The utility model discloses a capacitor operation monitoring and early warning instrument. The instrument comprises a keyboard, a current and voltage sampling circuit, an analog-to-digital converter, a central processor equipped with calculating and rapid Fourier series analysis software, a LCD display, a communication module and a programmable memory storing an alarm fixing value. An output terminal of the current and voltage sampling circuit is connected with a corresponding input terminal of the analog-to-digital converter. The analog-to-digital converter is bidirectionally connected with the central processor. The output terminal of the central processor is connected with the corresponding input terminal of the LCD display. The central processor is connected with the programmable memory through a data bus. According to the instrument of the utility model, the programmable memory and calculating and over-limit alarm software are arranged so that data storage and over-limit alarm functions are possessed. Therefore, each early warning value can be set according to a need and a guarantee is provided for safety operation of the capacitor.
Description
Technical field
The utility model relates to a kind of capacitor operational monitoring early warning instrument, especially a kind of capacitor operational monitoring early warning instrument with data storage and alarming value setting.
Background technology
For high-low pressure electric capacitor apparatus, GB regulation must have following several protection: overcurrent protection, overvoltage protection, under-voltage protection, the protection of transfiniting of unbalance protection, harmonic wave.Capacitor protection device in the market has discrete component and integrated protection dual mode; the discrete component mode is by current relay; voltage relay; the time relay and auxiliary reclay etc. are formed protection system; the employing element is numerous; it is all inconvenient that wiring and debugging are installed, and is in superseded substantially.Integrated protection is to adopt digitizing solution, and each defencive function is concentrated on the electronic circuit board, is calculated and the output action signal by central processing unit.
Above-mentioned protected mode is just at the capacitor fault that has taken place, when fault current or voltage reach the protection setting value, and the protective device action.In fact before the protection action, the fault of capacitor takes place, and damages forming, and the effect of protection is the disengagement failure circuit, prevents that fault from further enlarging.
The shortcoming of capacitor protection device is can not the abnormal running state of capacitor be detected and early warning at present.Because capacitor forms from the up-set condition to the fault, the protection tripping operation has an evolution, if can detect and early warning up-set condition, reminds the operational management personnel in time to handle, and then can reduce the loss, and guarantees the safe operation of capacitor device.
The utility model content
The technical problems to be solved in the utility model provides a kind of capacitor operational monitoring early warning instrument with data storage and monitoring and warning function.
For solving the problems of the technologies described above, technical solution adopted in the utility model is: a kind of capacitor operational monitoring early warning instrument, and its gordian technique is: it comprises keyboard, current sampling circuit, voltage sampling circuit, analog to digital converter U1, is equipped with and calculates and central processing unit U2, LCD display, the communication module of fast Fourier progression analysis (FFT) software and the programmable storage U3 that stores the warning definite value; The output terminal of described current sampling circuit and voltage sampling circuit is connected with the respective input of analog to digital converter U1 respectively, described analog to digital converter U1 is connected with central processing unit U2 is two-way, the output terminal of central processing unit U2 is connected with the respective input of LCD display, and described central processing unit U2 is connected with programmable storage U3 by data bus.
The model of described central processing unit U2 is STM32F103RET6; The model of described programmable storage U3 is AT45DB081DSV.Described analog to digital converter U1 adopts three-phase electrical energy computation chip, and its model is ATT7022D.
Described communication module model is RSM485; The model of described LCD display is CX16012801S-VA.
Described current sampling circuit is made of with the identical circuit of C phase three-phase mutually A phase, B; Described voltage sampling circuit also is made of with the identical circuit of C phase three-phase mutually A phase, B; Wherein the A of current sampling circuit comprises current transformer mutually, resistance R 2, R4, R6, R8, R10 and capacitor C 1 and C2, described resistance R 2 is in parallel with the secondary side L1 of current transformer, secondary side L1 one end of described current transformer connects 3 pin of analog to digital converter U1 through resistance R 4, its other end connects 4 pin of analog to digital converter U1 through resistance R 8, described capacitor C 1 is connected between 3 pin and ground of analog to digital converter U1, described capacitor C 2 is connected between 4 pin and ground of analog to digital converter U1, described resistance R 6 is connected between 3 pin and 11 pin of analog to digital converter U1, and described resistance R 10 is connected between 4 pin and 11 pin of analog to digital converter U1; The A of described voltage sampling circuit comprises resistance R 1, R3, R7, R9, R5 and R11 and capacitor C 11, C22 mutually, the VA of described A phase, VN end connects 13 pin, 14 pin of analog to digital converter U1 respectively successively through resistance R 1 and R3, R7 and R9, described capacitor C 11 is connected between 13 pin and ground of analog to digital converter U1, described capacitor C 22 is connected between 14 pin and ground of analog to digital converter U1, described resistance R 5 is connected between 13 pin and 11 pin of analog to digital converter U1, and described resistance R 11 is connected between 14 pin and 11 pin of analog to digital converter U1.
36 pin of described central processing unit U2 connect 1 pin of programmable storage, 34 pin of described central processing unit U2 connect 2 pin of programmable storage U3,33 pin of described central processing unit U2 connect 4 pin of programmable storage U3, and 35 pin of described central processing unit U2 connect 8 pin of programmable storage U3.
The beneficial effect that adopts technique scheme to produce is: the utility model can be with the data storage of current and voltage data and harmonic wave by the programmable storage that arranges, and the alarming value of measured value and setting compared, when measured value reaches alarming value, send alerting signal, remind the operations staff in time to check the hidden danger of fixing a breakdown; The warning project that the utility model can be set is: excess current, superpotential, low-voltage, current imbalance, Voltage unbalance, harmonic voltage and harmonic current, it is set numerical value and determines according to different needs, the warning project can all be set, and also can select wherein several to set at special-purpose.
LCD display can show the current/voltage value synchronously, and the histogram of performance number and current and voltage harmonic is in order to observe the operation conditions of capacitor device; Fourier series is installed in the central processing unit decomposes software, can obtain the harmonic component in the signal, in order to check the quality of power supply.The utility model has been filled up the blank of capacitor protection early warning, has great technology and economic worth.
Description of drawings
Fig. 1 is that hardware of the present utility model connects block diagram;
Fig. 2 is circuit theory diagrams of the present utility model;
Fig. 3 is software flow block diagram of the present utility model
Fig. 4 is the current history record diagram;
Fig. 5 is the voltage history record diagram;
Fig. 6 is the current harmonics histogram;
Fig. 7 is the voltage harmonic histogram.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is described in further detail.
Referring to accompanying drawing 1, accompanying drawing 2 and accompanying drawing 3, the utility model comprises keyboard, current sampling circuit and voltage sampling circuit, analog to digital converter U1, central processing unit U2, LCD display, communication module and the programmable storage U3 of calculating and fast Fourier progression analysis software (FFT) is housed, and stores various warning values of setting in the programmable storage U3; The output terminal of described current sampling circuit and voltage sampling circuit is connected with the respective input of analog to digital converter U1 respectively, described analog to digital converter U1 is connected with central processing unit U2 is two-way, the output terminal of central processing unit U2 is connected with the respective input of LCD display, and described central processing unit U2 is connected with programmable storage U3 by data bus.
Wherein, the model of described central processing unit is STM32F103RET6; The model of described programmable storage is AT45DB081DSV.Described analog to digital converter adopts three-phase electrical energy computation chip, and its model is ATT7022D.Described communication module model is RSM485; The model of described LCD display is HG12864-15AF.
Referring to accompanying drawing 2, described current sampling circuit is by the A phase, the circuit that the B phase is identical with C phase three-phase is formed, wherein A comprises current transformer mutually, resistance R 2, R4, R6, R8, R10 and capacitor C 1 and C2, described resistance R 2 is in parallel with the secondary side L1 of current transformer, secondary side L1 one end of described current transformer connects 3 pin of analog to digital converter U1 through resistance R 4, its other end connects 4 pin of analog to digital converter U1 through resistance R 8, described capacitor C 1 is connected between 3 pin and ground of analog to digital converter U1, described capacitor C 2 is connected between 4 pin and ground of analog to digital converter U1, described resistance R 6 is connected between 3 pin and 11 pin of analog to digital converter U1, and described resistance R 10 is connected between 4 pin and 11 pin of analog to digital converter U1.Wherein the B of current sampling circuit comprises current transformer L2, resistance R 12, R14, R16, R20, R18 and capacitor C 3 and C4 mutually; The C of current sampling circuit comprises current transformer L3, resistance R 22, R24, R28, R26, R30 and capacitor C 5 and C6 mutually.
Referring to accompanying drawing 2, described voltage sampling circuit is by the A phase, the circuit that the B phase is identical with C phase three-phase is formed, wherein A comprises resistance R 1 mutually, R3, R7, R9, R5 and R11 and capacitor C 11, C22, the VA of described A phase, the VN end is respectively successively through resistance R 1 and R3, R7 and R9 connect 13 pin of analog to digital converter U1,14 pin, described capacitor C 11 is connected between 13 pin and ground of analog to digital converter U1, described capacitor C 22 is connected between 14 pin and ground of analog to digital converter U1, described resistance R 5 is connected between 13 pin and 11 pin of analog to digital converter U1, and described resistance R 11 is connected between 14 pin and 11 pin of analog to digital converter U1.The B of voltage sampling circuit comprises resistance R 13, R15, R17, R19, R21 and R23 and capacitor C 33, C44 mutually; Voltage sampling circuit C comprises resistance R 25, R27, R29, R31, R33 and R35 and capacitor C 55, C66 mutually.
36 pin of described central processing unit connect 1 pin of programmable storage, 34 pin of described central processing unit connect 2 pin of programmable storage, 33 pin of described central processing unit connect 4 pin of programmable storage, and 35 pin of described central processing unit connect 8 pin of programmable storage.
Referring to accompanying drawing 2 and accompanying drawing 3, Current Transformer Secondary side three-phase sample rate current Ia, Ib, Ic signal are connected with the input end of analog to digital converter respectively.Three-phase sampled voltage Ua, Ub, Uc signal are connected with the input end of analog to digital converter respectively.Analog to digital converter U1 adopts 19 A/D converter ATT7022D of the bipolar input of six passages chip, and its analog quantity with current/voltage is converted to digital quantity, delivers to central processing unit U2 then and carries out computing.Central processing unit U2 is circumscribed with real-time clock integrated circuit, RSM485 communication module and external key interface.The digital signal output end of central processing unit U2 is connected with LCD display.Connect through SPI between central processing unit U2 and the programmable storage U3, central processing unit U2 calculates by the real-time analysis of FFT software, draws the amplitude of first-harmonic and 2～31 subharmonic.Central processing unit U1 is kept at measuring parameter among the programmable storage U3 by latch on the one hand, and it stores current/voltage and relevant harmonic value; On the other hand each measuring parameter is exported to LCD display (160*128), show by display screen, when the outside has data transmission to require, to 485 communication modules transmission data, namely link to each other with PC by the RSM485 communication module, can be correlated with to instrument arranges and data transmission, and continuous data is sent on the PC, is managed by the PC management software.The RSM485 interface can connect 128 instrument at most, and communication distance reaches 1.5 kilometers.
Referring to accompanying drawing 3, it is the workflow block diagram, and the measured value of current/voltage and the setting value of storage compare, when measured value during greater than setting value, after accumulative total and time-delay, this event is carried out record, the built-in relay closes of while control instrument, guide alarm circuit.Various warning projects take " or " relation carries out.Operating personnel can pass through the event query function, determine warning reason, in order to take corresponding measure.The data that transfinite also can pass to supervisory computer by the RS485 communication port and carry out record.
Referring to accompanying drawing 4 and accompanying drawing 5, during work, the form of presentation of current/voltage value historical data adopts graphics mode, the longitudinal axis is effective value, by volt (V), the amplitude scale of ampere (A) or kiloampere (kA) kilovolt (kV), transverse axis is 24 hours time scale, the current/voltage value is carried out the integral point time recording according to amplitude and time.When the 24th hour finishes, deposit the data of 24 hour records in programmable storage U3.During the historical data of some day, by the inquiry of historical data function, confirmed the date by the perpetual calendar in the machine before needs are checked, the data of this day namely are presented on the screen.When transferring historical data, do not influence normal measurement and the record of instrument.Historical data coexistence storage 365 days, the mode of the storage of taking to circulate, i.e. storage is full after 365 days, when nearest 24 hour datas deposit in, covers first data of 24 hours.
Referring to accompanying drawing 6 and accompanying drawing 7, when the digital quantity after the analog to digital conversion being carried out the first-harmonic metering, by central processing unit the RMS value is carried out fast Fourier progression (FFT) conversion, obtain the harmonic component in the signal, the utility model can analyze 2-31 times the harmonic wave entire spectrum, namely odd number is all carried out frequency analysis with even harmonics.2-31 subharmonic value shows at liquid crystal display with the form of histogram, the longitudinal axis is represented the content of harmonic wave by percentage, transverse axis is represented 2-31 subharmonic number of times, the content of harmonic wave represents that with the form of histogram (HRi% HRu%), shows fundamental current (A simultaneously on the display screen, kA), voltage (V, kV), and total percent harmonic distortion of analystal section (2-31) (THDi%, THDu%).The sample frequency of data is 3.2K/ second, when 24 hours finish, instrument calculate in 24 hours 3 mutually in the big value of 95% probability of each harmonic, minimum value and mean value deposit programmable storage U3 in.During the harmonic data of some day, by the inquiry of historical data function, confirmed the date by the perpetual calendar in the machine before needs are checked, the various data of this day namely are presented on the screen.When transferring historical data, do not influence normal measurement and the record of instrument.Historical data coexistence storage 365 days, the mode of the storage of taking to circulate, i.e. storage is full after 365 days, when nearest 24 hour datas deposit in, covers first data of 24 hours.
To the above-mentioned explanation of the disclosed embodiments, make this area professional and technical personnel can realize or use the utility model.Multiple modification to these embodiment will be apparent concerning those skilled in the art, and defined General Principle can realize under the situation that does not break away from spirit or scope of the present utility model in other embodiments herein.Therefore, the utility model will can not be restricted to these embodiment shown in this article, but will meet the wideest scope consistent with principle disclosed herein and features of novelty.
Claims (6)
1. capacitor operational monitoring early warning instrument is characterized in that: it comprises keyboard, current sampling circuit, voltage sampling circuit, analog to digital converter U1, is equipped with and calculates and central processing unit U2, LCD display, the communication module of fast Fourier progression analysis software and the programmable storage U3 that stores the warning definite value; The output terminal of described current sampling circuit and voltage sampling circuit is connected with the respective input of analog to digital converter U1 respectively, described analog to digital converter U1 is connected with central processing unit U2 is two-way, the output terminal of central processing unit U2 is connected with the respective input of LCD display, and described central processing unit U2 is connected with programmable storage U3 by data bus.
2. capacitor operational monitoring early warning instrument according to claim 1, it is characterized in that: the model of described central processing unit U2 is STM32F103RET6; The model of described programmable storage U3 is AT45DB081DSV.
3. capacitor operational monitoring early warning instrument according to claim 1 is characterized in that: described analog to digital converter U1 adopts three-phase electrical energy computation chip, and its model is ATT7022D.
4. capacitor operational monitoring early warning instrument according to claim 1, it is characterized in that: described communication module model is RSM485; The model of described LCD display is CX16012801S-VA.
5. capacitor operational monitoring early warning instrument according to claim 3 is characterized in that: described current sampling circuit is made of with the identical circuit of C phase three-phase mutually A phase, B; Described voltage sampling circuit also is made of with the identical circuit of C phase three-phase mutually A phase, B;
Wherein the A of current sampling circuit comprises current transformer mutually, resistance R 2, R4, R6, R8, R10 and capacitor C 1 and C2, described resistance R 2 is in parallel with the secondary side L1 of current transformer, secondary side L1 one end of described current transformer connects 3 pin of analog to digital converter U1 through resistance R 4, its other end connects 4 pin of analog to digital converter U1 through resistance R 8, described capacitor C 1 is connected between 3 pin and ground of analog to digital converter U1, described capacitor C 2 is connected between 4 pin and ground of analog to digital converter U1, described resistance R 6 is connected between 3 pin and 11 pin of analog to digital converter U1, and described resistance R 10 is connected between 4 pin and 11 pin of analog to digital converter U1;
The A of described voltage sampling circuit comprises resistance R 1, R3, R7, R9, R5 and R11 and capacitor C 11, C22 mutually, the VA of described A phase, VN end connects 13 pin, 14 pin of analog to digital converter U1 respectively successively through resistance R 1 and R3, R7 and R9, described capacitor C 11 is connected between 13 pin and ground of analog to digital converter U1, described capacitor C 22 is connected between 14 pin and ground of analog to digital converter U1, described resistance R 5 is connected between 13 pin and 11 pin of analog to digital converter U1, and described resistance R 11 is connected between 14 pin and 11 pin of analog to digital converter U1.
6. capacitor operational monitoring early warning instrument according to claim 2, it is characterized in that: 36 pin of described central processing unit U2 connect 1 pin of programmable storage, 34 pin of described central processing unit U2 connect 2 pin of programmable storage U3,33 pin of described central processing unit U2 connect 4 pin of programmable storage U3, and 35 pin of described central processing unit U2 connect 8 pin of programmable storage U3.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320029913 CN203069704U (en) | 2013-01-21 | 2013-01-21 | Capacitor operation monitoring and early warning instrument |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320029913 CN203069704U (en) | 2013-01-21 | 2013-01-21 | Capacitor operation monitoring and early warning instrument |
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| CN203069704U true CN203069704U (en) | 2013-07-17 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104280632A (en) * | 2014-09-28 | 2015-01-14 | 国家电网公司 | Automatic detecting and early warning method for relay protection device and fault recorder |
| CN108206508A (en) * | 2016-12-20 | 2018-06-26 | 南京南瑞继保电气有限公司 | A kind of adaptive shunt capacitor impedance protecting method |
| CN109738705A (en) * | 2018-12-29 | 2019-05-10 | 浙江南德电气有限公司 | A kind of capacitor capacitance decaying detection method |
-
2013
- 2013-01-21 CN CN 201320029913 patent/CN203069704U/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104280632A (en) * | 2014-09-28 | 2015-01-14 | 国家电网公司 | Automatic detecting and early warning method for relay protection device and fault recorder |
| CN104280632B (en) * | 2014-09-28 | 2017-01-11 | 国家电网公司 | Automatic detecting and early warning method for relay protection device and fault recorder |
| CN108206508A (en) * | 2016-12-20 | 2018-06-26 | 南京南瑞继保电气有限公司 | A kind of adaptive shunt capacitor impedance protecting method |
| CN108206508B (en) * | 2016-12-20 | 2019-05-21 | 南京南瑞继保电气有限公司 | A kind of adaptive shunt capacitor impedance protecting method |
| CN109738705A (en) * | 2018-12-29 | 2019-05-10 | 浙江南德电气有限公司 | A kind of capacitor capacitance decaying detection method |
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Legal Events
| Date | Code | Title | Description |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20130717 Termination date: 20160121 |
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| EXPY | Termination of patent right or utility model |