CN203056868U

CN203056868U - Interlaced pwm control circuit

Info

Publication number: CN203056868U
Application number: CN 201220663415
Authority: CN
Inventors: 胡家培; 胡民海
Original assignee: Xian Zhihai Power Technology Co Ltd
Current assignee: Xian Zhihai Power Technology Co Ltd
Priority date: 2012-11-30
Filing date: 2012-11-30
Publication date: 2013-07-10
Anticipated expiration: 2022-11-30

Abstract

The utility model provides an interlaced PWM control circuit. The circuit mainly solves the problem that a conventional low voltage new energy power converter is high in power consumption, low in efficiency and poor in reliability. A driving signal synthesizing circuit of the interlaced PWM control circuit is a standard dual-input or door control chip, and the control chip comprises four pairs of input ends A1, A2, B1, B2, C1, C2, D1 and D2 and four corresponding output ends A0, B0, C0 and D0, wherein the input end A1, B1, C1 and D1 are connected with the two output ends of a width modulation type pulse control circuit, the input ends A2, B2, C2 and D2 are connected with the two output ends of a follow current voltage sampling circuit, and the output ends A0, B0, C0 and D0 are connected with the input end of a VMOS switch driving circuit. A capacitor is used in an energy storage filter circuit, the positive end of the capacitor is connected with the positive end of a load, and the negative end of the capacitor is connected with the negative end of the load.

Description

Staggered pwm control circuit

Technical field

The present invention relates to a kind of staggered pwm control circuit, belong to power supply switch technology field.

Background technology

In recent years, the renewable new energy resources system of AC low-tensions such as photovoltaic generation, wind power generation, storage battery power supply, dc low-voltage power supply is widely used, and the power supplying efficiency, power supply quality, the power supply reliability that improve low pressure new energy system are imperative.

The basic employing of present power supply conversion known in this field:

1, exchange (AC) input, adopting full-wave rectifier is input AC (AC) power rectifier direct current (DC) power supply, carries out DC/DC again and is converted to direct current (DC) output.This kind scheme has solved the transfer problem than high input voltage AC power and small-power power.But when the input of low-voltage AC power and large power supply conversion, because the voltage drop of AC/DC rectification circuit is higher, and produce very high power consumption, make the power supply changeover device conversion efficiency very low.

2, direct current (DC) input is directly carried out DC/DC and is converted to direct current (DC) output.This kind scheme has solved the permanent plant powerup issue.But dependability is lower, especially at mobility equipment, often need reconnect the equipment of input power supply, connects anti-situation in case electric power polarity occurs, will produce the input short circuit accident.Therefore the higher equipment of ask for something reliability adds the directed rectification circuit of direct current at the transducer input.When the straight power supply input of low-voltage and large power supply conversion, higher because direct current is identified the voltage drop of directed rectification circuit, and produce very high power consumption, make the power supply changeover device conversion efficiency very low.

3, in order to improve low-voltage power supply efficient, to reduce line current and generally adopt boost type (BOOST) direct current (DC) supply power mode.Boost type (BOOST) direct current (DC) power supply is when output generation short trouble, and the BOOST circuit function lost efficacy when output voltage was lower than input voltage, and the input power supply is directly to load short circuits, and it is very big that difficulty is controlled in big electric current (high-power) system short-circuit protection.

Be that example describes with conventional rectification (identification directed) circuit being input as low pressure new forms of energy power supply, input voltage Ui=10V (AC, DC), input current Ii=20A, input power Pi=10 * 20=200W, rectification (identification is directed) circuit pressure drop Ud=2V, rectification (identification is directed) circuit consumption is: Pd=2 * 20=40W, power output Po=200-40=160W, its rectification (identification is directed) efficient is: E=160/200=0.8, this shows that conventional rectification (identification is directed) circuit is when being input as low pressure new forms of energy power supply, power consumption is very big, and efficient is very low.

Summary of the invention

The invention provides a kind of staggered pwm control circuit, solved mainly that existing low pressure new forms of energy power supply changeover device power consumption height, efficient are low, the problem of poor reliability.

Concrete technical solution of the present invention is as follows:

Be somebody's turn to do staggered pwm control circuit, comprise load, the input of described load is connected with the output of input power supply by energy storage filter circuit, reverse isolation circuit, VMOS control circuit, afterflow inductance successively; The output of described energy storage filter circuit is connected by the input of output current sample circuit and width modulation type pulse control circuit, the output of described input power supply is connected by the input of input current sample circuit and width modulation type pulse control circuit, the output of width modulation type pulse control circuit is connected with the input of VMOS switch driving circuit with the VMOS switching circuit by driving signal synthesis circuit successively, and the input that drives signal synthesis circuit is connected by the output of afterflow voltage sampling circuit with the VMOS switching circuit; Described width modulation type pulse control circuit, driving signal synthesis circuit, VMOS switch driving circuit and afterflow voltage sampling circuit are formed control circuit;

Described driving signal synthesis circuit is standard two input or gate control chips, and this control chip comprises four couples of input A1, A2, B1, B2, C1, C2, D1, D2 and corresponding four output terminals A o, Bo, Co, Do, input A1 wherein, B1, C1, D1 is connected input A2, B2 with two outputs of width modulation type pulse control circuit, C2, D2 is connected with two outputs of afterflow voltage sampling circuit, and output terminals A o, Bo, Co, Do are connected with the input of VMOS switch driving circuit; Described energy storage filter circuit adopts an electric capacity, the positive termination load anode of this electric capacity, and the negative terminal of this electric capacity connects the load negative terminal.

The invention has the advantages that:

Staggered pwm control circuit provided by the invention has XC/DC expansion (XC) shape, nonpolarity, many waveforms, the input of broadband power supply, DC (direct current) output, advantages such as auto polarity identification orientation, high conversion efficiency, High Power Factor, high reliability, high power density, low cost.

Description of drawings

Fig. 1 is schematic block circuit diagram of the present invention;

Fig. 2 is electrical block diagram of the present invention;

Monocycle oscillogram when Fig. 3 is the Ac sine wave for the input power supply.

Embodiment

Driving signal synthesis circuit is standard two input or gate control chips, and this control chip comprises four couples of input A1, A2, B1, B2, C1, C2, D1, D2 and corresponding four output terminals A o, Bo, Co, Do, input A1 wherein, B1, C1, D1 is connected input A2, B2 with two outputs of width modulation type pulse control circuit, C2, D2 is connected with two outputs of afterflow voltage sampling circuit, and output terminals A o, Bo, Co, Do are connected with the input of VMOS switch driving circuit; Described energy storage filter circuit adopts an electric capacity, the positive termination load anode of this electric capacity, and the negative terminal of this electric capacity connects the load negative terminal.

Below the function of each important circuit is described:

Afterflow inductance: utilize inductance characteristic that the input power supply is boosted;

VMOS switching circuit: VMOS switching circuit conduction period, have electric current to pass through in the afterflow inductance; VMOS switching circuit blocking interval, the freewheeling circuit conducting makes electric current continuation conducting in the afterflow inductance, produces high pressure, and the energy storage filter circuit is charged, and the charging back is powered to load by the energy storage filter circuit;

The energy storage filter circuit: VMOS switching circuit blocking interval charges and load is powered;

VMOS switch driving circuit: VMOS switching signal and the VMOS afterflow signal that drives the signal synthesis circuit generation amplified processing;

Drive signal synthesis circuit: the PWM width modulation type pulse signal of width modulation type pulse control circuit generation, alternating current-direct current signal, both positive and negative polarity signal or afterflow signal and the power supply signal of voltage sampling circuit input are synthesized, generate composite signal (comprising polarity, interchange, direct current, accent bandwidth signals); Automatically distribute according to composite signal then, divide into VMOS switching signal and VMOS afterflow signal;

The width modulation type pulse control circuit: the current sampling signal according to input sampling circuit and/or the input of output sample circuit generates PWM width modulation type pulse signal;

The afterflow voltage sampling circuit: the current signal to VMOS switching circuit and freewheeling circuit is sampled, and produces alternating current-direct current signal, both positive and negative polarity signal or afterflow signal, and above-mentioned signal is inputed to the driving signal synthesis circuit;

The input current sample circuit: input is sampled through the electric current of afterflow inductance to the input power supply, generates sampled signal and sampled signal is offered the width modulation type pulse control circuit and handle;

Below in conjunction with accompanying drawing the present invention is described in detail:

IC1 (UCC28084 or other similar device), for the standard both-end is alternately exported the PWM controller, PWM transfers wide output by device 1 end (OC) control, output alternative P WM waveform P1, P2.

R1, R5, the afterflow waveform of C12, Z4 PA detect shaping, form waveform P3.Wherein, voltage-stabiliser tube Z4 keeps the voltage of P3 stable, and capacitor C 12 makes to make P3 continue high level when high level appears in PA in order to filtering.

R4, R3, the afterflow waveform of C11, Z3 PB detect shaping, form waveform P4.Wherein, voltage-stabiliser tube Z3 keeps the voltage of P4 stable, and capacitor C 11 makes to make P4 continue high level when high level appears in PB in order to filtering.

IC2 (CD4071 or other similar device) is standard 2 inputs or door, wherein: and Ao=A1+A2, Bo=B1+B2, Co=C1+C2, Do=D1+D2, carry out the synthetic back of logic to P1, P2, P3, P4 and form staggered output pwm waveform.

IC3, IC4 (IR442 or other similar device) are standard drive, wherein: Ao=Ai, Bo=Bi, VMOS is carried out the big current drives of high speed, improve conversion efficiency to reduce VMOS switch power consumption.

CS1, CS2, D4, D5, R21, C13 form current sense, discriminating, testing circuit, detect the PWM current waveform that the high-end VMOS of power supply passes through when opening automatically.Super its circuit has very low power consumption simultaneously, adopts current sense coefficient ﹤ 100, controlling of sampling voltage ﹤ 0.5V, and control power consumption Pe ﹤ 0.5 * IO * 0.01=0.005 * IO (IO is the conducting electric current) is when IO is 20A: Pe ﹤ 0.05 * 20=0.1W.

C7, C8, C9 are mainly used in further eliminating noise (burst pulse).

L1, D3, C14 form the LDC of BOOST booster circuit, in order to adapt to the asymmetry of importing power supply, for example unipolarity direct current, unipolarity square wave, unipolarity triangular wave etc., L1 adopts the differential mode symmetrical expression, also can be only inductance be set as L1 at anode or the negative terminal of input circuit.

Ao port and the Bo port of pwm control circuit (IC1) are alternately exported control signal P1, P2, and total the maintenance blanking time (corresponding to the high level of PA waveform) that is used for afterflow between P1, the P2.P3, P4 are by the PA in the input circuit, PB waveform dividing potential drop gained.P1, P2, P3, P4 insert the input port of triggering signal combiner circuit (IC2), carry out foregoing or logical operation after, drive through switch driver IC3, IC4 respectively again triggering signal added to two VMOS switching circuit groups (M1, M2 respectively; M3, M4), D3 has two inputs, is connected to anode and the negative terminal of input circuit respectively, and forward current charges through the C14 of reverse isolation circuit D3.

M1 alternation in parallel with M2, M3 alternation in parallel with M4 (each VMOS switch itself has diode connected in parallel with it).

Negative just down on the positive half cycle of waveform or input direct current are at input AC, when one of the control signal P1 of pwm control circuit (IC1) output and P2 are in high level, this XC/DC automatic orientation BOOST circuit is in the PWM conducting state, electric current from anode flow through successively first group of VMOS switching circuit group (M1, M2), second group of VMOS switching circuit group (M3, M4), flows back to negative terminal then in input circuit; Because D3 plays the reverse isolation effect, the energy storage on the C14 can reverse flow not be fed back into the loop.

As the control signal P1 of pwm control circuit (IC1) output, when P2 is low level, then there is not triggering signal on M1, the M2, therefore M1, not conducting of M2, but because the existence of afterflow inductance L 1, and the diode among M3, the M4 can form the conducting loop of holding certainly to the input circuit negative terminal, thereby the afterflow that produces because of the afterflow inductance in the circuit is charged through the C14 of D3 from the anode of input circuit, and via load, second group of VMOS switching circuit group (M3, M4) of output loop, flow back to negative terminal then simultaneously.In fact, in case there is above-mentioned afterflow in the circuit, namely PA is that high level, PB are low level, thereby make P1, P2, P3, P4 carry out or logical operation after produce triggering signal, make M3, M4 conducting, because the resistance of M3, M4 is very little, therefore, the power consumption that produces in the afterflow process is still very little.And the output itself of boosting can reduce line loss.Such as, Ui=10 (V), the back Uo=50 (V) that boosts is then according to P=U ²/ R as can be known, line loss only is original 1/5.

Illustrate low-power consumption of the present invention: adopt R in the circuit _DS=0.001 Ω low on-resistance N raceway groove VMOS pipe, the staggered conducting of M1, M2 during PWM opens, VMOS conducting resistance R _DS=0.001 Ω, the two-tube paralleling and interleaving conducting of M3, M4, VMOS conducting resistance R _DS=0.001 Ω/2=0.0005 Ω, if still import the 20A electric current, then conducting voltage is: U1=0.001 * 20=0.02V, U2=0.0005 * 20=0.01V, identify directed power consumption and be: Pe=20 * (0.02+0.01)=0.6W; End shutoff, the two-tube paralleling and interleaving conducting of M3, M4 afterflow, VMOS conducting resistance R at PWM blocking interval M1, M2 _DS=0.001 Ω/2=0.0005 Ω, if the 20A freewheel current, then conducting voltage is: U2=0.0005 * 20=0.01V, identify directed power consumption and be: Pe=20 * 0.01=0.2W.Compare to the power consumption of the rectification identification directional circuit 40W of prior art, XC/DC of the present invention identifies directed BOOST circuit power consumption automatically and significantly reduces.

If reverse isolation circuit D3 also adopts synchronous VMOS switching circuit (synchronous waveform of its triggering signal and PA and PB), then can utilize the little characteristic of VMOS switching circuit resistance further to reduce line loss.Especially the raising of conversion efficiency is more remarkable when BOOST output is low.

The VMOS switch is under the triggering signal effect, can realize conducting forward or backwards according to institute's making alive polarity, based on this characteristic, be negative timing down at input AC at waveform negative half period or input direct current, the course of work of this XC/DC automatic orientation BOOST circuit and above-mentioned conducting, afterflow Principle of Process are identical, and because first group of VMOS switching circuit group (M1, M2) adopts the symmetric circuit structure with second group of VMOS switching circuit group (M3, M4), be completely reversibility in the VMOS conducting of Ui negative half period and afterflow.Such as, as the control signal P1 of pwm control circuit (IC1) output, when P2 is low level, then do not have triggering signal on M3, the M4, so M3, not conducting of M4, and realize the afterflow process by first group of VMOS switching circuit group (M1, M2).

As seen, this BOOST circuit can be finished the automatic identification orientation to bipolar power supply (exchanging just profound ripple, square wave, triangular wave, AC power frequency, intermediate frequency, low frequency, ultralow frequency) automatically; Reach the automatic identification orientation to unipolarity power supply (direct current, direct current square wave, direct current triangular wave etc.), exchange bipolar power supply and direct current unipolarity power supply and can be regardless of positive and negative any access.

Above-described embodiment is most preferred embodiment of the present invention, adopts this staggered PWM control mode to make M1, the M2 conducting that interlocks, and each VMOS switch operating frequency is 1/2 channel frequency, and the VMOS switch is being worked than under the low switching frequency, significantly reduces the switch power consumption; Correspondingly, the operating frequency of L, C device is 2 times of VMOS pipe frequencies in the circuit, and higher circuit work frequency has reduced the requirement to inductance in the lc circuit (L) amount and electric capacity (C), has reduced cost and technology difficulty.In fact, based on the basic principle of conducting of the present invention, afterflow, can consider that also each VMOS switching circuit group only adopts a VMOS switch, also is enough to embody technique effect of the present invention.Such as only keeping M1, M3, equally also can when input AC is negative just down on the positive half cycle of waveform or input direct current are, realize the conducting loop by M1, M3, realize continuous current circuit by M3; Be negative timing down at input AC at waveform negative half period or input direct current, realize the conducting loop by M1, M3, realize continuous current circuit by M1.Certainly, under this scheme, also can attempt allowing the operating frequency of each VMOS switch reduce by half, but this just need increase afterflow inductance, storage capacitor exponentially, satisfying the requirement of afterflow, thereby cause that cost is higher, the components and parts volume is big, power density reduces.

Claims

1. staggered pwm control circuit is characterized in that: comprise load, the input of described load is connected with the output of input power supply by energy storage filter circuit, reverse isolation circuit, VMOS control circuit, afterflow inductance successively; The output of described energy storage filter circuit is connected by the input of output current sample circuit and width modulation type pulse control circuit, the output of described input power supply is connected by the input of input current sample circuit and width modulation type pulse control circuit, the output of width modulation type pulse control circuit is connected with the input of VMOS switch driving circuit with the VMOS switching circuit by driving signal synthesis circuit successively, and the input that drives signal synthesis circuit is connected by the output of afterflow voltage sampling circuit with the VMOS switching circuit; Described width modulation type pulse control circuit, driving signal synthesis circuit, VMOS switch driving circuit and afterflow voltage sampling circuit are formed control circuit;