CN203025328U - Adjustable active load circuit - Google Patents

Adjustable active load circuit Download PDF

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Publication number
CN203025328U
CN203025328U CN 201220728854 CN201220728854U CN203025328U CN 203025328 U CN203025328 U CN 203025328U CN 201220728854 CN201220728854 CN 201220728854 CN 201220728854 U CN201220728854 U CN 201220728854U CN 203025328 U CN203025328 U CN 203025328U
Authority
CN
China
Prior art keywords
shunt resistance
operational amplifier
potentiometer
load
nmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN 201220728854
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Chinese (zh)
Inventor
杨思佳
孙元鹏
李迪伽
聂开云
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shenzhen Zhenhua Microelectronics Co Ltd
Original Assignee
Shenzhen Zhenhua Microelectronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
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Priority to CN 201220728854 priority Critical patent/CN203025328U/en
Application granted granted Critical
Publication of CN203025328U publication Critical patent/CN203025328U/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Abstract

The utility model belongs to the field of load circuits, and particularly relates to an adjustable active load circuit. The adjustable active load circuit provided by the utility model consists of usual discrete components, wherein the current passing through a regulator potentiometer RL and the current passing through an operational amplifier OP form a comparing circuit through the regulator potentiometer RL, so that load powder borne by the potentiometer RL is converted into an NMOS (N-Channel Metal Oxide Semiconductor) tube, and the power borne by the NMOS tube is controlled through the regulator potentiometer RL; when more parallel-connected NMOS tubes are arranged, the borne load power is larger and the adjustable load range is larger; the precision in load adjustment is improved through the operational amplifier OP; and meanwhile, a load resistance value is more stable and easy to adjust, and the service life is longer. The problems that the conventional load circuit or power potentiometer has the defects of higher cost, larger relative size, lower precision, unstable resistance value and short service life can be solved.

Description

A kind of adjustable active pull-up circuit
Technical field
The utility model belongs to the load circuit field, relates in particular to a kind of adjustable active pull-up circuit.
Background technology
In the test of electronic product, as commonly used to pull-up resistor in the test of DC/DC power supply especially at the power power-supply product, or electronic load.The pull-up resistor heating is larger, and commercial electronic load cost is high, and volume is large, all makes troubles to use.
Load commonly used is electronic load, power potentiometer etc. now.But the electronic load cost is higher, and relative volume is larger; Power points position device, precision is just relatively low, and resistance is stable not, and life cycle is short.
The utility model content
The utility model provides a kind of adjustable active load test circuit, is intended to solve existing load circuit or power potentiometer cost higher, and relative volume is larger, and total amount is larger, and precision is lower, and resistance is stable not, the problem that life cycle is short.
In order to solve the problems of the technologies described above, the utility model provides a kind of adjustable active load test circuit, and described active pull-up circuit comprises:
Shunt resistance R1, shunt resistance R2, shunt resistance R3, shunt resistance R4, shunt resistance R5, shunt resistance R6, shunt resistance R7, shunt resistance R8, potentiometer RL, filter capacitor C1, operational amplifier OP and a plurality of NMOS pipes in parallel;
the power supply termination of described operational amplifier OP+VIN driving voltage, described shunt resistance R1 and described shunt resistance R6 are connected in series between the first end and the 3rd end of the second end of described shunt resistance R2 and described potentiometer RL, the second end ground connection of described potentiometer RL, the first end of described shunt resistance R2 is connected with the power end of described operational amplifier OP, described shunt resistance R7 is connected between the in-phase input end of the public connecting end of described shunt resistance R6 and described potentiometer RL and described operational amplifier OP, the in-phase input end of described filter capacitor C1 the first described operational amplifier OP of termination, described filter capacitor C1 the second end ground connection, described shunt resistance R5 is connected between the inverting input and output terminal of described operational amplifier OP, the earth terminal ground connection of described operational amplifier OP, described shunt resistance R4 is connected between the grid of the output terminal of described operational amplifier OP and described a plurality of NMOS pipes, the source class of described a plurality of NMOS pipes is by described shunt resistance R8 ground connection, the drain electrode of described a plurality of NMOS pipes is connected with the second end of described shunt resistance R2 by described shunt resistance R3.
Further, described a plurality of NMOS pipe is 2 NMOS pipes, the grid of described 2 NMOS pipes is connected to together and is connected with the output terminal of described operational amplifier by described shunt resistance R4, the source class of described 2 NMOS pipes is connected to together and is connected with ground by described shunt resistance R8, and the drain electrode of described 2 NMOS pipes is connected with the second end of described shunt resistance R2 by described shunt resistance R3.
adjustable active pull-up circuit that the utility model provides is made of common discrete component, make it form comparator circuit by electric current and the electric current that passes through operational amplifier OP by regulator potentiometer RL, make and to be transformed on the NMOS pipe by the bearing power that potentiometer RL bears, control by regulator potentiometer RL the power that the NMOS pipe bears, NMOS pipe in parallel is more, the bearing power of bearing is larger, adjustable loading range is also larger, improved the precision of load regulation by operational amplifier OP, more stable and the easy adjusting of the resistance of simultaneously load, longer service life.Solved existing load circuit or the power potentiometer cost is higher, relative volume is larger, and precision is lower, and resistance is stable not, the problem that life cycle is short.
Description of drawings
Fig. 1 is the circuit diagram of adjustable active load test circuit of providing of the utility model embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
Below in conjunction with specific embodiment, specific implementation of the present invention is described in detail:
As shown in Figure 1, the circuit of adjustable active load that the utility model embodiment provides comprises:
Shunt resistance R1, shunt resistance R2, shunt resistance R3, shunt resistance R4, shunt resistance R5, shunt resistance R6, shunt resistance R7, shunt resistance R8, potentiometer RL, filter capacitor C1, operational amplifier OP and a plurality of NMOS pipes in parallel;
the power supply termination of operational amplifier OP+VIN driving voltage, shunt resistance R1 and shunt resistance R6 are connected in series between the first end and the 3rd end of the second end of shunt resistance R2 and potentiometer RL, the second end ground connection of potentiometer RL, the first end of shunt resistance R2 is connected with the power end of operational amplifier OP, shunt resistance R7 is connected between the in-phase input end of the public connecting end of shunt resistance R6 and potentiometer RL and operational amplifier OP, the in-phase input end of filter capacitor C1 the first termination operational amplifier OP, filter capacitor C1 the second end ground connection, shunt resistance R5 is connected between the inverting input and output terminal of operational amplifier OP, the earth terminal ground connection of operational amplifier OP, shunt resistance R4 is connected between the grid of the output terminal of operational amplifier OP and a plurality of NMOS pipes, the source class of a plurality of NMOS pipes is by shunt resistance R8 ground connection, the drain electrode of a plurality of NMOS pipes is connected with the second end of shunt resistance R2 by shunt resistance R3.
Further, in the utility model embodiment, a plurality of NMOS pipes are 2 NMOS pipes, the grid of 2 NMOS pipes is connected to together and is connected with the output terminal of operational amplifier OP by shunt resistance R4, the source class of 2 NMOS pipes is connected to together and is connected with ground by shunt resistance R8, and the drain electrode of 2 NMOS pipes is connected with the second end of shunt resistance R2 by shunt resistance R3.
As the utility model one embodiment, the quantity of NMOS can arrange as required, in the testing tool of the large load of needs, 6,7 even more NMOS can be set be connected in parallel.
The below describes the principle of work of adjustable active load test circuit that the utility model embodiment provides:
With operational amplifier OP be connected with shunt resistance R2+the VIN driving voltage drives potentiometer RL and operational amplifier OP, make it form comparator circuit by electric current and the electric current that passes through operational amplifier OP by regulator potentiometer RL, make and to be transformed on the NMOS pipe by the bearing power that potentiometer RL bears, realize the adjustable of bearing power, control by regulator potentiometer RL the power that the NMOS pipe bears, realize that load is adjustable, improved the precision of load regulation by operational amplifier OP, the more stable and easy adjusting of the resistance of simultaneously load.
adjustable active pull-up circuit that the utility model provides is made of common discrete component, make it form comparator circuit by electric current and the electric current that passes through operational amplifier OP by regulator potentiometer RL, make and to be transformed on the NMOS pipe by the bearing power that potentiometer RL bears, control by regulator potentiometer RL the power that the NMOS pipe bears, NMOS pipe in parallel is more, the bearing power of bearing is larger, adjustable loading range is also larger, improved the precision of load regulation by operational amplifier OP, more stable and the easy adjusting of the resistance of simultaneously load, longer service life.Solved existing load circuit or the power potentiometer cost is higher, relative volume is larger, and precision is lower, and resistance is stable not, the problem that life cycle is short.
The above is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection domain of the present utility model.

Claims (2)

1. an adjustable active pull-up circuit, is characterized in that, described adjustable active load test circuit comprises:
Shunt resistance R1, shunt resistance R2, shunt resistance R3, shunt resistance R4, shunt resistance R5, shunt resistance R6, shunt resistance R7, shunt resistance R8, potentiometer RL, filter capacitor C1, operational amplifier OP and a plurality of NMOS pipes in parallel;
the power supply termination of described operational amplifier OP+VIN driving voltage, described shunt resistance R1 and described shunt resistance R6 are connected in series between the first end and the 3rd end of the second end of described shunt resistance R2 and described potentiometer RL, the second end ground connection of described potentiometer RL, the first end of described shunt resistance R2 is connected with the power end of described operational amplifier OP, described shunt resistance R7 is connected between the in-phase input end of the public connecting end of described shunt resistance R6 and described potentiometer RL and described operational amplifier OP, the in-phase input end of described filter capacitor C1 the first described operational amplifier OP of termination, described filter capacitor C1 the second end ground connection, described shunt resistance R5 is connected between the inverting input and output terminal of described operational amplifier OP, the earth terminal ground connection of described operational amplifier OP, described shunt resistance R4 is connected between the grid of the output terminal of described operational amplifier OP and described a plurality of NMOS pipes, the source class of described a plurality of NMOS pipes is by described shunt resistance R8 ground connection, the drain electrode of described a plurality of NMOS pipes is connected with the second end of described shunt resistance R2 by described shunt resistance R3.
2. adjustable active pull-up circuit as claimed in claim 1, it is characterized in that, described a plurality of NMOS pipe is 2 NMOS pipes, the grid of described 2 NMOS pipes is connected to together and is connected with the output terminal of described operational amplifier OP by described shunt resistance R4, the source class of described 2 NMOS pipes is connected to together and is connected with ground by described shunt resistance R8, and the drain electrode of described 2 NMOS pipes is connected with the second end of described shunt resistance R2 by described shunt resistance R3.
CN 201220728854 2012-12-26 2012-12-26 Adjustable active load circuit Expired - Fee Related CN203025328U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN 201220728854 CN203025328U (en) 2012-12-26 2012-12-26 Adjustable active load circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN 201220728854 CN203025328U (en) 2012-12-26 2012-12-26 Adjustable active load circuit

Publications (1)

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CN203025328U true CN203025328U (en) 2013-06-26

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109870661A (en) * 2019-02-25 2019-06-11 湖南福德电气有限公司 High power continuous variable tunable load and its application method, computer readable storage medium
CN110291410A (en) * 2017-01-06 2019-09-27 艾利维特半导体公司 Low-power active load
CN113109611A (en) * 2021-04-15 2021-07-13 歌瑞宇航电子(天津)有限公司 Active load for medium-low voltage power supply test

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110291410A (en) * 2017-01-06 2019-09-27 艾利维特半导体公司 Low-power active load
CN110291410B (en) * 2017-01-06 2021-10-26 艾利维特半导体公司 Low power active load
CN109870661A (en) * 2019-02-25 2019-06-11 湖南福德电气有限公司 High power continuous variable tunable load and its application method, computer readable storage medium
CN113109611A (en) * 2021-04-15 2021-07-13 歌瑞宇航电子(天津)有限公司 Active load for medium-low voltage power supply test
CN113109611B (en) * 2021-04-15 2022-09-13 歌瑞宇航电子(天津)有限公司 Active load for medium-low voltage power supply test

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C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20130626

Termination date: 20191226