CN202998033U - Time-delay reset circuit and portable terminal employing same - Google Patents
Time-delay reset circuit and portable terminal employing same Download PDFInfo
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- CN202998033U CN202998033U CN 201320004916 CN201320004916U CN202998033U CN 202998033 U CN202998033 U CN 202998033U CN 201320004916 CN201320004916 CN 201320004916 CN 201320004916 U CN201320004916 U CN 201320004916U CN 202998033 U CN202998033 U CN 202998033U
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Abstract
The utility model which is suitable for the electronic circuit field provides a time-delay reset circuit and a portable terminal employing the same. In the time-delay reset circuit and the portable terminal employing the same, a press key switch cooperates with a time-delay control circuit, a number of operation keys which the portable terminal is already provided with are employed, and any one of the keys or a combination of multiple keys are pressed for a long time; and therefore through cooperation with the circuit, a time-delay reset function can be realized when a system crashed. The time-delay reset circuit and the portable terminal employing the same are characterized by realization of a reset function, simple user operation, and good user experience.
Description
Technical field
The utility model belongs to electronic circuit field, relates in particular to a kind of time-delay reset circuit and adopts the portable terminal of this circuit.
Background technology
Along with the function of portable terminal from strength to strength, its software is also day by day complicated, thus the deadlock of portable terminal also becomes inevitable problem.In order to solve the deadlock problem of portable terminal device, except Software for Design must be improved as far as possible, often take two kinds of measures on hardware:
1, the independent reset key of design, its way is: perforate on shell, when deadlock occurs, use slender rod shaped thing to trigger reset key by the aperture of shell; 2, battery design is detachable, and when occurring crashing, the battery of dismantling gets final product.
For above-mentioned dual mode, now the battery design of many portable terminals is non-dismountable (for reducing costs and reducing thickness), and the user also is difficult to acceptance to the mode of using thin rod to trigger reset key.Like this, just cause the user to operate trouble and the user experiences relatively poor.
The utility model content
In order to solve the problems of the technologies described above, the purpose of this utility model is to provide a kind of time-delay reset circuit.
the utility model is to realize like this, a kind of time-delay reset circuit, described time-delay reset circuit comprises: the first resistance of termination first power supply, another termination first metal-oxide-semiconductor of described the first resistance, one end of the grid of the 3rd metal-oxide-semiconductor and the first key switch, the drain electrode of described the first metal-oxide-semiconductor connects second source by the second resistance, the source electrode of described the first metal-oxide-semiconductor is connected to an end of delay control circuit/electric capacity, this end of described delay control circuit/electric capacity is also connected to the drain electrode of the 3rd metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor, the source electrode of described the 3rd metal-oxide-semiconductor is by the 4th grounding through resistance, the drain electrode of described the second metal-oxide-semiconductor connects second source and exports reset signal by the drain electrode of the second metal-oxide-semiconductor by the 3rd resistance, the other end of described the first key switch, the other end of delay control circuit/electric capacity, the source grounding of the second metal-oxide-semiconductor.
Further, also be connected with the second key switch between described the second resistance and second source.
Further, also be connected the 3rd key switch between the other end of described delay control circuit/electric capacity and ground.
Further, also be connected with the second key switch between described the second resistance and second source.
Further, the first metal-oxide-semiconductor is identical with the control mode of the second metal-oxide-semiconductor, and the first metal-oxide-semiconductor is opposite with the control mode of the 3rd metal-oxide-semiconductor.
Further, described the first metal-oxide-semiconductor, the second metal-oxide-semiconductor adopt the PMOS pipe, and described the 3rd metal-oxide-semiconductor adopts the NMOS pipe.
Another purpose of the present utility model is to provide a kind of portable terminal, and described portable terminal adopts the described time-delay reset circuit of any one in claim 1-6.
In the utility model, coordinate by key switch and delay control circuit, by adopting the certain operations key that has had on portable terminal, utilize any or a plurality of key combination in these keys to carry out long-time push, coordinate this circuit, when system in case of system halt, can realize the time-delay reset function.Not only can realize resetting, and user's operation is simpler, better user experience.
Description of drawings
Fig. 1 is the circuit diagram of the time-delay reset circuit of the single-button switch that provides of the utility model the first embodiment;
Fig. 2 is the circuit diagram of the time-delay reset circuit of the single-button switch that provides of the utility model the second embodiment;
Fig. 3 is the circuit diagram of the time-delay reset circuit of two key switches of providing of the utility model the 3rd embodiment;
Fig. 4 is the circuit diagram of the time-delay reset circuit of two key switches of providing of the utility model the 4th embodiment;
Fig. 5 is the circuit diagram of the time-delay reset circuit of two key switches of providing of the utility model the 5th embodiment;
Fig. 6 is the circuit diagram of the time-delay reset circuit of two key switches of providing of the utility model the 6th embodiment;
Fig. 7 is the circuit diagram of the time-delay reset circuit of three key switches that provide of the utility model the 7th embodiment;
Fig. 8 is the circuit diagram of the time-delay reset circuit of three key switches that provide of the utility model the 8th embodiment.
Embodiment
In order to make the purpose of this utility model, technical scheme and advantage clearer, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
Consult Fig. 1,2, show the circuit of the time-delay reset circuit of the single-button switch that first and second embodiment of the utility model provides.
This time-delay reset circuit comprises: first resistance (R1) of termination first power supply (VBAT1 in figure), another termination first metal-oxide-semiconductor (T1) of described the first resistance (R1), the grid of the 3rd metal-oxide-semiconductor (T3) and an end of the first key switch (K).The drain electrode of described the first metal-oxide-semiconductor (T1) connects second source (VBAT2) by the second resistance (R2), and the source electrode of described the first metal-oxide-semiconductor (T1) is connected to an end of delay control circuit/electric capacity (C1).This end of described delay control circuit/electric capacity (C1) is also connected to the drain electrode of the 3rd metal-oxide-semiconductor (T3) and the grid of the second metal-oxide-semiconductor (T2), and the source electrode of described the 3rd metal-oxide-semiconductor (T3) is by the 4th resistance (R4) ground connection.The drain electrode of described the second metal-oxide-semiconductor (T2) connects second source (VBAT2) and exports reset signal by the drain electrode of the second metal-oxide-semiconductor (T2) by the 3rd resistance (R3).The source grounding of the other end of the other end of described the first key switch (K), delay control circuit/electric capacity (C1), the second metal-oxide-semiconductor (T2).
For the first embodiment (Fig. 1), the second embodiment (Fig. 2), it is all controlled by single the first key switch (K) and carries out time-delay reset.The main distinction of these two embodiment is, in the first embodiment, the source electrode of the first metal-oxide-semiconductor (T1) connects delay control circuit, and delay control circuit also is connected with the drain electrode of the 3rd metal-oxide-semiconductor (T3); In a second embodiment, the source electrode of the first metal-oxide-semiconductor (T1) connects the drain electrode of electric capacity (C1) and the 3rd metal-oxide-semiconductor (T3).
In the first embodiment, the second embodiment, the first metal-oxide-semiconductor (T1) is identical with the control mode of the second metal-oxide-semiconductor (T2), and the first metal-oxide-semiconductor (T1) is opposite with the control mode of the 3rd metal-oxide-semiconductor (T3), for example T1, T2 can adopt the PMOS pipe, and T3 adopts NMOS.
When pressing without key, the first metal-oxide-semiconductor (T1) is in closed condition, and the 3rd metal-oxide-semiconductor (T3) is in open mode, and the second metal-oxide-semiconductor (T2) is in closed condition, and at this moment, reset signal RESET is invalid.The first key switch (K) is pressed the time during more than or equal to setting-up time (delay control circuit design time), the first metal-oxide-semiconductor (T1) is in open mode, the 3rd metal-oxide-semiconductor (T3) is closed, delay control circuit starts, when delay time equals the design load of delay control circuit, the output control signal is opened the second metal-oxide-semiconductor (T2), thereby reset signal RESET is effective.If the first key switch (K) is pressed the time less than design time (delay control circuit design time), the first metal-oxide-semiconductor (T1) is opened, and the 3rd metal-oxide-semiconductor (T3) is closed.Delay time can not be exported control signal during less than or equal to the delay control circuit design load, and the second metal-oxide-semiconductor (T2) is closed, and reset signal RESET is invalid, and when the first key switch (K) discharged, T3 opened, and delay circuit is by clear 0.
Consult Fig. 3,5, Fig. 3, the 5th, the circuit diagram of the time-delay reset circuit of two key switches that the utility model the 3rd, five embodiment provide, the main distinction of itself and Fig. 1 is that it has increased a key switch (being respectively the 3rd key switch KT2, the second key switch KT1).For Fig. 3, also be connected the 3rd key switch (KT2) between the other end of described delay control circuit/electric capacity and ground.For Fig. 5, also be connected with the second key switch (KT1) between described the second resistance (R2) and second source (VBAT2).
Like this, just can control by 2 key switches and send effective reset signal, thus the mistake of having avoided single key switch to cause.
Consult Fig. 4,6, Fig. 4, the 6th, the main distinction of the 3rd, five embodiment in the circuit diagram of the time-delay reset circuit of two key switches that the utility model the 4th, six embodiment provide, itself and Fig. 3,5 is to adopt electric capacity to substitute delay control circuit.
Consult Fig. 7-8, Fig. 7, the 8th, the circuit diagram of the time-delay reset circuit of three key switches that the utility model the 7th, eight embodiment provide, the main distinction of itself and Fig. 5,6 the 5th, six embodiment is, it has increased the 3rd key switch (KT2) again on the basis of having used the first key switch (K), the second key switch (KT1).When thereby the user controls, need long three key switches of pressing, just can send effective reset signal.
During for the operation of a plurality of key switches, the first metal-oxide-semiconductor (T1) is identical with the control mode of the second metal-oxide-semiconductor (T2), and the first metal-oxide-semiconductor (T1) is opposite with the control mode of the 3rd metal-oxide-semiconductor (T3), T1 for example, and T2 is PMOS, T3 is NMOS.When pressing without key, T1 closes, and T3 opens, and T2 closes, and at this moment, reset signal RESET is invalid.Press K and press KT1 and/or KT2 (press 2 for Fig. 3-6, press 3 for Fig. 7-8), and the time of pressing more than or equal to design time (delay circuit design time), T1 opens, T3 closes, delay control circuit starts; When delay time equaled the delay control circuit design load, the output control signal was opened T2, and reset signal RESET is effective.Press K and press KT1 and/or KT2 (presses 2 for Fig. 3-6, press 3 for Fig. 7-8), and the time of pressing is less than design time (delay circuit design time), T1 opens, T3 closes, at this moment, delay time can not be exported control signal during less than or equal to the delay control circuit design load, and T2 closes, reset signal RESET is invalid, press K and press KT1 and/or KT2 (press 2 for Fig. 3-6, press 3 for Fig. 7-8), when discharging simultaneously, T3 opens, and delay circuit is by clear 0.
As embodiment of the present utility model, this key switch can adopt has had the certain operations key on portable terminal, as key, and upper line unit, lower line unit, left lateral key, right lateral key etc.; Can utilize any or a plurality of keyboard combination in these keys to carry out long-time push, (normal running of these keys when not crashing is to press the short time), cooperation when system in case of system halt, can realize the time-delay reset function with the circuit in the utility model.
The above is only preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of doing within spirit of the present utility model and principle, be equal to and replace and improvement etc., within all should being included in protection range of the present utility model.
Claims (7)
1. time-delay reset circuit, it is characterized in that, described time-delay reset circuit comprises: the first resistance of termination first power supply, another termination first metal-oxide-semiconductor of described the first resistance, one end of the grid of the 3rd metal-oxide-semiconductor and the first key switch, the drain electrode of described the first metal-oxide-semiconductor connects second source by the second resistance, the source electrode of described the first metal-oxide-semiconductor is connected to an end of delay control circuit/electric capacity, this end of described delay control circuit/electric capacity is also connected to the drain electrode of the 3rd metal-oxide-semiconductor and the grid of the second metal-oxide-semiconductor, the source electrode of described the 3rd metal-oxide-semiconductor is by the 4th grounding through resistance, the drain electrode of described the second metal-oxide-semiconductor connects second source and exports reset signal by the drain electrode of the second metal-oxide-semiconductor by the 3rd resistance, the other end of described the first key switch, the other end of delay control circuit/electric capacity, the source grounding of the second metal-oxide-semiconductor.
2. time-delay reset circuit according to claim 1, is characterized in that, also is connected with the second key switch between described the second resistance and second source.
3. time-delay reset circuit according to claim 1, is characterized in that, also has been connected the 3rd key switch between the other end of described delay control circuit/electric capacity and ground.
4. time-delay reset circuit according to claim 3, is characterized in that, also is connected with the second key switch between described the second resistance and second source.
5. time-delay reset circuit according to claim 1, is characterized in that, the first metal-oxide-semiconductor is identical with the control mode of the second metal-oxide-semiconductor, and the first metal-oxide-semiconductor is opposite with the control mode of the 3rd metal-oxide-semiconductor.
6. time-delay reset circuit according to claim 5, is characterized in that, described the first metal-oxide-semiconductor, the second metal-oxide-semiconductor adopt the PMOS pipe, and described the 3rd metal-oxide-semiconductor adopts the NMOS pipe.
7. a portable terminal, is characterized in that, described portable terminal adopts the described time-delay reset circuit of any one in claim 1-6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320004916 CN202998033U (en) | 2013-01-06 | 2013-01-06 | Time-delay reset circuit and portable terminal employing same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201320004916 CN202998033U (en) | 2013-01-06 | 2013-01-06 | Time-delay reset circuit and portable terminal employing same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN202998033U true CN202998033U (en) | 2013-06-12 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 201320004916 Expired - Lifetime CN202998033U (en) | 2013-01-06 | 2013-01-06 | Time-delay reset circuit and portable terminal employing same |
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| Country | Link |
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| CN (1) | CN202998033U (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105425927A (en) * | 2015-12-29 | 2016-03-23 | 青岛歌尔声学科技有限公司 | Multi-key reset circuit and electronic product provided with same |
| CN104135634B (en) * | 2014-07-31 | 2017-03-08 | 深圳创维－Rgb电子有限公司 | Reset circuit and television set |
| CN107733407A (en) * | 2017-11-03 | 2018-02-23 | 中国电子科技集团公司第五十四研究所 | A kind of fast charging and discharging and resetting time controllable electrification reset circuit |
-
2013
- 2013-01-06 CN CN 201320004916 patent/CN202998033U/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104135634B (en) * | 2014-07-31 | 2017-03-08 | 深圳创维－Rgb电子有限公司 | Reset circuit and television set |
| CN105425927A (en) * | 2015-12-29 | 2016-03-23 | 青岛歌尔声学科技有限公司 | Multi-key reset circuit and electronic product provided with same |
| CN105425927B (en) * | 2015-12-29 | 2019-03-12 | 歌尔智能科技有限公司 | More key reset circuits and electronic product with reset key |
| CN107733407A (en) * | 2017-11-03 | 2018-02-23 | 中国电子科技集团公司第五十四研究所 | A kind of fast charging and discharging and resetting time controllable electrification reset circuit |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: NUBIAN TECHNOLOGIES LTD. Free format text: FORMER NAME: SHENZHEN ZTE MOBILE TECH CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: A District No. 9018 Han innovation building in Nanshan District high tech Zone in Shenzhen city of Guangdong Province, North Central Avenue, 518000 floor 10 Patentee after: NUBIA TECHNOLOGY Co.,Ltd. Address before: A District No. 9018 Han innovation building in Nanshan District high tech Zone in Shenzhen city of Guangdong Province, North Central Avenue, 518000 floor 10 Patentee before: SHENZHEN ZTE MOBILE TELECOM Co.,Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20130612 |