CN202978936U

CN202978936U - System for correcting in-band flatness of digital repeater based on LMS algorithm

Info

Publication number: CN202978936U
Application number: CN 201220380800
Authority: CN
Inventors: 郝禄国; 杨建坡; 郑辉明; 余嘉池; 杨舜君; 曾文彬
Original assignee: Allwin Telecommunication Co Ltd
Current assignee: Allwin Telecommunication Co Ltd
Priority date: 2012-08-02
Filing date: 2012-08-02
Publication date: 2013-06-05
Anticipated expiration: 2022-08-02

Abstract

The utility model discloses a system for correcting the in-band flatness of a digital repeater based on an LMS algorithm, comprising an analog-to-digital conversion module, a digital analog conversion module and an FPGA module. The output terminal of the analog-to-digital conversion module is connected to the input terminal of the FPGA module; the output terminal of the FPGA module is connected to the input terminal of the digital analog conversion module; the output terminal of the digital analog conversion module is connected to the input terminal of the analog-to-digital conversion module; and the FPGA module includes a flatness correcting module and a digital signal processing module. According to the system for correcting the in-band flatness of a digital repeater based on LMS algorithm, automatic correction of the in-band flatness of the digital repeater is realized, the flatness correction hardware debug method by changing resistance and capacitance values are prevented, thereby the workload of the debugging personnel is minimized, the work efficiency of the debugging personnel is raised, and simultaneously, the usage of components is saved. The system with excellent performance for correcting the in-band flatness of a digital repeater based on the LMS algorithm can be widely applied for the communication field.

Description

System based on LMS algorithm correcting digital repeater inband flatness

Technical field

The utility model relates to the communications field, particularly a kind of system based on LMS adaptive algorithm correcting digital repeater inband flatness.

Background technology

Because there is the poor problem of consistency in the zero device of digital high-frequency amplification station, thereby the inconsistent phenomenon of inband flatness often can appear in digital high-frequency amplification station, and this inband flatness is inconsistent need to be proofreaied and correct by certain means.Existing correcting scheme is mainly by hardware debug, namely constantly changes the correction that the value of resistance and electric capacity in the zero device of digital high-frequency amplification station realizes flatness.But this correcting scheme need to use the components and parts of different parameters value, thereby has increased the workload of producing the commissioning staff, has reduced commissioning staff's operating efficiency, has also caused the waste of components and parts simultaneously.

The utility model content

In order to solve above-mentioned technical problem, the utility model provides a kind of system based on LMS adaptive algorithm correcting digital repeater inband flatness.

The utility model is that the technical scheme that its technical problem of solution proposes is:

A kind of system based on LMS algorithm correcting digital repeater inband flatness, comprise analog-to-digital conversion module, D/A converter module and FPGA module, the output of analog-to-digital conversion module is connected to the input of FPGA module, the output of FPGA module is connected to the input of D/A converter module, the output of D/A converter module is connected to the input of analog-to-digital conversion module, and described FPGA module comprises correcting flatness module and digital signal processing module.

Further, the output of described D/A converter module with the input of analog-to-digital conversion module by RF-coupled connection.

Further, described digital signal processing module comprises Digital Down Converter Module, and Digital Down Converter Module is connected with filtering extraction module, the first compensating filter module, on-off switch, baseband processing module, interpolation filtering module and Digital Up Convert module in turn; The input of Digital Down Converter Module is connected with the output of analog-to-digital conversion module; The output of Digital Up Convert module is connected with the input of D/A converter module; The common port of on-off switch connects the input of baseband processing module, and an end of the non-common port of on-off switch connects the output of the first compensating filter module.

Further, described correcting flatness module comprises LMS algoritic module, training sequence module and EPROM module; The first input end of described LMS algoritic module connects the output of filtering extraction module, and the second input of LMS algoritic module connects the output of training sequence module, and the output of LMS algoritic module connects the input of EPROM module; The output of EPROM module connects the first compensating filter module; The output of training sequence module also is connected with the other end of the non-common port of described on-off switch.

Further, described LMS algoritic module comprises channel estimation module, the second compensating filter module and subtracter; The first input end of the first input end of channel estimation module and the second compensating filter module and the output of filtering extraction module are connected, the second input of channel estimation module connects the output of subtracter, the output of the second input connecting channel estimation module of the second compensating filter module, the first input end of subtracter is connected with the output of the second compensating filter module, the second input of subtracter is connected with the output of training sequence module, and the output of channel estimation module also is connected with the input of EPROM module.

The beneficial effects of the utility model are: the system based on LMS algorithm correcting digital repeater inband flatness of the present utility model, be designed with the correcting flatness module, the training sequence that training sequence module in this module produces is through after a series of conversion, produce a compensating filter coefficient under the effect of LMS algoritic module, just can realize the correction of the inband flatness of repeater by this compensation filter coefficient to the correction of the first compensating filter module.Avoid using the hardware debug method in current scheme, namely realized the correction of flatness by continuous change resistance and capacitance, thereby reduced commissioning staff's workload, increased commissioning staff's operating efficiency, saved simultaneously the use of components and parts.

Description of drawings

The utility model is described in further detail below in conjunction with drawings and Examples.

Fig. 1 is based on the structured flowchart of the system of LMS adaptive algorithm correcting digital repeater inband flatness;

Fig. 2 is the internal structure block diagram of FPGA module;

Fig. 3 is the internal structure block diagram of LMS algoritic module.

Reference numeral:

1. analog-to-digital conversion module, 2. D/A converter module, 3. FPGA module, 4. correcting flatness module, 5. digital signal processing module, 6. Digital Down Converter Module, 7. filtering extraction module, 8. the first compensating filter module, 9. on-off switch, 10. baseband processing module, 11. interpolation filtering module, 12. the Digital Up Convert module, 13.LMS algoritic module, 14. training sequence modules; 15.EPROM module; 16. channel estimation module, 17. second compensating filter modules, 18. subtracters.

Embodiment

For convenience of following description, the definition of some basic names of given first:

LMS algorithm (Least Mean Square algorithm): least mean square algorithm;

EPROM (Erasable Programmable Read-Only Memory): the read-only memory of erasable programmable;

FPGA (Field Programmable Gate Array): field programmable gate array.

With reference to Fig. 1, the utility model provides a kind of system based on LMS algorithm correcting digital repeater inband flatness, comprise analog-to-digital conversion module 1, D/A converter module 2 and FPGA module 3, the output of analog-to-digital conversion module 1 is connected to the input of FPGA module 3, the output of FPGA module 3 is connected to the input of D/A converter module 2, the output of D/A converter module 2 is connected to the input of analog-to-digital conversion module 1, and described FPGA module 3 comprises correcting flatness module 4 and digital signal processing module 5.

Further, the output of described D/A converter module 2 with the input of analog-to-digital conversion module 1 by RF-coupled connection.

Further, with reference to Fig. 2, described digital signal processing module 5 comprises Digital Down Converter Module 6, and Digital Down Converter Module 6 is connected with filtering extraction module 7, the first compensating filter module 8, on-off switch 9, baseband processing module 10, interpolation filtering module 11 and Digital Up Convert module 12 in turn; The input of Digital Down Converter Module 6 is connected with the output of analog-to-digital conversion module 1; The output of Digital Up Convert module 12 is connected with the input of D/A converter module 2; The common port of on-off switch 9 connects the input of baseband processing module 12, and an end of the non-common port of on-off switch 9 connects the output of the first compensating filter module 8.

Further, described correcting flatness module 4 comprises LMS algoritic module 13, training sequence module 14 and EPROM module 15; The first input end of described LMS algoritic module 13 connects the output of filtering extraction module 7, and the second input of LMS algoritic module 13 connects the output of training sequence module 14, and the output of LMS algoritic module 13 connects the input of EPROM module 15; The output of EPROM module 15 connects the first compensating filter module 8; The output of training sequence module 14 also is connected with the other end of described on-off switch 9 non-common ports.

further, with reference to Fig. 3, described LMS algoritic module 13 comprises channel estimation module 16, the second compensating filter module 17 and subtracter 18, the first input end of the first input end of channel estimation module 16 and the second compensating filter module 17 and the output of filtering extraction module 7 are connected, the second input of channel estimation module 16 connects the output of subtracter 18, the output of the second input connecting channel estimation module 16 of the second compensating filter module 17, the first input end of subtracter 18 is connected with the output of the second compensating filter module 17, the second input of subtracter 18 is connected with the output of training sequence module 14, the output of channel estimation module 16 also is connected with the input of EPROM module 15.

The bearing calibration of a kind of system based on LMS algorithm correcting digital repeater inband flatness of the present utility model comprises the following steps:

A, training sequence module 14 produce a training sequence signal D (n)

B, open the switch of training sequence module 14 and baseband processing module 10;

C, training sequence signal D (n)After Base-Band Processing, interpolation filtering, Digital Up Convert, become analog if signal by D/A converter module;

D, access RF-coupled connection, described analog if signal by the RF-coupled input that is input to analog-to-digital conversion module 1, is carried out analog-to-digital conversion, Digital Down Convert, filtering extraction to it, obtain filtering signal X (n)

E, with filtering signal X (n)With former training sequence signal D (n)Carry out together the LMS algorithm and upgrade, obtain best compensating filter coefficient;

F, with described compensating filter coefficient storage in EPROM module 15;

G, disconnect RF-coupled connection, open the switch of the first compensating filter module 8 and baseband processing module 10, the compensating filter coefficient in EPROM module 15 is imported in the first compensating filter module 8, can realize correcting flatness.

Further, described step e comprises:

A1, according to filtering signal X (n)Calculate the impulse response of channel W (n)

B1, according to the impulse response of described channel W (n), simulation obtains the training sequence signal D (n)Inversion model signal through channel Y (n)

C1, calculation of filtered signal X (n)And inversion model signal Y (n)Difference E (n): E (n)=x (n)-y (n)

D1, according to described difference E (n)Adjust the tap coefficient of channel; Repeating step A1 to D1 is until difference E (n)Be in preset range;

E1, obtain the impulse response that obtains at last W (n), namely obtain best compensating filter coefficient.

Here, according to difference E (n)Constantly adjust the tap coefficient of channel impulse response, order W (n)More near real channel, when E (n)Converge to preset range with interior i.e. locking W (n)Update coefficients no longer, this moment W (n)I.e. best compensating filter coefficient.

Further, the LMS algorithm of described step e upgrades, and adopts following formula, change into the form of real number according to the complex operation equation of LMS algorithm:

The tap input vector:

Desired signal:

The tap weights coefficient:

Filter output:

Estimation error signal:

Corresponding renewal equation:

Wherein I, Q represent the cross stream component on complex plane and the longitudinal component after signal carries out down-conversion.

More than that better enforcement of the present utility model is illustrated, but the utility model is created and is not limited to described embodiment, those of ordinary skill in the art also can make all equivalent variations or replacement under the prerequisite of the utility model spirit, the modification that these are equal to or replacement all are included in the application's claim limited range.

Claims

1. based on the system of LMS algorithm correcting digital repeater inband flatness, comprise analog-to-digital conversion module (1), D/A converter module (2) and FPGA module (3), the output of analog-to-digital conversion module (1) is connected to the input of FPGA module (3), the output of FPGA module (3) is connected to the input of D/A converter module (2), the output of D/A converter module (2) is connected to the input of analog-to-digital conversion module (1), it is characterized in that: described FPGA module (3) comprises digital signal processing module (5).

2. the system based on LMS algorithm correcting digital repeater inband flatness according to claim 1 is characterized in that: the output of described D/A converter module (2) with the input of analog-to-digital conversion module (1) by RF-coupled connection.

3. the system based on LMS algorithm correcting digital repeater inband flatness according to claim 2, it is characterized in that: described digital signal processing module (5) comprises Digital Down Converter Module (6), and Digital Down Converter Module (6) is connected with filtering extraction module (7), the first compensating filter module (8), on-off switch (9), baseband processing module (10), interpolation filtering module (11) and Digital Up Convert module (12) in turn; The input of Digital Down Converter Module (6) is connected with the output of analog-to-digital conversion module (1); The output of Digital Up Convert module (12) is connected with the input of D/A converter module (2); The common port of on-off switch (9) connects the input of baseband processing module (12), and an end of the non-common port of on-off switch (9) connects the output of the first compensating filter module (8).