CN202949375U - Five-level inversion unit and five-level inverter - Google Patents

Five-level inversion unit and five-level inverter Download PDF

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Publication number
CN202949375U
CN202949375U CN 201220531871 CN201220531871U CN202949375U CN 202949375 U CN202949375 U CN 202949375U CN 201220531871 CN201220531871 CN 201220531871 CN 201220531871 U CN201220531871 U CN 201220531871U CN 202949375 U CN202949375 U CN 202949375U
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capacitor
inversion unit
direct current
direct
level
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倪华
代尚方
李晓迅
汪洪亮
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Sungrow Power Supply Co Ltd
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Sungrow Power Supply Co Ltd
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Abstract

A five-level inversion unit comprises eight switch devices in inverse-parallel connection with diodes and two diodes in series connection with the switch devices. Compared with the prior art, the five-level inversion unit guarantees that a channel is provided for current in single-phase and multi-phase application, simultaneously guarantees that semiconductor devices of a whole inverter are few, the size is small, the cost is low, the loss is small simultaneously, and the efficiency is high. The five-level inversion unit has five active power operating modes and five reactive power operating modes, meets the requirements of an alternating current load or an alternating current power grid for reactive power, and is wide in application range in comparison with the prior art. Besides, due to the fact that each level has a corresponding active power path and a reactive power path, total harmonic distortion of output current is extremely small when the active power or the reactive power is sent.

Description

A kind of five level inverse conversion unit and five-electrical level inverters
Technical field
The application relates to electric and electronic technical field, particularly a kind of five level inverse conversion unit and have the five-electrical level inverter of this five level inverse conversion unit.
Background technology
The large capacity occasion of middle pressure, multi-electrical level inverter is widely used, and present five-electrical level inverter is mainly diode-clamped.The below is introduced the diode-clamped five-level inverter.
Referring to Fig. 1, this figure is the five-electrical level inverter topological diagram of disclosed diode-clamped in prior art.
Shown in Figure 1 is the topological structure of half-bridge five-electrical level inverter.Diode is used to each switching device to carry out voltage clamp.For example, the first diode DB1 is used for the voltage clamp of switching element T 1 lower end is positioned at the lower end of the first capacitor C 1; The second diode DB2 is used for the voltage clamp of switching element T 5 lower ends is positioned at the lower end of the first capacitor C 1.Other diodes DB3, DB4, DB5 and DB6 are similar, do not repeat them here.
Because clamping diode need to be blocked many times of level voltages, usually need the diode series connection of a plurality of same nominal values, these diodes are together in series and jointly bear the voltage that in Fig. 1, diode DB2 bears.Due to the dispersiveness of diode and the impact of stray parameter, the pressure that the diode that nominal value is identical can bear is difference to some extent also, is together in series like this to cause the diode two ends overvoltage that has.Therefore, need equalizer circuit measure and very large RC absorbing circuit, but will cause systems bulky like this, cost increases, and loss is more, and efficient is lower.
The utility model content
The application's technical problem to be solved is to provide a kind of five level inverse conversion unit and five-electrical level inverters, and bulky in order to solve in prior art inverter system, cost increases, and the technical problem such as loss is more, and efficient is lower.
The application discloses a kind of five level inverse conversion unit, comprises that the first switching device, the 3rd switching device, the 4th switching device, the 5th switching device, second switch device, the 6th switching device, minion close device, the 8th switch device, the 9th diode and the tenth diode; Diode of the equal reverse parallel connection of each described switching device is respectively the first diode, the 3rd diode, the 4th diode, the 5th diode, the second diode, the 6th diode, the 7th diode, the 8th diode; The first direct-flow input end of this inversion unit is connected with the first end of the 3rd switching device; The second direct-flow input end is connected with the second end of the 6th switching device; The 3rd direct-flow input end is connected with the first end of the 4th switching device; The 4th direct-flow input end is connected with the second end that minion is closed device; The 5th direct-flow input end is connected with the anode of the 9th diode and the negative electrode of the tenth diode; The second end of the 4th switching device is connected with the negative electrode of the first end of the first switching device and the 9th diode; The second end of the 3rd switching device is connected with the second end of the 5th switching device; The first end of the 6th switching device is connected with the first end of the 8th switch device; The first end that minion is closed device is connected with the second end of second switch device and the anode of the tenth diode; The second end of the second end of the first switching device, the first end of the 5th switching device, the 8th switch device, the first end of second switch device are connected, and are connected with the output node that exchanges of this inversion unit.
Further, this five level inverse conversion unit has ten operation modes, be respectively: the first operation mode: the first switching device and the 9th diode current flow, current path: the interchange output node of the 5th direct-flow input end-the 9th diode-first switching device-this inversion unit; The second operation mode: the 3rd switching device and the 5th diode current flow, current path is: the first direct-flow input end-the 3rd switching device-the 5th diode-interchange output node; The 3rd operation mode: the first switching device and the 4th switching device conducting, current path is: the 3rd direct-flow input end-the 4th switching device-first switching device-interchange output node; The 4th operation mode: second switch device and the tenth diode current flow, current path is: exchange output node-second switch device-Di ten diodes-the 5th direct-flow input end; The 5th operation mode: the 6th switching device and the 8th diode current flow, current path is: exchange output node-Di eight diodes-the 6th switching device-second direct-flow input end; The 6th operation mode: second switch device and minion are closed break-over of device, and current path is: exchange output node-second switch device-Di minion and close device-Di four direct-flow input ends; The 7th operation mode: the first diode and the 4th diode current flow, current path is: exchange output node-first diode-the 4th diode-the 3rd direct-flow input end; The 8th operation mode: the 7th diode and the second diode current flow, current path is: the 4th direct-flow input end-the 7th diode-second diode-interchange output node; The 9th operation mode: the 5th switching device and the 3rd diode current flow, current path is: exchange output node-Di five switching devices-the 3rd diode-first direct-flow input end; The tenth operation mode: the 6th diode and the 8th switch break-over of device, current path is: the second direct-flow input end-the 6th diode-the 8th switch device-interchange output node.
Corresponding varying level is counted in situation, and the driving signal of each switching device of this five level inverse conversion unit is respectively:
+ 2 level: the driving signal of the first switching device and the 4th switching device is high level, and the driving signal of the 3rd switching device is high level or low level, and the driving signal of rest switch device is low level;
+ 1 level: the driving signal of the first switching device, the 3rd switching device and the 5th switching device is high level, and the driving signal of rest switch device is low level;
0 level: the driving signal of the first switching device, second switch device is high level, and the driving signal of rest switch device is low level;
-1 level: the driving signal of second switch device, the 6th switching device, the 8th switch device is high level, and the driving signal of rest switch device is low level;
-2 level: the driving signal that second switch device, minion are closed device is high level, and the driving signal of the 6th switching device is high level or low level, and the driving signal of rest switch device is low level.
Disclosed herein as well is a kind of five-electrical level inverter, comprise above-mentioned five level inverse conversion unit, wherein: the first direct current positive electricity flush end is connected with the first direct-flow input end, the second direct current positive electricity flush end is connected with the 3rd direct-flow input end, direct current zero level end is connected with the 5th direct-flow input end, the first direct current negative electricity flush end is connected with the second direct-flow input end, and the second direct current negative electricity flush end is connected with the 4th direct-flow input end; The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively; The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively; The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical; The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor; The first ac output end of this inverter is connected with the output node that exchanges of inversion unit, and the second ac output end of this inverter is connected with the 5th direct-flow input end of inversion unit.
Further, above-mentioned five-electrical level inverter also comprises the filtration module that is formed by inductance L 501 and capacitor C 501, wherein: inductance L 501 is connected between the first ac output end of the interchange output node of inversion unit and this inverter, and capacitor C 501 is connected between first ac output end and the second ac output end of this inverter.
Disclosed herein as well is a kind of five-electrical level inverter, comprise two above-mentioned five level inverse conversion unit: the first inversion unit and the second inversion unit; The first direct current positive electricity flush end is connected with each first direct-flow input end of the first inversion unit and the second inversion unit; The first direct current negative electricity flush end is connected with each second direct-flow input end of the first inversion unit and the second inversion unit; The second direct current positive electricity flush end is connected with each the 3rd direct-flow input end of the first inversion unit and the second inversion unit; The second direct current negative electricity flush end is connected with each the 4th direct-flow input end of the first inversion unit and the second inversion unit; Direct current zero level end is connected with each the 5th direct-flow input end of the first inversion unit and the second inversion unit; The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively; The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively; The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical; The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor; The output node that respectively exchanges of the first inversion unit and the second inversion unit is connected with the second ac output end with the first ac output end of this inverter respectively.
Further, above-mentioned five-electrical level inverter also comprises inductance L 1701, inductance L 1702 and capacitor C 1701, wherein: inductance L 1701 is connected between the first ac output end of the interchange output node of the first inversion unit and this inverter, inductance L 1702 is connected between the second ac output end of the interchange output node of the second inversion unit and this inverter, and capacitor C 1701 is connected between first ac output end and the second ac output end of this inverter.
Disclosed herein as well is a kind of five-electrical level inverter, comprise three above-mentioned five level inverse conversion unit: the first inversion unit, the second inversion unit and the 3rd inversion unit; The first direct current positive electricity flush end is connected with each first direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit; The first direct current negative electricity flush end is connected with each second direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit; The second direct current positive electricity flush end is connected with each the 3rd direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit; The second direct current negative electricity flush end is connected with each the 4th direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit; Direct current zero level end is connected with each the 5th direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit; The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively; The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively; The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical; The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor; The output node that respectively exchanges in the first inversion unit, the second inversion unit and the 3rd inversion unit is connected with the first ac output end, the second ac output end and the 3rd ac output end of this inverter respectively.
Further, above-mentioned five-electrical level inverter also comprises inductance L 1901, inductance L 1902, inductance L 1903, capacitor C 1901, capacitor C 1902 and capacitor C 1903, and wherein: the interchange output node of the first inversion unit is connected with the output node that exchanges of the second inversion unit by inductance L 1901, capacitor C 1901, capacitor C 1902 and the inductance L 1902 of series connection successively; The interchange output node of the 3rd inversion unit is connected with the connecting line of capacitor C 1901 with capacitor C 1902 with capacitor C 1903 by the inductance L 1903 of series connection successively; The connecting line of inductance L 1901 and capacitor C 1901 is connected with the first ac output end of this inverter, the connecting line of inductance L 1902 and capacitor C 1902 is connected with the second ac output end of this inverter, and the connecting line of inductance L 1903 and capacitor C 1903 is connected with the 3rd ac output end of this inverter.
Disclosed herein as well is a kind of five-electrical level inverter, comprise four above-mentioned five level inverse conversion unit: the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit; The first direct current positive electricity flush end is connected with each first direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit; The first direct current negative electricity flush end is connected with each second direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit; The second direct current positive electricity flush end is connected with each the 3rd direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit; The second direct current negative electricity flush end is connected with each the 4th direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit; Direct current zero level end is connected with each the 5th direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit; The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively; The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively; The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical; The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor; The output node that respectively exchanges in the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit is connected with the first ac output end, the second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.
Further, above-mentioned five-electrical level inverter also comprises inductance L 2201, inductance L 2202, inductance L 2203, capacitor C 2201, capacitor C 2202 and capacitor C 2203, and wherein: the interchange output node of the second inversion unit is connected with the output node that exchanges of the 3rd inversion unit by inductance L 2201, capacitor C 2201, capacitor C 2202 and the inductance L 2202 of series connection successively; The interchange output node of the 4th inversion unit is connected with the connecting line of capacitor C 2201 with capacitor C 2202 with capacitor C 2203 by the inductance L 2203 of series connection successively; The interchange output node of the first inversion unit is connected with the connecting line of capacitor C 2201, capacitor C 2202; The connecting line of inductance L 2201, capacitor C 2201 is connected with the first ac output end of this inverter, the connecting line of capacitor C 2202 and inductance L 2202 is connected with the second ac output end of this inverter, and the connecting line of inductance L 2203 and capacitor C 2203 is connected with the 3rd ac output end of this inverter.
With respect to prior art, the disclosed five level inverse conversion unit of the application comprise that the first switching device, the 3rd switching device, the 4th switching device, the 5th switching device, second switch device, the 6th switching device, the minion that are connected to respectively anti-paralleled diode close device, the 8th switch device, and two clamp diodes, i.e. the 9th diode and the tenth diode; With respect to prior art, semiconductor device is few, has reduced volume and cost, has reduced loss, has improved efficient, need not extra equalizer circuit measure; In addition, the application disclosed five level inverse conversion unit have ten kinds of operation modes, comprise five kinds of meritorious operation modes and five kinds of idle operation modes, satisfy AC load or AC network to idle demand, with respect to prior art, and applied range; And because each level has corresponding meritorious path and idle path, guaranteed inversion unit when transmission is meritorious or idle, THD is very little for output current.
With respect to prior art, the disclosed five-electrical level inverter of the application guarantees that the semiconductor device of whole inverter is few when realizing single-phase and heterogeneous application, reduced volume and cost, has reduced loss, has improved efficient, need not extra equalizer circuit measure; In addition, the disclosed five-electrical level inverter of the application has ten kinds of operation modes, comprises five kinds of meritorious operation modes and five kinds of idle operation modes, satisfies AC load or AC network to idle demand, with respect to prior art, and applied range; And because each level has corresponding meritorious path and idle path, guaranteed inverter when transmission is meritorious or idle, THD is very little for output current.
Certainly, arbitrary product of enforcement the application might not need to reach simultaneously above-described all advantages.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the present application, during the below will describe embodiment, the accompanying drawing of required use is done to introduce simply, apparently, accompanying drawing in the following describes is only some embodiment of the application, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is diode-clamped five-level inverter topology figure in prior art;
Fig. 2 is the topological diagram of the disclosed five level inverse conversion unit embodiment one of the application;
Fig. 3 is the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment one;
Fig. 4 is the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment two;
Fig. 5 is the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three;
Fig. 6 is the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment four;
Fig. 7 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the first operation mode;
Fig. 8 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the second operation mode;
Fig. 9 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 3rd operation mode;
Figure 10 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 4th operation mode;
Figure 11 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 5th operation mode;
Figure 12 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 6th operation mode;
Figure 13 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 7th operation mode;
Figure 14 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 8th operation mode;
Figure 15 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the 9th operation mode;
Figure 16 is the topological diagram that the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three is in the tenth operation mode;
Figure 17 is the equivalent modules figure of the disclosed five level inverse conversion unit embodiment one of the application;
Figure 18 is the topological diagram of the disclosed single-phase full bridge five-electrical level inverter of the application embodiment four;
Figure 19 is the topological diagram of the disclosed single-phase full bridge five-electrical level inverter of the application embodiment five;
Figure 20 is the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment six;
Figure 21 is the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment seven;
Figure 22 is the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment eight;
Figure 23 is the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment nine;
Figure 24 is the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment ten;
Figure 25 is the waveform of single-phase semi-bridge five-electrical level inverter output inverter voltage U shown in Figure 5 and output grid-connected current i.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is clearly and completely described, obviously, described embodiment is only the application's part embodiment, rather than whole embodiment.Based on the embodiment in the application, those of ordinary skills are not making the every other embodiment that obtains under the creative work prerequisite, all belong to the scope of the application's protection.
With reference to figure 2, it shows the topological diagram of the disclosed a kind of five level inverse conversion unit embodiment one of the application, and described five level inverse conversion unit comprise: comprise that the first switching element T 1, the 3rd switching element T A1, the 4th switching element T A2, the 5th switching element T A3, second switch device T2, the 6th switching element T B1, minion close device TB2, the 8th switch device TB3, the 9th diode DF1 and the tenth diode DF2; Diode of the equal reverse parallel connection of each described switching device is respectively the first diode D1, the 3rd diode DA1, the 4th diode DA2, the 5th diode DA3, the second diode D2, the 6th diode DB1, the 7th diode DB2, the 8th diode DB3; The first direct-flow input end M1 of this inversion unit is connected with the first end of the 3rd switching element T A1; The second direct-flow input end M2 is connected with the second end of the 6th switching element T B1; The 3rd direct-flow input end M3 is connected with the first end of the 4th switching element T A2; The 4th direct-flow input end M4 is connected with the second end that minion is closed device TB2; The 5th direct-flow input end M5 is connected with the anode of the 9th diode DF1 and the negative electrode of the tenth diode DF2; The second end of the 4th switching element T A2 is connected with the negative electrode of the first end of the first switching element T 1 and the 9th diode DF1; The second end of the 3rd switching element T A1 is connected with the second end of the 5th switching element T A3; The first end of the 6th switching element T B1 is connected with the first end of the 8th switch device TB3; The first end that minion is closed device TB2 is connected with the second end of second switch device T2 and the anode of the tenth diode DF2; The second end of the second end of the first switching element T 1, the first end of the 5th switching element T A3, the 8th switch device TB3, the first end of second switch device T2 are connected, and are connected with the output node that exchanges of this inversion unit.
Wherein, above switching device can be managed for IGBT, MOSFET manages, IGCT manages or the IEGT pipe.Be understandable that, above switching device also can be selected the switching device of other types.The diode of above and switching device reverse parallel connection can be diode independently, can be also and switching device encapsulation and integration diode together.
Need to prove, when switching device was selected IGBT, the first end of above-mentioned each switching device referred to collector electrode, and the second end refers to the generating utmost point; When switching device was selected MOSFET, the first end of above-mentioned each switching device referred to drain electrode, and the second end refers to source electrode.Can know by inference according to the characteristic of switching device, can also select the switching device of other types according to practical application.
With reference to Figure 17, it shows the disclosed five level inverse conversion unit embodiment one equivalent module map of the application.In practical application, the application disclosed five level inverse conversion unit can also be packaged into module or chip uses according to Figure 17.
With respect to prior art, the disclosed five level inverse conversion unit of the application comprise that the first switching element T 1, the 3rd switching element T A1, the 4th switching element T A2, the 5th switching element T A3, second switch device T2, the 6th switching element T B1, the minion that are connected to respectively anti-paralleled diode close device TB2, the 8th switch device TB3, and two clamp diodes are the 9th diode DF1 and the tenth diode DF2, with respect to prior art, semiconductor device is few, volume and cost have been reduced, reduced loss, improve efficient, need not extra equalizer circuit measure.
The disclosed five level inverse conversion unit of the application have ten kinds of operation modes, comprise five kinds of meritorious operation modes and five kinds of idle operation modes.
Five kinds of meritorious operation modes comprise the first operation mode, the second operation mode, the 3rd operation mode, the 5th operation mode, the 6th operation mode, and are specific as follows:
The first operation mode: the first switching element T 1 and the 9th diode DF1 conducting, current path: the interchange output node of the 5th direct-flow input end M5-the 9th diode DF1-first this inversion unit of switching element T 1-;
The second operation mode: the 3rd switching element T A1 and the 5th diode DA3 conducting, current path is: the first direct-flow input end M1-the 3rd switching element T A1-the 5th diode DA3-exchanges output node;
The 3rd operation mode: the first switching element T 1 and the 4th switching element T A2 conducting, current path is: the 3rd direct-flow input end M3-the 4th switching element T A2-the first switching element T 1-exchanges output node;
The 5th operation mode: the 6th switching element T B1 and the 8th diode DB3 conducting, current path is: exchange output node-Di eight diode DB3-the 6th switching element T B1-the second direct-flow input end M2;
The 6th operation mode: second switch device T2 and minion are closed device TB2 conducting, and current path is: exchange output node-second switch device T2-minion and close device TB2-the 4th direct-flow input end M4.
Five kinds of idle operation modes comprise the 4th operation mode, the 7th operation mode, the 8th operation mode, the 9th operation mode, the tenth operation mode, and are specific as follows:
The 4th operation mode: second switch device T2 and the tenth diode DF2 conducting, current path is: exchange output node-second switch device T2-the tenth diode DF2-the 5th direct-flow input end M5;
The 7th operation mode: the first diode D1 and the 4th diode DA2 conducting, current path is: exchange output node-first diode D1-the 4th diode DA2-the 3rd direct-flow input end M3;
The 8th operation mode: the 7th diode DB2 and the second diode D2 conducting, current path is: the 4th direct-flow input end M4-the 7th diode DB2-the second diode D2-exchanges output node;
The 9th operation mode: corresponding to Figure 15, the 5th switching element T A3 and the 3rd diode DA1 conducting, current path is: exchange output node-Di five switching element T A3-the 3rd diode DA1-the first direct-flow input end M1;
The tenth operation mode: the 6th diode DB1 and the 8th switch device TB3 conducting, current path is: the second direct-flow input end M2-the 6th diode DB1-the 8th switch device TB3-exchanges output node.
From the above, the application disclosed five level inverse conversion unit have ten kinds of operation modes, comprise five kinds of meritorious operation modes and five kinds of idle operation modes, satisfy AC load or AC network to idle demand, with respect to prior art, and applied range; And because each level has corresponding meritorious path and idle path, guaranteed inversion unit when transmission is meritorious or idle, THD is very little for output current.
The application is the driving signal of disclosed five eight switching devices in level inverse conversion unit also, sees table:
Level number T1 TA1 TA2 TA3 T2 TB1 TB2 TB3
+ 2 level 1 0 or 1 1 0 0 0 0 0
+ 1 level 1 1 0 1 0 0 0 0
0 level 1 0 0 0 1 0 0 0
-1 level 0 0 0 0 1 1 0 1
-2 level 0 0 0 0 1 0 or 1 1 0
Need to prove, the numeral in table " 1 ", " 0 " represent respectively is that the driving signal of each switching device is high and low level.Need to prove, 0 level ,+1 level ,+period that 2 level are corresponding, the driving signal of the first switching element T 1 is high level always, but the first 1 of switching element T is in period conducting corresponding to 0 level and+2 level, in fact not conducting of period corresponding to+1 level, make the driving Design of Signal easy, reduced simultaneously turn-on consumption; In like manner, in 0 level ,-1 level ,-2 periods corresponding to level, the driving signal of second switch device T2 is high level always, but second switch device T2 only in 0 level and period conducting corresponding to-2 level, in period not conducting corresponding to-1 level; The driving design of rest switch device in like manner repeats no more herein.
With reference to figure 3, the topological diagram that it shows the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment one comprises above-mentioned five level inverse conversion unit, wherein:
The first direct current positive electricity flush end PV1+ is connected with the first direct-flow input end M1, the second direct current positive electricity flush end PV2+ is connected with the 3rd direct-flow input end M3, direct current zero level end PV0 is connected with the 5th direct-flow input end M5, the first direct current negative electricity flush end PV1-is connected with the second direct-flow input end M2, and the second direct current negative electricity flush end PV2-is connected with the 4th direct-flow input end M4;
The first direct current positive electricity flush end PV1+ is connected with the first direct current negative electricity flush end PV1-with the second dc capacitor CB1 by the first dc capacitor CA1 of series connection successively;
The second direct current positive electricity flush end PV2+ is connected with the second direct current negative electricity flush end PV2-with the 4th dc capacitor CB2 by the 3rd dc capacitor CA2 of series connection successively;
The appearance value of the first dc capacitor CA1 and the second dc capacitor CB1 is identical, and the appearance value of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 is identical;
The connecting line of the first dc capacitor CA1 and the second dc capacitor CB1 is connected with the connecting line of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 and is connected with direct current zero level end PV0;
The first ac output end of this inverter is connected with the output node that exchanges of inversion unit, and the second ac output end of this inverter is connected with the 5th direct-flow input end M5 of inversion unit.
Cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to needing in prior art to adopt equalizer circuit measure and larger RC absorbing circuit to prevent the two ends overvoltage of part diode, the disclosed single-phase semi-bridge five-electrical level inverter of the application semiconductor device is few, volume and cost have been reduced, reduced loss, improve efficient, and need not extra equalizer circuit measure.
Need to prove, during inverter work, five required level can provide by external direct current power supply, and DC power supply must not be one of composition of inverter, but depends on the circumstances.
Referring to Fig. 4, topological diagram for the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment two, five level of inverter can add that two DC/DC booster circuits obtain by two DC power supply PVM and PVN, concrete, two DC power supply PVM and PVN are connected in series, the first direct current positive electricity flush end PV1+, the first direct current negative electricity flush end PV1-and direct current zero level end PV0 are provided, two DC power supply PVM are connected with PVN and are connected a DC/DC booster circuit, and the second direct current positive electricity flush end PV2+ and the second direct current negative electricity flush end PV2-are provided.
With reference to figure 5, it shows the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three, with the difference of Fig. 4 be, the disclosed single-phase semi-bridge five-electrical level inverter of the application also comprises the filtration module that is formed by inductance L 501 and capacitor C 501, wherein: inductance L 501 is connected between the first ac output end of the interchange output node of inversion unit and this inverter, capacitor C 501 is connected between first ac output end and the second ac output end of this inverter, AC network V GBe connected in parallel on the two ends of capacitor C 501; By increasing the filtration module that is formed by inductance L 501 and capacitor C 501, reduced the harmonic wave in the five-electrical level inverter output current.
With reference to figure 6, it shows the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment four, to produce the first direct current positive electricity flush end PV1+ and the first direct current negative electricity flush end PV1-by DC power supply PVS with the difference of Fig. 4, dividing potential drop effect by the first capacitor C A1 and the second capacitor C B1 produces direct current zero level end PV0, DC power supply PVS two ends respectively connect a DC/DC booster circuit, generate the second direct current positive electricity flush end PV2+ and the second direct current negative electricity flush end PV2-.
Need to prove, two DC/DC booster circuits respectively with+1 level and-1 lever boosting to+2 level and-2 level, need to prove ,+2 level might not be+twice of 1 level,-2 level might not be the twices of-1 level, just represent different level.
The disclosed single-phase semi-bridge five-electrical level inverter of the application adopts the DC/DC booster circuit to construct in five level+2 level and-2 level, makes the DC input voitage scope of inverter wider.
The syndeton of single-phase semi-bridge five-electrical level inverter shown in Figure 6 and the syndeton of inductance and electric capacity and five-electrical level inverter as shown in Figure 5 and inductance and electric capacity is similar, no longer sets forth at this.
In sum, cause the problem that inverter is bulky, cost increases, loss is more and efficient is lower with respect to needing in prior art to adopt equalizer circuit measure and larger RC absorbing circuit to prevent the two ends overvoltage of part diode, the disclosed single-phase semi-bridge five-electrical level inverter of the application semiconductor device is few, volume and cost have been reduced, reduced loss, improve efficient, and need not extra equalizer circuit measure; In addition, by increasing the filtration module that is formed by inductance L 501 and capacitor C 501, reduced the harmonic wave in the five-electrical level inverter output current.
Corresponding to the disclosed five level inverse conversion unit of the application, the disclosed single-phase semi-bridge five-electrical level inverter of the application is when realizing the conversion of direct current and alternating current, comprise ten operation modes, below in conjunction with accompanying drawing 7 to Figure 16, ten kinds of operation modes of single-phase semi-bridge five-electrical level inverter shown in Figure 5 are carried out labor, the operation mode of all the other single-phase semi-bridge five-electrical level inverter embodiment similarly, wherein, the path of not conducting illustrates with fine line in the drawings, and the path of conducting illustrates with heavy line.
With reference to figure 7, it shows the topological diagram of the first operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The first operation mode is meritorious operation mode, the first switching element T 1 and the 9th diode DF1 conducting, and the path of electric current is: the 9th diode DF1-the first switching element T 1-inductance L 501-electrical network VG-the 9th diode DF1.
With reference to figure 8, it shows the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment 3 second operation modes.The second operation mode is meritorious operation mode, the 3rd switching element T A1 and the 5th diode DA3 conducting, and current path is: the first direct current positive electricity flush end PV1+-the 3rd switching element T A1-the 5th diode DA3-inductance L 501-electrical network V G-direct current zero level end PV0.
With reference to figure 9, it shows the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment 3 the 3rd operation mode.The 3rd operation mode is meritorious operation mode, the first switching element T 1 and the 4th switching element T A2 conducting, and current path is: second direct current positive electricity flush end PV2+-the 4th switching element T A2-the first switching element T 1-inductance L 501-electrical network V G-direct current zero level end PV0.
With reference to Figure 10, it shows the topological diagram of the 4th operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The 4th operation mode is idle operation mode, second switch device T2 and the tenth diode DF2 conducting, and current path is: inductance L 501-second switch device T2-the tenth diode DF2-electrical network V G-inductance L 501.
With reference to Figure 11, it shows the topological diagram of the 5th operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The 5th operation mode is meritorious operation mode, the 6th switching element T B1 and the 8th diode DB3 conducting, and current path is: inductance L 501-the 8th diode DB3-the 6th switching element T B1-the first direct current negative electricity flush end PV1-is to direct current zero level end PV0-electrical network V G-inductance L 501.
With reference to Figure 12, it shows the topological diagram of the 6th operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The 6th operation mode closes device TB2 conducting for meritorious operation mode, second switch device T2 and minion, and current path is: inductance L 501-second switch device T2-minion is closed device TB2-the second direct current negative electricity flush end PV2-to direct current zero level end PV0-electrical network V G-inductance L 501.
With reference to Figure 13, it shows the topological diagram of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment 3 the 7th operation mode.The 7th operation mode is idle operation mode, the first diode D1 and the 4th diode DA2 conducting, and current path is: inductance L 501-first diode D1-the 4th diode DA2-the second direct current positive electricity flush end PV2+ is to direct current zero level end PV0-electrical network V G-inductance L 501.
With reference to Figure 14, it shows the topological diagram of the 8th operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The 8th operation mode is idle operation mode, the 7th diode DB2 and the second diode D2 conducting, and current path is: second direct current negative electricity flush end PV2-to the seven diode DB2-the second diode D2-inductance L 501-electrical network V G-direct current zero level end PV0.
With reference to Figure 15, it shows the topological diagram of the 9th operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The 9th operation mode is idle operation mode, the 5th switching element T A3 and the 3rd diode DA1 conducting, and current path is: inductance L 501-the 5th switching element T A3-the 3rd diode DA1-the first direct current positive electricity flush end PV1+ is to direct current zero level end PV0-electrical network V G-inductance L 501.
With reference to Figure 16, it shows the topological diagram of the tenth operation mode of the disclosed single-phase semi-bridge five-electrical level inverter of the application embodiment three.The tenth operation mode is meritorious operation mode, the 8th switch device TB3 and the 6th diode DB1 conducting, and current path is: the first direct current negative electricity flush end PV1-to the six diode DB1-the 8th switch device TB3-inductance L 501-electrical network V G-direct current zero level end PV0.
Please again referring to Fig. 5, U is single-phase semi-bridge five-electrical level inverter output inverter voltage (the non-filtered module) the i.e. interchange output node and the voltage between the 5th direct-flow input end M5 of five level inverse conversion unit, and i is that the single-phase semi-bridge five-electrical level inverter is exported grid-connected current (passing through the electric current of filtration module).Referring to Figure 25, the waveform of U and i when it shows five-electrical level inverter in Fig. 5 and sends capacitive reactive power to electrical network, can be found out by waveform, because the disclosed five level inverse conversion power supplys of the application have ten kinds of operation modes, namely 2,1,0 ,-1 ,-2 level all have meritorious, reactive current path.When inverter is idle to the electrical network transmission, at the voltage zero-crossing point of power grid place, when namely inverter output inverter voltage U is switched to-1 level to 1 level or 0 level by 0 level, because 1 ,-1 level has the reactive current path, can find out, grid-connected current i is not distortion when zero crossing; When output inverter voltage U was switched to-2 level to 2 level or-1 level by 1 level, because 2 ,-2 level have idle path equally, grid-connected current i is distortion not; Can draw thus, when inverter was idle to the electrical network transmission, grid-connected current sine degree was good, and the THD value is very little.
In sum, the disclosed single-phase semi-bridge five-electrical level inverter of the application has ten kinds of operation modes, comprises five kinds of meritorious operation modes and five kinds of idle operation modes, satisfies AC load or AC network to idle demand, with respect to prior art, and applied range; And because each level has corresponding meritorious path and idle path, guaranteed inverter when transmission is meritorious or idle, THD is very little for output current.
With reference to Figure 18, it shows the topological diagram of the disclosed single-phase full bridge five-electrical level inverter of the application embodiment four, and five-electrical level inverter embodiment four comprises two inversion units as shown in figure 17: the first inversion unit and the second inversion unit;
The first direct current positive electricity flush end PV1+ is connected with each first direct-flow input end M1 of the first inversion unit and the second inversion unit;
The first direct current negative electricity flush end PV1-is connected with each second direct-flow input end M2 of the first inversion unit and the second inversion unit;
The second direct current positive electricity flush end PV2+ is connected with each the 3rd direct-flow input end M3 of the first inversion unit and the second inversion unit;
The second direct current negative electricity flush end PV2-is connected with each the 4th direct-flow input end M4 of the first inversion unit and the second inversion unit;
Direct current zero level end PV0 is connected with each the 5th direct-flow input end M5 of the first inversion unit and the second inversion unit;
The first direct current positive electricity flush end PV1+ is connected with the first direct current negative electricity flush end PV1-with the second dc capacitor CB1 by the first dc capacitor CA1 of series connection successively;
The second direct current positive electricity flush end PV2+ is connected with the second direct current negative electricity flush end PV2-with the 4th dc capacitor CB2 by the 3rd dc capacitor CA2 of series connection successively;
The appearance value of the first dc capacitor CA1 and the second dc capacitor CB1 is identical, and the appearance value of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 is identical;
The connecting line of the first dc capacitor CA1 and the second dc capacitor CB1 is connected with the connecting line of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 and is connected with direct current zero level end PV0;
The output node that respectively exchanges of the first inversion unit and the second inversion unit is connected with the second ac output end with the first ac output end of this inverter respectively.
Wherein, with reference to Figure 19, it shows the topological diagram of the disclosed single-phase full bridge five-electrical level inverter of the application embodiment five, is with the difference of as described in Figure 18 embodiment four, described five-electrical level inverter also comprises inductance L 1701, inductance L 1702 and capacitor C 1701, wherein:
Inductance L 1701 is connected between the first ac output end of the interchange output node of the first inversion unit and this inverter, inductance L 1702 is connected between the second ac output end of the interchange output node of the second inversion unit and this inverter, and capacitor C 1701 is connected between first ac output end and the second ac output end of this inverter.
In sum, the disclosed five-electrical level inverter of the application when guaranteeing to provide path for electric current, guarantees that the semiconductor device of whole inverter is few when realizing single-phase application, volume and cost have been reduced, reduce loss, improved efficient, and need not extra equalizer circuit measure; In addition, by increasing the filtration module that is formed by inductance and electric capacity, reduced the harmonic wave in the five-electrical level inverter output current.
With reference to Figure 20, the topological diagram that it shows the disclosed three-phase five-electrical level inverter of the application embodiment six comprises three as the inversion unit of Figure 17: the first inversion unit, the second inversion unit and the 3rd inversion unit;
The first direct current positive electricity flush end PV1+ is connected with each first direct-flow input end M1 of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The first direct current negative electricity flush end PV1-is connected with each second direct-flow input end M2 of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The second direct current positive electricity flush end PV2+ is connected with each the 3rd direct-flow input end M3 of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The second direct current negative electricity flush end PV2-is connected with each the 4th direct-flow input end M4 of the first inversion unit, the second inversion unit and the 3rd inversion unit;
Direct current zero level end PV0 is connected with each the 5th direct-flow input end M5 of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The first direct current positive electricity flush end PV1+ is connected with the first direct current negative electricity flush end PV1-with the second dc capacitor CB1 by the first dc capacitor CA1 of series connection successively;
The second direct current positive electricity flush end PV2+ is connected with the second direct current negative electricity flush end PV2-with the 4th dc capacitor CB2 by the 3rd dc capacitor CA2 of series connection successively;
The appearance value of the first dc capacitor CA1 and the second dc capacitor CB1 is identical, and the appearance value of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 is identical;
The connecting line of the first dc capacitor CA1 and the second dc capacitor CB1 is connected with the connecting line of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 and is connected with direct current zero level end PV0;
The output node that respectively exchanges in the first inversion unit, the second inversion unit and the 3rd inversion unit is connected with the first ac output end, the second ac output end and the 3rd ac output end of this inverter respectively.
Wherein, with reference to Figure 21, it shows the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment seven, be with the difference of the described embodiment six of Figure 20, described five-electrical level inverter also comprises inductance L 1901, inductance L 1902, inductance L 1903, capacitor C 1901, capacitor C 1902 and capacitor C 1903, wherein:
The interchange output node of the first inversion unit is connected with the output node that exchanges of the second inversion unit by inductance L 1901, capacitor C 1901, capacitor C 1902 and the inductance L 1902 of series connection successively; The interchange output node of the 3rd inversion unit is connected with the connecting line of capacitor C 1901 with capacitor C 1902 with capacitor C 1903 by the inductance L 1903 of series connection successively; The connecting line of inductance L 1901 and capacitor C 1901 is connected with the first ac output end of this inverter, the connecting line of inductance L 1902 and capacitor C 1902 is connected with the second ac output end of this inverter, and the connecting line of inductance L 1903 and capacitor C 1903 is connected with the 3rd ac output end of this inverter.
Need to prove, five-electrical level inverter embodiment six and seven is three-phase three-wire system (three brachium pontis) five-electrical level inverter.
With reference to Figure 22, it shows the topological diagram of the embodiment of the present application eight, is with the difference of embodiment seven as described in Figure 21:
The connecting line of capacitor C 1901, capacitor C 1902 and capacitor C 1903 is connected with direct current zero level end PV0.Need to prove, five-electrical level inverter as shown in figure 20 is three-phase four-wire system (three brachium pontis) five-electrical level inverter.
With reference to Figure 23, the topological diagram that it shows the disclosed three-phase five-electrical level inverter of the application embodiment nine (four brachium pontis) comprises four as the inversion unit of Figure 17: the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The first direct current positive electricity flush end PV1+ is connected with each first direct-flow input end M1 of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The first direct current negative electricity flush end PV1-is connected with each second direct-flow input end M2 of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The second direct current positive electricity flush end PV2+ is connected with each the 3rd direct-flow input end M3 of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The second direct current negative electricity flush end PV2-is connected with each the 4th direct-flow input end M4 of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
Direct current zero level end PV0 is connected with each the 5th direct-flow input end M5 of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The first direct current positive electricity flush end PV1+ is connected with the first direct current negative electricity flush end PV1-with the second dc capacitor CB1 by the first dc capacitor CA1 of series connection successively;
The second direct current positive electricity flush end PV2+ is connected with the second direct current negative electricity flush end PV2-with the 4th dc capacitor CB2 by the 3rd dc capacitor CA2 of series connection successively;
The appearance value of the first dc capacitor CA1 and the second dc capacitor CB1 is identical, and the appearance value of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 is identical;
The connecting line of the first dc capacitor CA1 and the second dc capacitor CB1 is connected with the connecting line of the 3rd dc capacitor CA2 and the 4th dc capacitor CB2 and is connected with direct current zero level end PV0;
The output node that respectively exchanges in the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit is connected with the first ac output end, the second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.
Wherein, with reference to Figure 24, it shows the topological diagram of the disclosed three-phase five-electrical level inverter of the application embodiment ten, be with the difference of as described in Figure 23 embodiment nine, described five-electrical level inverter also comprises inductance L 2201, inductance L 2202, inductance L 2203, capacitor C 2201, capacitor C 2202 and capacitor C 2203, wherein:
The interchange output node of the second inversion unit is connected with the output node that exchanges of the 3rd inversion unit by inductance L 2201, capacitor C 2201, capacitor C 2202 and the inductance L 2202 of series connection successively;
The interchange output node of the 4th inversion unit is connected with the connecting line of capacitor C 2201 with capacitor C 2202 with capacitor C 2203 by the inductance L 2203 of series connection successively;
The interchange output node of the first inversion unit is connected with the connecting line of capacitor C 2201, capacitor C 2202;
The connecting line of inductance L 2201, capacitor C 2201 is connected with the first ac output end of this inverter, the connecting line of capacitor C 2202 and inductance L 2202 is connected with the second ac output end of this inverter, and the connecting line of inductance L 2203 and capacitor C 2203 is connected with the 3rd ac output end of this inverter.
In sum, the disclosed five-electrical level inverter of the application when guaranteeing to provide path for electric current, guarantees that the semiconductor device of whole inverter is few when realizing three-phase applications, volume and cost have been reduced, reduce loss, improved efficient, and need not extra equalizer circuit measure; In addition, by increasing the filtration module that is formed by inductance and electric capacity, reduced the harmonic wave in the five-electrical level inverter output current.
Need to prove, each embodiment in this specification all adopts the mode of going forward one by one to describe, and what each embodiment stressed is and the difference of other embodiment that between each embodiment, identical similar part is mutually referring to getting final product.The five-electrical level inverter in this specification for example, comprise single-phase semi-bridge five-electrical level inverter, single-phase full bridge five-electrical level inverter, phase three-wire three five-electrical level inverter, three-phase and four-line five-electrical level inverter etc., in each inverter, the driving signal of the operation mode of the driving signal of the operation mode of each five level inverse conversion unit and switching device and five level topology unit shown in Figure 2 and switching device is consistent.
At last, also need to prove, in this article, relational terms such as the first and second grades only is used for an entity or operation are separated with another entity or operating space, and not necessarily requires or hint and have the relation of any this reality or sequentially between these entities or operation.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thereby make the process, method, article or the equipment that comprise a series of key elements not only comprise those key elements, but also comprise other key elements of clearly not listing, or also be included as the intrinsic key element of this process, method, article or equipment.In the situation that not more restrictions, the key element that is limited by statement " comprising ... ", and be not precluded within process, method, article or the equipment that comprises described key element and also have other identical element.
Above the disclosed a kind of five level inverse conversion unit of the application and five-electrical level inverter are described in detail, used specific case herein the application's principle and execution mode are set forth, the explanation of above embodiment just is used for helping to understand the application's method and core concept thereof; Simultaneously, for one of ordinary skill in the art, the thought according to the application all will change in specific embodiments and applications, and in sum, this description should not be construed as the restriction to the application.

Claims (10)

1. level inverse conversion unit, it is characterized in that, comprise that the first switching device, the 3rd switching device, the 4th switching device, the 5th switching device, second switch device, the 6th switching device, minion close device, the 8th switch device, the 9th diode and the tenth diode; Diode of the equal reverse parallel connection of each described switching device is respectively the first diode, the 3rd diode, the 4th diode, the 5th diode, the second diode, the 6th diode, the 7th diode, the 8th diode;
The first direct-flow input end of this inversion unit is connected with the first end of the 3rd switching device;
The second direct-flow input end is connected with the second end of the 6th switching device;
The 3rd direct-flow input end is connected with the first end of the 4th switching device;
The 4th direct-flow input end is connected with the second end that minion is closed device;
The 5th direct-flow input end is connected with the anode of the 9th diode and the negative electrode of the tenth diode;
The second end of the 4th switching device is connected with the negative electrode of the first end of the first switching device and the 9th diode;
The second end of the 3rd switching device is connected with the second end of the 5th switching device;
The first end of the 6th switching device is connected with the first end of the 8th switch device;
The first end that minion is closed device is connected with the second end of second switch device and the anode of the tenth diode;
The second end of the second end of the first switching device, the first end of the 5th switching device, the 8th switch device, the first end of second switch device are connected, and are connected with the output node that exchanges of this inversion unit.
2. five level inverse conversion unit according to claim 1, is characterized in that,
Corresponding varying level is counted in situation, and the driving signal of each switching device of this five level inverse conversion unit is respectively:
+ 2 level: the driving signal of the first switching device and the 4th switching device is high level, and the driving signal of the 3rd switching device is high level or low level, and the driving signal of rest switch device is low level;
+ 1 level: the driving signal of the first switching device, the 3rd switching device and the 5th switching device is high level, and the driving signal of rest switch device is low level;
0 level: the driving signal of the first switching device, second switch device is high level, and the driving signal of rest switch device is low level;
-1 level: the driving signal of second switch device, the 6th switching device, the 8th switch device is high level, and the driving signal of rest switch device is low level;
-2 level: the driving signal that second switch device, minion are closed device is high level, and the driving signal of the 6th switching device is high level or low level, and the driving signal of rest switch device is low level.
3. a five-electrical level inverter, is characterized in that, comprises an inversion unit as claimed in claim 1 or 2, wherein:
The first direct current positive electricity flush end is connected with the first direct-flow input end, the second direct current positive electricity flush end is connected with the 3rd direct-flow input end, direct current zero level end is connected with the 5th direct-flow input end, the first direct current negative electricity flush end is connected with the second direct-flow input end, and the second direct current negative electricity flush end is connected with the 4th direct-flow input end;
The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively;
The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively;
The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical;
The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor;
The first ac output end of this inverter is connected with the output node that exchanges of inversion unit, and the second ac output end of this inverter is connected with the 5th direct-flow input end of inversion unit.
4. five-electrical level inverter according to claim 3, it is characterized in that, also comprise the filtration module that is formed by inductance L 501 and capacitor C 501, wherein: inductance L 501 is connected between the first ac output end of the interchange output node of inversion unit and this inverter, and capacitor C 501 is connected between first ac output end and the second ac output end of this inverter.
5. a five-electrical level inverter, is characterized in that, comprises two inversion units as claimed in claim 1 or 2: the first inversion unit and the second inversion unit;
The first direct current positive electricity flush end is connected with each first direct-flow input end of the first inversion unit and the second inversion unit;
The first direct current negative electricity flush end is connected with each second direct-flow input end of the first inversion unit and the second inversion unit;
The second direct current positive electricity flush end is connected with each the 3rd direct-flow input end of the first inversion unit and the second inversion unit;
The second direct current negative electricity flush end is connected with each the 4th direct-flow input end of the first inversion unit and the second inversion unit;
Direct current zero level end is connected with each the 5th direct-flow input end of the first inversion unit and the second inversion unit;
The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively;
The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively;
The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical;
The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor;
The output node that respectively exchanges of the first inversion unit and the second inversion unit is connected with the second ac output end with the first ac output end of this inverter respectively.
6. five-electrical level inverter according to claim 5, is characterized in that, also comprises inductance L 1701, inductance L 1702 and capacitor C 1701, wherein:
Inductance L 1701 is connected between the first ac output end of the interchange output node of the first inversion unit and this inverter, inductance L 1702 is connected between the second ac output end of the interchange output node of the second inversion unit and this inverter, and capacitor C 1701 is connected between first ac output end and the second ac output end of this inverter.
7. a five-electrical level inverter, is characterized in that, comprises three inversion units as claimed in claim 1 or 2: the first inversion unit, the second inversion unit and the 3rd inversion unit;
The first direct current positive electricity flush end is connected with each first direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The first direct current negative electricity flush end is connected with each second direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The second direct current positive electricity flush end is connected with each the 3rd direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The second direct current negative electricity flush end is connected with each the 4th direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit;
Direct current zero level end is connected with each the 5th direct-flow input end of the first inversion unit, the second inversion unit and the 3rd inversion unit;
The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively;
The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively;
The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical;
The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor;
The output node that respectively exchanges in the first inversion unit, the second inversion unit and the 3rd inversion unit is connected with the first ac output end, the second ac output end and the 3rd ac output end of this inverter respectively.
8. five-electrical level inverter according to claim 7, is characterized in that, also comprises inductance L 1901, inductance L 1902, inductance L 1903, capacitor C 1901, capacitor C 1902 and capacitor C 1903, wherein:
The interchange output node of the first inversion unit is connected with the output node that exchanges of the second inversion unit by inductance L 1901, capacitor C 1901, capacitor C 1902 and the inductance L 1902 of series connection successively; The interchange output node of the 3rd inversion unit is connected with the connecting line of capacitor C 1901 with capacitor C 1902 with capacitor C 1903 by the inductance L 1903 of series connection successively; The connecting line of inductance L 1901 and capacitor C 1901 is connected with the first ac output end of this inverter, the connecting line of inductance L 1902 and capacitor C 1902 is connected with the second ac output end of this inverter, and the connecting line of inductance L 1903 and capacitor C 1903 is connected with the 3rd ac output end of this inverter.
9. a five-electrical level inverter, is characterized in that, comprises four inversion units as claimed in claim 1 or 2: the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The first direct current positive electricity flush end is connected with each first direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The first direct current negative electricity flush end is connected with each second direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The second direct current positive electricity flush end is connected with each the 3rd direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The second direct current negative electricity flush end is connected with each the 4th direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
Direct current zero level end is connected with each the 5th direct-flow input end of the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit;
The first direct current positive electricity flush end is connected with the first direct current negative electricity flush end with the second dc capacitor by the first dc capacitor of series connection successively;
The second direct current positive electricity flush end is connected with the second direct current negative electricity flush end with the 4th dc capacitor by the 3rd dc capacitor of series connection successively;
The appearance value of the first dc capacitor and the second dc capacitor is identical, and the appearance value of the 3rd dc capacitor and the 4th dc capacitor is identical;
The connecting line of the first dc capacitor and the second dc capacitor is connected and is connected with direct current zero level end with the connecting line of the 3rd dc capacitor and the 4th dc capacitor;
The output node that respectively exchanges in the first inversion unit, the second inversion unit, the 3rd inversion unit and the 4th inversion unit is connected with the first ac output end, the second ac output end, the 3rd ac output end and the 4th ac output end of this inverter respectively.
10. five-electrical level inverter according to claim 9, is characterized in that, also comprises inductance L 2201, inductance L 2202, inductance L 2203, capacitor C 2201, capacitor C 2202 and capacitor C 2203, wherein:
The interchange output node of the second inversion unit is connected with the output node that exchanges of the 3rd inversion unit by inductance L 2201, capacitor C 2201, capacitor C 2202 and the inductance L 2202 of series connection successively;
The interchange output node of the 4th inversion unit is connected with the connecting line of capacitor C 2201 with capacitor C 2202 with capacitor C 2203 by the inductance L 2203 of series connection successively;
The interchange output node of the first inversion unit is connected with the connecting line of capacitor C 2201, capacitor C 2202;
The connecting line of inductance L 2201, capacitor C 2201 is connected with the first ac output end of this inverter, the connecting line of capacitor C 2202 and inductance L 2202 is connected with the second ac output end of this inverter, and the connecting line of inductance L 2203 and capacitor C 2203 is connected with the 3rd ac output end of this inverter.
CN 201220531871 2012-10-17 2012-10-17 Five-level inversion unit and five-level inverter Expired - Lifetime CN202949375U (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104467016A (en) * 2014-12-18 2015-03-25 阳光电源股份有限公司 Pre-charging control method and system for five-level photovoltaic inverter
US10581313B2 (en) 2018-02-28 2020-03-03 Eaton Intelligent Power Limited Hybrid I-T type multi-level converters

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104467016A (en) * 2014-12-18 2015-03-25 阳光电源股份有限公司 Pre-charging control method and system for five-level photovoltaic inverter
US10581313B2 (en) 2018-02-28 2020-03-03 Eaton Intelligent Power Limited Hybrid I-T type multi-level converters
US11095232B2 (en) 2018-02-28 2021-08-17 Eaton Intelligent Power Limited Hybrid I-T type multi-level converters

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